arch/alpha/kernel/sys_eiger.c

   1 /*
   2  *      linux/arch/alpha/kernel/sys_eiger.c
   3  *
   4  *      Copyright (C) 1995 David A Rusling
   5  *      Copyright (C) 1996, 1999 Jay A Estabrook
   6  *      Copyright (C) 1998, 1999 Richard Henderson
   7  *      Copyright (C) 1999 Iain Grant
   8  *
   9  * Code supporting the EIGER (EV6+TSUNAMI).
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/mm.h>
  15 #include <linux/sched.h>
  16 #include <linux/pci.h>
  17 #include <linux/init.h>
  18 #include <linux/bitops.h>
  19
  20 #include <asm/ptrace.h>
  21 #include <asm/system.h>
  22 #include <asm/dma.h>
  23 #include <asm/irq.h>
  24 #include <asm/mmu_context.h>
  25 #include <asm/io.h>
  26 #include <asm/pci.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/core_tsunami.h>
  29 #include <asm/hwrpb.h>
  30 #include <asm/tlbflush.h>
  31
  32 #include "proto.h"
  33 #include "irq_impl.h"
  34 #include "pci_impl.h"
  35 #include "machvec_impl.h"
  36
  37
  38 /* Note that this interrupt code is identical to TAKARA.  */
  39
  40 /* Note mask bit is true for DISABLED irqs.  */
  41 static unsigned long cached_irq_mask[2] = { -1, -1 };
  42
  43 static inline void
  44 eiger_update_irq_hw(unsigned long irq, unsigned long mask)
  45 {
  46         int regaddr;
  47
  48         mask = (irq >= 64 ? mask << 16 : mask >> ((irq - 16) & 0x30));
  49         regaddr = 0x510 + (((irq - 16) >> 2) & 0x0c);
  50         outl(mask & 0xffff0000UL, regaddr);
  51 }
  52
  53 static inline void
  54 eiger_enable_irq(struct irq_data *d)
  55 {
  56         unsigned int irq = d->irq;
  57         unsigned long mask;
  58         mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63)));
  59         eiger_update_irq_hw(irq, mask);
  60 }
  61
  62 static void
  63 eiger_disable_irq(struct irq_data *d)
  64 {
  65         unsigned int irq = d->irq;
  66         unsigned long mask;
  67         mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63));
  68         eiger_update_irq_hw(irq, mask);
  69 }
  70
  71 static struct irq_chip eiger_irq_type = {
  72         .name           = "EIGER",
  73         .irq_unmask     = eiger_enable_irq,
  74         .irq_mask       = eiger_disable_irq,
  75         .irq_mask_ack   = eiger_disable_irq,
  76 };
  77
  78 static void
  79 eiger_device_interrupt(unsigned long vector)
  80 {
  81         unsigned intstatus;
  82
  83         /*
  84          * The PALcode will have passed us vectors 0x800 or 0x810,
  85          * which are fairly arbitrary values and serve only to tell
  86          * us whether an interrupt has come in on IRQ0 or IRQ1. If
  87          * it's IRQ1 it's a PCI interrupt; if it's IRQ0, it's
  88          * probably ISA, but PCI interrupts can come through IRQ0
  89          * as well if the interrupt controller isn't in accelerated
  90          * mode.
  91          *
  92          * OTOH, the accelerator thing doesn't seem to be working
  93          * overly well, so what we'll do instead is try directly
  94          * examining the Master Interrupt Register to see if it's a
  95          * PCI interrupt, and if _not_ then we'll pass it on to the
  96          * ISA handler.
  97          */
  98
  99         intstatus = inw(0x500) & 15;
 100         if (intstatus) {
 101                 /*
 102                  * This is a PCI interrupt. Check each bit and
 103                  * despatch an interrupt if it's set.
 104                  */
 105
 106                 if (intstatus & 8) handle_irq(16+3);
 107                 if (intstatus & 4) handle_irq(16+2);
 108                 if (intstatus & 2) handle_irq(16+1);
 109                 if (intstatus & 1) handle_irq(16+0);
 110         } else {
 111                 isa_device_interrupt(vector);
 112         }
 113 }
 114
 115 static void
 116 eiger_srm_device_interrupt(unsigned long vector)
 117 {
 118         int irq = (vector - 0x800) >> 4;
 119         handle_irq(irq);
 120 }
 121
 122 static void __init
 123 eiger_init_irq(void)
 124 {
 125         long i;
 126
 127         outb(0, DMA1_RESET_REG);
 128         outb(0, DMA2_RESET_REG);
 129         outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
 130         outb(0, DMA2_MASK_REG);
 131
 132         if (alpha_using_srm)
 133                 alpha_mv.device_interrupt = eiger_srm_device_interrupt;
 134
 135         for (i = 16; i < 128; i += 16)
 136                 eiger_update_irq_hw(i, -1);
 137
 138         init_i8259a_irqs();
 139
 140         for (i = 16; i < 128; ++i) {
 141                 irq_set_chip_and_handler(i, &eiger_irq_type, handle_level_irq);
 142                 irq_set_status_flags(i, IRQ_LEVEL);
 143         }
 144 }
 145
 146 static int __init
 147 eiger_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 148 {
 149         u8 irq_orig;
 150
 151         /* The SRM console has already calculated out the IRQ value's for
 152            option cards. As this works lets just read in the value already
 153            set and change it to a useable value by Linux.
 154
 155            All the IRQ values generated by the console are greater than 90,
 156            so we subtract 80 because it is (90 - allocated ISA IRQ's).  */
 157
 158         pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq_orig);
 159
 160         return irq_orig - 0x80;
 161 }
 162
 163 static u8 __init
 164 eiger_swizzle(struct pci_dev *dev, u8 *pinp)
 165 {
 166         struct pci_controller *hose = dev->sysdata;
 167         int slot, pin = *pinp;
 168         int bridge_count = 0;
 169
 170         /* Find the number of backplane bridges.  */
 171         int backplane = inw(0x502) & 0x0f;
 172
 173         switch (backplane)
 174         {
 175            case 0x00: bridge_count = 0; break; /* No bridges */
 176            case 0x01: bridge_count = 1; break; /* 1 */
 177            case 0x03: bridge_count = 2; break; /* 2 */
 178            case 0x07: bridge_count = 3; break; /* 3 */
 179            case 0x0f: bridge_count = 4; break; /* 4 */
 180         };
 181
 182         slot = PCI_SLOT(dev->devfn);
 183         while (dev->bus->self) {
 184                 /* Check for built-in bridges on hose 0. */
 185                 if (hose->index == 0
 186                     && (PCI_SLOT(dev->bus->self->devfn)
 187                         > 20 - bridge_count)) {
 188                         slot = PCI_SLOT(dev->devfn);
 189                         break;
 190                 }
 191                 /* Must be a card-based bridge.  */
 192                 pin = pci_swizzle_interrupt_pin(dev, pin);
 193
 194                 /* Move up the chain of bridges.  */
 195                 dev = dev->bus->self;
 196         }
 197         *pinp = pin;
 198         return slot;
 199 }
 200
 201 /*
 202  * The System Vectors
 203  */
 204
 205 struct alpha_machine_vector eiger_mv __initmv = {
 206         .vector_name            = "Eiger",
 207         DO_EV6_MMU,
 208         DO_DEFAULT_RTC,
 209         DO_TSUNAMI_IO,
 210         .machine_check          = tsunami_machine_check,
 211         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 212         .min_io_address         = DEFAULT_IO_BASE,
 213         .min_mem_address        = DEFAULT_MEM_BASE,
 214         .pci_dac_offset         = TSUNAMI_DAC_OFFSET,
 215
 216         .nr_irqs                = 128,
 217         .device_interrupt       = eiger_device_interrupt,
 218
 219         .init_arch              = tsunami_init_arch,
 220         .init_irq               = eiger_init_irq,
 221         .init_rtc               = common_init_rtc,
 222         .init_pci               = common_init_pci,
 223         .kill_arch              = tsunami_kill_arch,
 224         .pci_map_irq            = eiger_map_irq,
 225         .pci_swizzle            = eiger_swizzle,
 226 };
 227 ALIAS_MV(eiger)