| blob | dedb8852a646db285567557091469e77c67e5f15 |
1 config ARM
2 bool
3 default y
4 select HAVE_AOUT
5 select HAVE_DMA_API_DEBUG
6 select HAVE_IDE if PCI || ISA || PCMCIA
7 select HAVE_MEMBLOCK
8 select RTC_LIB
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
12 select HAVE_ARCH_KGDB
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
20 select HAVE_GENERIC_DMA_COHERENT
21 select HAVE_KERNEL_GZIP
22 select HAVE_KERNEL_LZO
23 select HAVE_KERNEL_LZMA
24 select HAVE_IRQ_WORK
25 select HAVE_PERF_EVENTS
26 select PERF_USE_VMALLOC
27 select HAVE_REGS_AND_STACK_ACCESS_API
28 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
29 select HAVE_C_RECORDMCOUNT
30 select HAVE_GENERIC_HARDIRQS
31 select HAVE_SPARSE_IRQ
32 select GENERIC_IRQ_SHOW
33 select CPU_PM if (SUSPEND || CPU_IDLE)
34 select GENERIC_PCI_IOMAP
35 help
36 The ARM series is a line of low-power-consumption RISC chip designs
37 licensed by ARM Ltd and targeted at embedded applications and
38 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
39 manufactured, but legacy ARM-based PC hardware remains popular in
40 Europe. There is an ARM Linux project with a web page at
41 <http://www.arm.linux.org.uk/>.
43 config ARM_HAS_SG_CHAIN
44 bool
46 config HAVE_PWM
47 bool
49 config MIGHT_HAVE_PCI
50 bool
52 config SYS_SUPPORTS_APM_EMULATION
53 bool
55 config HAVE_SCHED_CLOCK
56 bool
58 config GENERIC_GPIO
59 bool
61 config ARCH_USES_GETTIMEOFFSET
62 bool
63 default n
65 config GENERIC_CLOCKEVENTS
66 bool
68 config GENERIC_CLOCKEVENTS_BROADCAST
69 bool
70 depends on GENERIC_CLOCKEVENTS
71 default y if SMP
73 config KTIME_SCALAR
74 bool
75 default y
77 config HAVE_TCM
78 bool
79 select GENERIC_ALLOCATOR
81 config HAVE_PROC_CPU
82 bool
84 config NO_IOPORT
85 bool
87 config EISA
88 bool
89 ---help---
90 The Extended Industry Standard Architecture (EISA) bus was
91 developed as an open alternative to the IBM MicroChannel bus.
93 The EISA bus provided some of the features of the IBM MicroChannel
94 bus while maintaining backward compatibility with cards made for
95 the older ISA bus. The EISA bus saw limited use between 1988 and
96 1995 when it was made obsolete by the PCI bus.
98 Say Y here if you are building a kernel for an EISA-based machine.
100 Otherwise, say N.
102 config SBUS
103 bool
105 config MCA
106 bool
107 help
108 MicroChannel Architecture is found in some IBM PS/2 machines and
109 laptops. It is a bus system similar to PCI or ISA. See
110 <file:Documentation/mca.txt> (and especially the web page given
111 there) before attempting to build an MCA bus kernel.
113 config STACKTRACE_SUPPORT
114 bool
115 default y
117 config HAVE_LATENCYTOP_SUPPORT
118 bool
119 depends on !SMP
120 default y
122 config LOCKDEP_SUPPORT
123 bool
124 default y
126 config TRACE_IRQFLAGS_SUPPORT
127 bool
128 default y
130 config HARDIRQS_SW_RESEND
131 bool
132 default y
134 config GENERIC_IRQ_PROBE
135 bool
136 default y
138 config GENERIC_LOCKBREAK
139 bool
140 default y
141 depends on SMP && PREEMPT
143 config RWSEM_GENERIC_SPINLOCK
144 bool
145 default y
147 config RWSEM_XCHGADD_ALGORITHM
148 bool
150 config ARCH_HAS_ILOG2_U32
151 bool
153 config ARCH_HAS_ILOG2_U64
154 bool
156 config ARCH_HAS_CPUFREQ
157 bool
158 help
159 Internal node to signify that the ARCH has CPUFREQ support
160 and that the relevant menu configurations are displayed for
161 it.
163 config ARCH_HAS_CPU_IDLE_WAIT
164 def_bool y
166 config GENERIC_HWEIGHT
167 bool
168 default y
170 config GENERIC_CALIBRATE_DELAY
171 bool
172 default y
174 config ARCH_MAY_HAVE_PC_FDC
175 bool
177 config ZONE_DMA
178 bool
180 config NEED_DMA_MAP_STATE
181 def_bool y
183 config GENERIC_ISA_DMA
184 bool
186 config FIQ
187 bool
189 config ARCH_MTD_XIP
190 bool
192 config VECTORS_BASE
193 hex
194 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
195 default DRAM_BASE if REMAP_VECTORS_TO_RAM
196 default 0x00000000
197 help
198 The base address of exception vectors.
200 config ARM_PATCH_PHYS_VIRT
201 bool "Patch physical to virtual translations at runtime" if EMBEDDED
202 default y
203 depends on !XIP_KERNEL && MMU
204 depends on !ARCH_REALVIEW || !SPARSEMEM
205 help
206 Patch phys-to-virt and virt-to-phys translation functions at
207 boot and module load time according to the position of the
208 kernel in system memory.
210 This can only be used with non-XIP MMU kernels where the base
211 of physical memory is at a 16MB boundary.
213 Only disable this option if you know that you do not require
214 this feature (eg, building a kernel for a single machine) and
215 you need to shrink the kernel to the minimal size.
217 config NEED_MACH_MEMORY_H
218 bool
219 help
220 Select this when mach/memory.h is required to provide special
221 definitions for this platform. The need for mach/memory.h should
222 be avoided when possible.
224 config PHYS_OFFSET
225 hex "Physical address of main memory" if MMU
226 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
227 default DRAM_BASE if !MMU
228 help
229 Please provide the physical address corresponding to the
230 location of main memory in your system.
232 config GENERIC_BUG
233 def_bool y
234 depends on BUG
236 source "init/Kconfig"
238 source "kernel/Kconfig.freezer"
240 menu "System Type"
242 config MMU
243 bool "MMU-based Paged Memory Management Support"
244 default y
245 help
246 Select if you want MMU-based virtualised addressing space
247 support by paged memory management. If unsure, say 'Y'.
249 #
250 # The "ARM system type" choice list is ordered alphabetically by option
251 # text. Please add new entries in the option alphabetic order.
252 #
253 choice
254 prompt "ARM system type"
255 default ARCH_VERSATILE
257 config ARCH_INTEGRATOR
258 bool "ARM Ltd. Integrator family"
259 select ARM_AMBA
260 select ARCH_HAS_CPUFREQ
261 select CLKDEV_LOOKUP
262 select HAVE_MACH_CLKDEV
263 select HAVE_TCM
264 select ICST
265 select GENERIC_CLOCKEVENTS
266 select PLAT_VERSATILE
267 select PLAT_VERSATILE_FPGA_IRQ
268 select NEED_MACH_MEMORY_H
269 help
270 Support for ARM's Integrator platform.
272 config ARCH_REALVIEW
273 bool "ARM Ltd. RealView family"
274 select ARM_AMBA
275 select CLKDEV_LOOKUP
276 select HAVE_MACH_CLKDEV
277 select ICST
278 select GENERIC_CLOCKEVENTS
279 select ARCH_WANT_OPTIONAL_GPIOLIB
280 select PLAT_VERSATILE
281 select PLAT_VERSATILE_CLCD
282 select ARM_TIMER_SP804
283 select GPIO_PL061 if GPIOLIB
284 select NEED_MACH_MEMORY_H
285 help
286 This enables support for ARM Ltd RealView boards.
288 config ARCH_VERSATILE
289 bool "ARM Ltd. Versatile family"
290 select ARM_AMBA
291 select ARM_VIC
292 select CLKDEV_LOOKUP
293 select HAVE_MACH_CLKDEV
294 select ICST
295 select GENERIC_CLOCKEVENTS
296 select ARCH_WANT_OPTIONAL_GPIOLIB
297 select PLAT_VERSATILE
298 select PLAT_VERSATILE_CLCD
299 select PLAT_VERSATILE_FPGA_IRQ
300 select ARM_TIMER_SP804
301 help
302 This enables support for ARM Ltd Versatile board.
304 config ARCH_VEXPRESS
305 bool "ARM Ltd. Versatile Express family"
306 select ARCH_WANT_OPTIONAL_GPIOLIB
307 select ARM_AMBA
308 select ARM_TIMER_SP804
309 select CLKDEV_LOOKUP
310 select HAVE_MACH_CLKDEV
311 select GENERIC_CLOCKEVENTS
312 select HAVE_CLK
313 select HAVE_PATA_PLATFORM
314 select ICST
315 select PLAT_VERSATILE
316 select PLAT_VERSATILE_CLCD
317 help
318 This enables support for the ARM Ltd Versatile Express boards.
320 config ARCH_AT91
321 bool "Atmel AT91"
322 select ARCH_REQUIRE_GPIOLIB
323 select HAVE_CLK
324 select CLKDEV_LOOKUP
325 help
326 This enables support for systems based on the Atmel AT91RM9200,
327 AT91SAM9 and AT91CAP9 processors.
329 config ARCH_BCMRING
330 bool "Broadcom BCMRING"
331 depends on MMU
332 select CPU_V6
333 select ARM_AMBA
334 select ARM_TIMER_SP804
335 select CLKDEV_LOOKUP
336 select GENERIC_CLOCKEVENTS
337 select ARCH_WANT_OPTIONAL_GPIOLIB
338 help
339 Support for Broadcom's BCMRing platform.
341 config ARCH_HIGHBANK
342 bool "Calxeda Highbank-based"
343 select ARCH_WANT_OPTIONAL_GPIOLIB
344 select ARM_AMBA
345 select ARM_GIC
346 select ARM_TIMER_SP804
347 select CACHE_L2X0
348 select CLKDEV_LOOKUP
349 select CPU_V7
350 select GENERIC_CLOCKEVENTS
351 select HAVE_ARM_SCU
352 select HAVE_SMP
353 select USE_OF
354 help
355 Support for the Calxeda Highbank SoC based boards.
357 config ARCH_CLPS711X
358 bool "Cirrus Logic CLPS711x/EP721x-based"
359 select CPU_ARM720T
360 select ARCH_USES_GETTIMEOFFSET
361 select NEED_MACH_MEMORY_H
362 help
363 Support for Cirrus Logic 711x/721x based boards.
365 config ARCH_CNS3XXX
366 bool "Cavium Networks CNS3XXX family"
367 select CPU_V6K
368 select GENERIC_CLOCKEVENTS
369 select ARM_GIC
370 select MIGHT_HAVE_CACHE_L2X0
371 select MIGHT_HAVE_PCI
372 select PCI_DOMAINS if PCI
373 help
374 Support for Cavium Networks CNS3XXX platform.
376 config ARCH_GEMINI
377 bool "Cortina Systems Gemini"
378 select CPU_FA526
379 select ARCH_REQUIRE_GPIOLIB
380 select ARCH_USES_GETTIMEOFFSET
381 help
382 Support for the Cortina Systems Gemini family SoCs
384 config ARCH_PRIMA2
385 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
386 select CPU_V7
387 select NO_IOPORT
388 select GENERIC_CLOCKEVENTS
389 select CLKDEV_LOOKUP
390 select GENERIC_IRQ_CHIP
391 select MIGHT_HAVE_CACHE_L2X0
392 select USE_OF
393 select ZONE_DMA
394 help
395 Support for CSR SiRFSoC ARM Cortex A9 Platform
397 config ARCH_EBSA110
398 bool "EBSA-110"
399 select CPU_SA110
400 select ISA
401 select NO_IOPORT
402 select ARCH_USES_GETTIMEOFFSET
403 select NEED_MACH_MEMORY_H
404 help
405 This is an evaluation board for the StrongARM processor available
406 from Digital. It has limited hardware on-board, including an
407 Ethernet interface, two PCMCIA sockets, two serial ports and a
408 parallel port.
410 config ARCH_EP93XX
411 bool "EP93xx-based"
412 select CPU_ARM920T
413 select ARM_AMBA
414 select ARM_VIC
415 select CLKDEV_LOOKUP
416 select ARCH_REQUIRE_GPIOLIB
417 select ARCH_HAS_HOLES_MEMORYMODEL
418 select ARCH_USES_GETTIMEOFFSET
419 select NEED_MACH_MEMORY_H
420 help
421 This enables support for the Cirrus EP93xx series of CPUs.
423 config ARCH_FOOTBRIDGE
424 bool "FootBridge"
425 select CPU_SA110
426 select FOOTBRIDGE
427 select GENERIC_CLOCKEVENTS
428 select HAVE_IDE
429 select NEED_MACH_MEMORY_H
430 help
431 Support for systems based on the DC21285 companion chip
432 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
434 config ARCH_MXC
435 bool "Freescale MXC/iMX-based"
436 select GENERIC_CLOCKEVENTS
437 select ARCH_REQUIRE_GPIOLIB
438 select CLKDEV_LOOKUP
439 select CLKSRC_MMIO
440 select GENERIC_IRQ_CHIP
441 select HAVE_SCHED_CLOCK
442 select MULTI_IRQ_HANDLER
443 help
444 Support for Freescale MXC/iMX-based family of processors
446 config ARCH_MXS
447 bool "Freescale MXS-based"
448 select GENERIC_CLOCKEVENTS
449 select ARCH_REQUIRE_GPIOLIB
450 select CLKDEV_LOOKUP
451 select CLKSRC_MMIO
452 select HAVE_CLK_PREPARE
453 help
454 Support for Freescale MXS-based family of processors
456 config ARCH_NETX
457 bool "Hilscher NetX based"
458 select CLKSRC_MMIO
459 select CPU_ARM926T
460 select ARM_VIC
461 select GENERIC_CLOCKEVENTS
462 help
463 This enables support for systems based on the Hilscher NetX Soc
465 config ARCH_H720X
466 bool "Hynix HMS720x-based"
467 select CPU_ARM720T
468 select ISA_DMA_API
469 select ARCH_USES_GETTIMEOFFSET
470 help
471 This enables support for systems based on the Hynix HMS720x
473 config ARCH_IOP13XX
474 bool "IOP13xx-based"
475 depends on MMU
476 select CPU_XSC3
477 select PLAT_IOP
478 select PCI
479 select ARCH_SUPPORTS_MSI
480 select VMSPLIT_1G
481 select NEED_MACH_MEMORY_H
482 help
483 Support for Intel's IOP13XX (XScale) family of processors.
485 config ARCH_IOP32X
486 bool "IOP32x-based"
487 depends on MMU
488 select CPU_XSCALE
489 select PLAT_IOP
490 select PCI
491 select ARCH_REQUIRE_GPIOLIB
492 help
493 Support for Intel's 80219 and IOP32X (XScale) family of
494 processors.
496 config ARCH_IOP33X
497 bool "IOP33x-based"
498 depends on MMU
499 select CPU_XSCALE
500 select PLAT_IOP
501 select PCI
502 select ARCH_REQUIRE_GPIOLIB
503 help
504 Support for Intel's IOP33X (XScale) family of processors.
506 config ARCH_IXP23XX
507 bool "IXP23XX-based"
508 depends on MMU
509 select CPU_XSC3
510 select PCI
511 select ARCH_USES_GETTIMEOFFSET
512 select NEED_MACH_MEMORY_H
513 help
514 Support for Intel's IXP23xx (XScale) family of processors.
516 config ARCH_IXP2000
517 bool "IXP2400/2800-based"
518 depends on MMU
519 select CPU_XSCALE
520 select PCI
521 select ARCH_USES_GETTIMEOFFSET
522 select NEED_MACH_MEMORY_H
523 help
524 Support for Intel's IXP2400/2800 (XScale) family of processors.
526 config ARCH_IXP4XX
527 bool "IXP4xx-based"
528 depends on MMU
529 select CLKSRC_MMIO
530 select CPU_XSCALE
531 select GENERIC_GPIO
532 select GENERIC_CLOCKEVENTS
533 select HAVE_SCHED_CLOCK
534 select MIGHT_HAVE_PCI
535 select DMABOUNCE if PCI
536 help
537 Support for Intel's IXP4XX (XScale) family of processors.
539 config ARCH_DOVE
540 bool "Marvell Dove"
541 select CPU_V7
542 select PCI
543 select ARCH_REQUIRE_GPIOLIB
544 select GENERIC_CLOCKEVENTS
545 select PLAT_ORION
546 help
547 Support for the Marvell Dove SoC 88AP510
549 config ARCH_KIRKWOOD
550 bool "Marvell Kirkwood"
551 select CPU_FEROCEON
552 select PCI
553 select ARCH_REQUIRE_GPIOLIB
554 select GENERIC_CLOCKEVENTS
555 select PLAT_ORION
556 help
557 Support for the following Marvell Kirkwood series SoCs:
558 88F6180, 88F6192 and 88F6281.
560 config ARCH_LPC32XX
561 bool "NXP LPC32XX"
562 select CLKSRC_MMIO
563 select CPU_ARM926T
564 select ARCH_REQUIRE_GPIOLIB
565 select HAVE_IDE
566 select ARM_AMBA
567 select USB_ARCH_HAS_OHCI
568 select CLKDEV_LOOKUP
569 select GENERIC_CLOCKEVENTS
570 help
571 Support for the NXP LPC32XX family of processors
573 config ARCH_MV78XX0
574 bool "Marvell MV78xx0"
575 select CPU_FEROCEON
576 select PCI
577 select ARCH_REQUIRE_GPIOLIB
578 select GENERIC_CLOCKEVENTS
579 select PLAT_ORION
580 help
581 Support for the following Marvell MV78xx0 series SoCs:
582 MV781x0, MV782x0.
584 config ARCH_ORION5X
585 bool "Marvell Orion"
586 depends on MMU
587 select CPU_FEROCEON
588 select PCI
589 select ARCH_REQUIRE_GPIOLIB
590 select GENERIC_CLOCKEVENTS
591 select PLAT_ORION
592 help
593 Support for the following Marvell Orion 5x series SoCs:
594 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
595 Orion-2 (5281), Orion-1-90 (6183).
597 config ARCH_MMP
598 bool "Marvell PXA168/910/MMP2"
599 depends on MMU
600 select ARCH_REQUIRE_GPIOLIB
601 select CLKDEV_LOOKUP
602 select GENERIC_CLOCKEVENTS
603 select GPIO_PXA
604 select HAVE_SCHED_CLOCK
605 select TICK_ONESHOT
606 select PLAT_PXA
607 select SPARSE_IRQ
608 select GENERIC_ALLOCATOR
609 help
610 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
612 config ARCH_KS8695
613 bool "Micrel/Kendin KS8695"
614 select CPU_ARM922T
615 select ARCH_REQUIRE_GPIOLIB
616 select ARCH_USES_GETTIMEOFFSET
617 select NEED_MACH_MEMORY_H
618 help
619 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
620 System-on-Chip devices.
622 config ARCH_W90X900
623 bool "Nuvoton W90X900 CPU"
624 select CPU_ARM926T
625 select ARCH_REQUIRE_GPIOLIB
626 select CLKDEV_LOOKUP
627 select CLKSRC_MMIO
628 select GENERIC_CLOCKEVENTS
629 help
630 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
631 At present, the w90x900 has been renamed nuc900, regarding
632 the ARM series product line, you can login the following
633 link address to know more.
635 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
636 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
638 config ARCH_TEGRA
639 bool "NVIDIA Tegra"
640 select CLKDEV_LOOKUP
641 select CLKSRC_MMIO
642 select GENERIC_CLOCKEVENTS
643 select GENERIC_GPIO
644 select HAVE_CLK
645 select HAVE_SCHED_CLOCK
646 select HAVE_SMP
647 select MIGHT_HAVE_CACHE_L2X0
648 select ARCH_HAS_CPUFREQ
649 help
650 This enables support for NVIDIA Tegra based systems (Tegra APX,
651 Tegra 6xx and Tegra 2 series).
653 config ARCH_PICOXCELL
654 bool "Picochip picoXcell"
655 select ARCH_REQUIRE_GPIOLIB
656 select ARM_PATCH_PHYS_VIRT
657 select ARM_VIC
658 select CPU_V6K
659 select DW_APB_TIMER
660 select GENERIC_CLOCKEVENTS
661 select GENERIC_GPIO
662 select HAVE_SCHED_CLOCK
663 select HAVE_TCM
664 select NO_IOPORT
665 select SPARSE_IRQ
666 select USE_OF
667 help
668 This enables support for systems based on the Picochip picoXcell
669 family of Femtocell devices. The picoxcell support requires device tree
670 for all boards.
672 config ARCH_PNX4008
673 bool "Philips Nexperia PNX4008 Mobile"
674 select CPU_ARM926T
675 select CLKDEV_LOOKUP
676 select ARCH_USES_GETTIMEOFFSET
677 help
678 This enables support for Philips PNX4008 mobile platform.
680 config ARCH_PXA
681 bool "PXA2xx/PXA3xx-based"
682 depends on MMU
683 select ARCH_MTD_XIP
684 select ARCH_HAS_CPUFREQ
685 select CLKDEV_LOOKUP
686 select CLKSRC_MMIO
687 select ARCH_REQUIRE_GPIOLIB
688 select GENERIC_CLOCKEVENTS
689 select GPIO_PXA
690 select HAVE_SCHED_CLOCK
691 select TICK_ONESHOT
692 select PLAT_PXA
693 select SPARSE_IRQ
694 select AUTO_ZRELADDR
695 select MULTI_IRQ_HANDLER
696 select ARM_CPU_SUSPEND if PM
697 select HAVE_IDE
698 help
699 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
701 config ARCH_MSM
702 bool "Qualcomm MSM"
703 select HAVE_CLK
704 select GENERIC_CLOCKEVENTS
705 select ARCH_REQUIRE_GPIOLIB
706 select CLKDEV_LOOKUP
707 help
708 Support for Qualcomm MSM/QSD based systems. This runs on the
709 apps processor of the MSM/QSD and depends on a shared memory
710 interface to the modem processor which runs the baseband
711 stack and controls some vital subsystems
712 (clock and power control, etc).
714 config ARCH_SHMOBILE
715 bool "Renesas SH-Mobile / R-Mobile"
716 select HAVE_CLK
717 select CLKDEV_LOOKUP
718 select HAVE_MACH_CLKDEV
719 select HAVE_SMP
720 select GENERIC_CLOCKEVENTS
721 select MIGHT_HAVE_CACHE_L2X0
722 select NO_IOPORT
723 select SPARSE_IRQ
724 select MULTI_IRQ_HANDLER
725 select PM_GENERIC_DOMAINS if PM
726 select NEED_MACH_MEMORY_H
727 help
728 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
730 config ARCH_RPC
731 bool "RiscPC"
732 select ARCH_ACORN
733 select FIQ
734 select TIMER_ACORN
735 select ARCH_MAY_HAVE_PC_FDC
736 select HAVE_PATA_PLATFORM
737 select ISA_DMA_API
738 select NO_IOPORT
739 select ARCH_SPARSEMEM_ENABLE
740 select ARCH_USES_GETTIMEOFFSET
741 select HAVE_IDE
742 select NEED_MACH_MEMORY_H
743 help
744 On the Acorn Risc-PC, Linux can support the internal IDE disk and
745 CD-ROM interface, serial and parallel port, and the floppy drive.
747 config ARCH_SA1100
748 bool "SA1100-based"
749 select CLKSRC_MMIO
750 select CPU_SA1100
751 select ISA
752 select ARCH_SPARSEMEM_ENABLE
753 select ARCH_MTD_XIP
754 select ARCH_HAS_CPUFREQ
755 select CPU_FREQ
756 select GENERIC_CLOCKEVENTS
757 select HAVE_CLK
758 select HAVE_SCHED_CLOCK
759 select TICK_ONESHOT
760 select ARCH_REQUIRE_GPIOLIB
761 select HAVE_IDE
762 select NEED_MACH_MEMORY_H
763 help
764 Support for StrongARM 11x0 based boards.
766 config ARCH_S3C2410
767 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
768 select GENERIC_GPIO
769 select ARCH_HAS_CPUFREQ
770 select HAVE_CLK
771 select CLKDEV_LOOKUP
772 select ARCH_USES_GETTIMEOFFSET
773 select HAVE_S3C2410_I2C if I2C
774 help
775 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
776 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
777 the Samsung SMDK2410 development board (and derivatives).
779 Note, the S3C2416 and the S3C2450 are so close that they even share
780 the same SoC ID code. This means that there is no separate machine
781 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
783 config ARCH_S3C64XX
784 bool "Samsung S3C64XX"
785 select PLAT_SAMSUNG
786 select CPU_V6
787 select ARM_VIC
788 select HAVE_CLK
789 select HAVE_TCM
790 select CLKDEV_LOOKUP
791 select NO_IOPORT
792 select ARCH_USES_GETTIMEOFFSET
793 select ARCH_HAS_CPUFREQ
794 select ARCH_REQUIRE_GPIOLIB
795 select SAMSUNG_CLKSRC
796 select SAMSUNG_IRQ_VIC_TIMER
797 select S3C_GPIO_TRACK
798 select S3C_DEV_NAND
799 select USB_ARCH_HAS_OHCI
800 select SAMSUNG_GPIOLIB_4BIT
801 select HAVE_S3C2410_I2C if I2C
802 select HAVE_S3C2410_WATCHDOG if WATCHDOG
803 help
804 Samsung S3C64XX series based systems
806 config ARCH_S5P64X0
807 bool "Samsung S5P6440 S5P6450"
808 select CPU_V6
809 select GENERIC_GPIO
810 select HAVE_CLK
811 select CLKDEV_LOOKUP
812 select CLKSRC_MMIO
813 select HAVE_S3C2410_WATCHDOG if WATCHDOG
814 select GENERIC_CLOCKEVENTS
815 select HAVE_SCHED_CLOCK
816 select HAVE_S3C2410_I2C if I2C
817 select HAVE_S3C_RTC if RTC_CLASS
818 help
819 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
820 SMDK6450.
822 config ARCH_S5PC100
823 bool "Samsung S5PC100"
824 select GENERIC_GPIO
825 select HAVE_CLK
826 select CLKDEV_LOOKUP
827 select CPU_V7
828 select ARCH_USES_GETTIMEOFFSET
829 select HAVE_S3C2410_I2C if I2C
830 select HAVE_S3C_RTC if RTC_CLASS
831 select HAVE_S3C2410_WATCHDOG if WATCHDOG
832 help
833 Samsung S5PC100 series based systems
835 config ARCH_S5PV210
836 bool "Samsung S5PV210/S5PC110"
837 select CPU_V7
838 select ARCH_SPARSEMEM_ENABLE
839 select ARCH_HAS_HOLES_MEMORYMODEL
840 select GENERIC_GPIO
841 select HAVE_CLK
842 select CLKDEV_LOOKUP
843 select CLKSRC_MMIO
844 select ARCH_HAS_CPUFREQ
845 select GENERIC_CLOCKEVENTS
846 select HAVE_SCHED_CLOCK
847 select HAVE_S3C2410_I2C if I2C
848 select HAVE_S3C_RTC if RTC_CLASS
849 select HAVE_S3C2410_WATCHDOG if WATCHDOG
850 select NEED_MACH_MEMORY_H
851 help
852 Samsung S5PV210/S5PC110 series based systems
854 config ARCH_EXYNOS
855 bool "SAMSUNG EXYNOS"
856 select CPU_V7
857 select ARCH_SPARSEMEM_ENABLE
858 select ARCH_HAS_HOLES_MEMORYMODEL
859 select GENERIC_GPIO
860 select HAVE_CLK
861 select CLKDEV_LOOKUP
862 select ARCH_HAS_CPUFREQ
863 select GENERIC_CLOCKEVENTS
864 select HAVE_S3C_RTC if RTC_CLASS
865 select HAVE_S3C2410_I2C if I2C
866 select HAVE_S3C2410_WATCHDOG if WATCHDOG
867 select NEED_MACH_MEMORY_H
868 help
869 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
871 config ARCH_SHARK
872 bool "Shark"
873 select CPU_SA110
874 select ISA
875 select ISA_DMA
876 select ZONE_DMA
877 select PCI
878 select ARCH_USES_GETTIMEOFFSET
879 select NEED_MACH_MEMORY_H
880 help
881 Support for the StrongARM based Digital DNARD machine, also known
882 as "Shark" (<http://www.shark-linux.de/shark.html>).
884 config ARCH_U300
885 bool "ST-Ericsson U300 Series"
886 depends on MMU
887 select CLKSRC_MMIO
888 select CPU_ARM926T
889 select HAVE_SCHED_CLOCK
890 select HAVE_TCM
891 select ARM_AMBA
892 select ARM_PATCH_PHYS_VIRT
893 select ARM_VIC
894 select GENERIC_CLOCKEVENTS
895 select CLKDEV_LOOKUP
896 select HAVE_MACH_CLKDEV
897 select GENERIC_GPIO
898 select ARCH_REQUIRE_GPIOLIB
899 help
900 Support for ST-Ericsson U300 series mobile platforms.
902 config ARCH_U8500
903 bool "ST-Ericsson U8500 Series"
904 select CPU_V7
905 select ARM_AMBA
906 select GENERIC_CLOCKEVENTS
907 select CLKDEV_LOOKUP
908 select ARCH_REQUIRE_GPIOLIB
909 select ARCH_HAS_CPUFREQ
910 select HAVE_SMP
911 select MIGHT_HAVE_CACHE_L2X0
912 help
913 Support for ST-Ericsson's Ux500 architecture
915 config ARCH_NOMADIK
916 bool "STMicroelectronics Nomadik"
917 select ARM_AMBA
918 select ARM_VIC
919 select CPU_ARM926T
920 select CLKDEV_LOOKUP
921 select GENERIC_CLOCKEVENTS
922 select MIGHT_HAVE_CACHE_L2X0
923 select ARCH_REQUIRE_GPIOLIB
924 help
925 Support for the Nomadik platform by ST-Ericsson
927 config ARCH_DAVINCI
928 bool "TI DaVinci"
929 select GENERIC_CLOCKEVENTS
930 select ARCH_REQUIRE_GPIOLIB
931 select ZONE_DMA
932 select HAVE_IDE
933 select CLKDEV_LOOKUP
934 select GENERIC_ALLOCATOR
935 select GENERIC_IRQ_CHIP
936 select ARCH_HAS_HOLES_MEMORYMODEL
937 help
938 Support for TI's DaVinci platform.
940 config ARCH_OMAP
941 bool "TI OMAP"
942 select HAVE_CLK
943 select ARCH_REQUIRE_GPIOLIB
944 select ARCH_HAS_CPUFREQ
945 select CLKSRC_MMIO
946 select GENERIC_CLOCKEVENTS
947 select HAVE_SCHED_CLOCK
948 select ARCH_HAS_HOLES_MEMORYMODEL
949 help
950 Support for TI's OMAP platform (OMAP1/2/3/4).
952 config PLAT_SPEAR
953 bool "ST SPEAr"
954 select ARM_AMBA
955 select ARCH_REQUIRE_GPIOLIB
956 select CLKDEV_LOOKUP
957 select CLKSRC_MMIO
958 select GENERIC_CLOCKEVENTS
959 select HAVE_CLK
960 help
961 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
963 config ARCH_VT8500
964 bool "VIA/WonderMedia 85xx"
965 select CPU_ARM926T
966 select GENERIC_GPIO
967 select ARCH_HAS_CPUFREQ
968 select GENERIC_CLOCKEVENTS
969 select ARCH_REQUIRE_GPIOLIB
970 select HAVE_PWM
971 help
972 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
974 config ARCH_ZYNQ
975 bool "Xilinx Zynq ARM Cortex A9 Platform"
976 select CPU_V7
977 select GENERIC_CLOCKEVENTS
978 select CLKDEV_LOOKUP
979 select ARM_GIC
980 select ARM_AMBA
981 select ICST
982 select MIGHT_HAVE_CACHE_L2X0
983 select USE_OF
984 help
985 Support for Xilinx Zynq ARM Cortex A9 Platform
986 endchoice
988 #
989 # This is sorted alphabetically by mach-* pathname. However, plat-*
990 # Kconfigs may be included either alphabetically (according to the
991 # plat- suffix) or along side the corresponding mach-* source.
992 #
993 source "arch/arm/mach-at91/Kconfig"
995 source "arch/arm/mach-bcmring/Kconfig"
997 source "arch/arm/mach-clps711x/Kconfig"
999 source "arch/arm/mach-cns3xxx/Kconfig"
1001 source "arch/arm/mach-davinci/Kconfig"
1003 source "arch/arm/mach-dove/Kconfig"
1005 source "arch/arm/mach-ep93xx/Kconfig"
1007 source "arch/arm/mach-footbridge/Kconfig"
1009 source "arch/arm/mach-gemini/Kconfig"
1011 source "arch/arm/mach-h720x/Kconfig"
1013 source "arch/arm/mach-integrator/Kconfig"
1015 source "arch/arm/mach-iop32x/Kconfig"
1017 source "arch/arm/mach-iop33x/Kconfig"
1019 source "arch/arm/mach-iop13xx/Kconfig"
1021 source "arch/arm/mach-ixp4xx/Kconfig"
1023 source "arch/arm/mach-ixp2000/Kconfig"
1025 source "arch/arm/mach-ixp23xx/Kconfig"
1027 source "arch/arm/mach-kirkwood/Kconfig"
1029 source "arch/arm/mach-ks8695/Kconfig"
1031 source "arch/arm/mach-lpc32xx/Kconfig"
1033 source "arch/arm/mach-msm/Kconfig"
1035 source "arch/arm/mach-mv78xx0/Kconfig"
1037 source "arch/arm/plat-mxc/Kconfig"
1039 source "arch/arm/mach-mxs/Kconfig"
1041 source "arch/arm/mach-netx/Kconfig"
1043 source "arch/arm/mach-nomadik/Kconfig"
1044 source "arch/arm/plat-nomadik/Kconfig"
1046 source "arch/arm/plat-omap/Kconfig"
1048 source "arch/arm/mach-omap1/Kconfig"
1050 source "arch/arm/mach-omap2/Kconfig"
1052 source "arch/arm/mach-orion5x/Kconfig"
1054 source "arch/arm/mach-pxa/Kconfig"
1055 source "arch/arm/plat-pxa/Kconfig"
1057 source "arch/arm/mach-mmp/Kconfig"
1059 source "arch/arm/mach-realview/Kconfig"
1061 source "arch/arm/mach-sa1100/Kconfig"
1063 source "arch/arm/plat-samsung/Kconfig"
1064 source "arch/arm/plat-s3c24xx/Kconfig"
1065 source "arch/arm/plat-s5p/Kconfig"
1067 source "arch/arm/plat-spear/Kconfig"
1069 if ARCH_S3C2410
1070 source "arch/arm/mach-s3c2410/Kconfig"
1071 source "arch/arm/mach-s3c2412/Kconfig"
1072 source "arch/arm/mach-s3c2416/Kconfig"
1073 source "arch/arm/mach-s3c2440/Kconfig"
1074 source "arch/arm/mach-s3c2443/Kconfig"
1075 endif
1077 if ARCH_S3C64XX
1078 source "arch/arm/mach-s3c64xx/Kconfig"
1079 endif
1081 source "arch/arm/mach-s5p64x0/Kconfig"
1083 source "arch/arm/mach-s5pc100/Kconfig"
1085 source "arch/arm/mach-s5pv210/Kconfig"
1087 source "arch/arm/mach-exynos/Kconfig"
1089 source "arch/arm/mach-shmobile/Kconfig"
1091 source "arch/arm/mach-tegra/Kconfig"
1093 source "arch/arm/mach-u300/Kconfig"
1095 source "arch/arm/mach-ux500/Kconfig"
1097 source "arch/arm/mach-versatile/Kconfig"
1099 source "arch/arm/mach-vexpress/Kconfig"
1100 source "arch/arm/plat-versatile/Kconfig"
1102 source "arch/arm/mach-vt8500/Kconfig"
1104 source "arch/arm/mach-w90x900/Kconfig"
1106 # Definitions to make life easier
1107 config ARCH_ACORN
1108 bool
1110 config PLAT_IOP
1111 bool
1112 select GENERIC_CLOCKEVENTS
1113 select HAVE_SCHED_CLOCK
1115 config PLAT_ORION
1116 bool
1117 select CLKSRC_MMIO
1118 select GENERIC_IRQ_CHIP
1119 select HAVE_SCHED_CLOCK
1121 config PLAT_PXA
1122 bool
1124 config PLAT_VERSATILE
1125 bool
1127 config ARM_TIMER_SP804
1128 bool
1129 select CLKSRC_MMIO
1131 source arch/arm/mm/Kconfig
1133 config ARM_NR_BANKS
1134 int
1135 default 16 if ARCH_EP93XX
1136 default 8
1138 config IWMMXT
1139 bool "Enable iWMMXt support"
1140 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1141 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1142 help
1143 Enable support for iWMMXt context switching at run time if
1144 running on a CPU that supports it.
1146 config XSCALE_PMU
1147 bool
1148 depends on CPU_XSCALE
1149 default y
1151 config CPU_HAS_PMU
1152 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1153 (!ARCH_OMAP3 || OMAP3_EMU)
1154 default y
1155 bool
1157 config MULTI_IRQ_HANDLER
1158 bool
1159 help
1160 Allow each machine to specify it's own IRQ handler at run time.
1162 if !MMU
1163 source "arch/arm/Kconfig-nommu"
1164 endif
1166 config ARM_ERRATA_326103
1167 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1168 depends on CPU_V6
1169 help
1170 Executing a SWP instruction to read-only memory does not set bit 11
1171 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1172 treat the access as a read, preventing a COW from occurring and
1173 causing the faulting task to livelock.
1175 config ARM_ERRATA_411920
1176 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1177 depends on CPU_V6 || CPU_V6K
1178 help
1179 Invalidation of the Instruction Cache operation can
1180 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1181 It does not affect the MPCore. This option enables the ARM Ltd.
1182 recommended workaround.
1184 config ARM_ERRATA_430973
1185 bool "ARM errata: Stale prediction on replaced interworking branch"
1186 depends on CPU_V7
1187 help
1188 This option enables the workaround for the 430973 Cortex-A8
1189 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1190 interworking branch is replaced with another code sequence at the
1191 same virtual address, whether due to self-modifying code or virtual
1192 to physical address re-mapping, Cortex-A8 does not recover from the
1193 stale interworking branch prediction. This results in Cortex-A8
1194 executing the new code sequence in the incorrect ARM or Thumb state.
1195 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1196 and also flushes the branch target cache at every context switch.
1197 Note that setting specific bits in the ACTLR register may not be
1198 available in non-secure mode.
1200 config ARM_ERRATA_458693
1201 bool "ARM errata: Processor deadlock when a false hazard is created"
1202 depends on CPU_V7
1203 help
1204 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1205 erratum. For very specific sequences of memory operations, it is
1206 possible for a hazard condition intended for a cache line to instead
1207 be incorrectly associated with a different cache line. This false
1208 hazard might then cause a processor deadlock. The workaround enables
1209 the L1 caching of the NEON accesses and disables the PLD instruction
1210 in the ACTLR register. Note that setting specific bits in the ACTLR
1211 register may not be available in non-secure mode.
1213 config ARM_ERRATA_460075
1214 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1215 depends on CPU_V7
1216 help
1217 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1218 erratum. Any asynchronous access to the L2 cache may encounter a
1219 situation in which recent store transactions to the L2 cache are lost
1220 and overwritten with stale memory contents from external memory. The
1221 workaround disables the write-allocate mode for the L2 cache via the
1222 ACTLR register. Note that setting specific bits in the ACTLR register
1223 may not be available in non-secure mode.
1225 config ARM_ERRATA_742230
1226 bool "ARM errata: DMB operation may be faulty"
1227 depends on CPU_V7 && SMP
1228 help
1229 This option enables the workaround for the 742230 Cortex-A9
1230 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1231 between two write operations may not ensure the correct visibility
1232 ordering of the two writes. This workaround sets a specific bit in
1233 the diagnostic register of the Cortex-A9 which causes the DMB
1234 instruction to behave as a DSB, ensuring the correct behaviour of
1235 the two writes.
1237 config ARM_ERRATA_742231
1238 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1239 depends on CPU_V7 && SMP
1240 help
1241 This option enables the workaround for the 742231 Cortex-A9
1242 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1243 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1244 accessing some data located in the same cache line, may get corrupted
1245 data due to bad handling of the address hazard when the line gets
1246 replaced from one of the CPUs at the same time as another CPU is
1247 accessing it. This workaround sets specific bits in the diagnostic
1248 register of the Cortex-A9 which reduces the linefill issuing
1249 capabilities of the processor.
1251 config PL310_ERRATA_588369
1252 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1253 depends on CACHE_L2X0
1254 help
1255 The PL310 L2 cache controller implements three types of Clean &
1256 Invalidate maintenance operations: by Physical Address
1257 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1258 They are architecturally defined to behave as the execution of a
1259 clean operation followed immediately by an invalidate operation,
1260 both performing to the same memory location. This functionality
1261 is not correctly implemented in PL310 as clean lines are not
1262 invalidated as a result of these operations.
1264 config ARM_ERRATA_720789
1265 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1266 depends on CPU_V7
1267 help
1268 This option enables the workaround for the 720789 Cortex-A9 (prior to
1269 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1270 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1271 As a consequence of this erratum, some TLB entries which should be
1272 invalidated are not, resulting in an incoherency in the system page
1273 tables. The workaround changes the TLB flushing routines to invalidate
1274 entries regardless of the ASID.
1276 config PL310_ERRATA_727915
1277 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1278 depends on CACHE_L2X0
1279 help
1280 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1281 operation (offset 0x7FC). This operation runs in background so that
1282 PL310 can handle normal accesses while it is in progress. Under very
1283 rare circumstances, due to this erratum, write data can be lost when
1284 PL310 treats a cacheable write transaction during a Clean &
1285 Invalidate by Way operation.
1287 config ARM_ERRATA_743622
1288 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1289 depends on CPU_V7
1290 help
1291 This option enables the workaround for the 743622 Cortex-A9
1292 (r2p*) erratum. Under very rare conditions, a faulty
1293 optimisation in the Cortex-A9 Store Buffer may lead to data
1294 corruption. This workaround sets a specific bit in the diagnostic
1295 register of the Cortex-A9 which disables the Store Buffer
1296 optimisation, preventing the defect from occurring. This has no
1297 visible impact on the overall performance or power consumption of the
1298 processor.
1300 config ARM_ERRATA_751472
1301 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1302 depends on CPU_V7
1303 help
1304 This option enables the workaround for the 751472 Cortex-A9 (prior
1305 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1306 completion of a following broadcasted operation if the second
1307 operation is received by a CPU before the ICIALLUIS has completed,
1308 potentially leading to corrupted entries in the cache or TLB.
1310 config PL310_ERRATA_753970
1311 bool "PL310 errata: cache sync operation may be faulty"
1312 depends on CACHE_PL310
1313 help
1314 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1316 Under some condition the effect of cache sync operation on
1317 the store buffer still remains when the operation completes.
1318 This means that the store buffer is always asked to drain and
1319 this prevents it from merging any further writes. The workaround
1320 is to replace the normal offset of cache sync operation (0x730)
1321 by another offset targeting an unmapped PL310 register 0x740.
1322 This has the same effect as the cache sync operation: store buffer
1323 drain and waiting for all buffers empty.
1325 config ARM_ERRATA_754322
1326 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1327 depends on CPU_V7
1328 help
1329 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1330 r3p*) erratum. A speculative memory access may cause a page table walk
1331 which starts prior to an ASID switch but completes afterwards. This
1332 can populate the micro-TLB with a stale entry which may be hit with
1333 the new ASID. This workaround places two dsb instructions in the mm
1334 switching code so that no page table walks can cross the ASID switch.
1336 config ARM_ERRATA_754327
1337 bool "ARM errata: no automatic Store Buffer drain"
1338 depends on CPU_V7 && SMP
1339 help
1340 This option enables the workaround for the 754327 Cortex-A9 (prior to
1341 r2p0) erratum. The Store Buffer does not have any automatic draining
1342 mechanism and therefore a livelock may occur if an external agent
1343 continuously polls a memory location waiting to observe an update.
1344 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1345 written polling loops from denying visibility of updates to memory.
1347 config ARM_ERRATA_364296
1348 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1349 depends on CPU_V6 && !SMP
1350 help
1351 This options enables the workaround for the 364296 ARM1136
1352 r0p2 erratum (possible cache data corruption with
1353 hit-under-miss enabled). It sets the undocumented bit 31 in
1354 the auxiliary control register and the FI bit in the control
1355 register, thus disabling hit-under-miss without putting the
1356 processor into full low interrupt latency mode. ARM11MPCore
1357 is not affected.
1359 config ARM_ERRATA_764369
1360 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1361 depends on CPU_V7 && SMP
1362 help
1363 This option enables the workaround for erratum 764369
1364 affecting Cortex-A9 MPCore with two or more processors (all
1365 current revisions). Under certain timing circumstances, a data
1366 cache line maintenance operation by MVA targeting an Inner
1367 Shareable memory region may fail to proceed up to either the
1368 Point of Coherency or to the Point of Unification of the
1369 system. This workaround adds a DSB instruction before the
1370 relevant cache maintenance functions and sets a specific bit
1371 in the diagnostic control register of the SCU.
1373 config PL310_ERRATA_769419
1374 bool "PL310 errata: no automatic Store Buffer drain"
1375 depends on CACHE_L2X0
1376 help
1377 On revisions of the PL310 prior to r3p2, the Store Buffer does
1378 not automatically drain. This can cause normal, non-cacheable
1379 writes to be retained when the memory system is idle, leading
1380 to suboptimal I/O performance for drivers using coherent DMA.
1381 This option adds a write barrier to the cpu_idle loop so that,
1382 on systems with an outer cache, the store buffer is drained
1383 explicitly.
1385 endmenu
1387 source "arch/arm/common/Kconfig"
1389 menu "Bus support"
1391 config ARM_AMBA
1392 bool
1394 config ISA
1395 bool
1396 help
1397 Find out whether you have ISA slots on your motherboard. ISA is the
1398 name of a bus system, i.e. the way the CPU talks to the other stuff
1399 inside your box. Other bus systems are PCI, EISA, MicroChannel
1400 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1401 newer boards don't support it. If you have ISA, say Y, otherwise N.
1403 # Select ISA DMA controller support
1404 config ISA_DMA
1405 bool
1406 select ISA_DMA_API
1408 # Select ISA DMA interface
1409 config ISA_DMA_API
1410 bool
1412 config PCI
1413 bool "PCI support" if MIGHT_HAVE_PCI
1414 help
1415 Find out whether you have a PCI motherboard. PCI is the name of a
1416 bus system, i.e. the way the CPU talks to the other stuff inside
1417 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1418 VESA. If you have PCI, say Y, otherwise N.
1420 config PCI_DOMAINS
1421 bool
1422 depends on PCI
1424 config PCI_NANOENGINE
1425 bool "BSE nanoEngine PCI support"
1426 depends on SA1100_NANOENGINE
1427 help
1428 Enable PCI on the BSE nanoEngine board.
1430 config PCI_SYSCALL
1431 def_bool PCI
1433 # Select the host bridge type
1434 config PCI_HOST_VIA82C505
1435 bool
1436 depends on PCI && ARCH_SHARK
1437 default y
1439 config PCI_HOST_ITE8152
1440 bool
1441 depends on PCI && MACH_ARMCORE
1442 default y
1443 select DMABOUNCE
1445 source "drivers/pci/Kconfig"
1447 source "drivers/pcmcia/Kconfig"
1449 endmenu
1451 menu "Kernel Features"
1453 source "kernel/time/Kconfig"
1455 config HAVE_SMP
1456 bool
1457 help
1458 This option should be selected by machines which have an SMP-
1459 capable CPU.
1461 The only effect of this option is to make the SMP-related
1462 options available to the user for configuration.
1464 config SMP
1465 bool "Symmetric Multi-Processing"
1466 depends on CPU_V6K || CPU_V7
1467 depends on GENERIC_CLOCKEVENTS
1468 depends on HAVE_SMP
1469 depends on MMU
1470 select USE_GENERIC_SMP_HELPERS
1471 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1472 help
1473 This enables support for systems with more than one CPU. If you have
1474 a system with only one CPU, like most personal computers, say N. If
1475 you have a system with more than one CPU, say Y.
1477 If you say N here, the kernel will run on single and multiprocessor
1478 machines, but will use only one CPU of a multiprocessor machine. If
1479 you say Y here, the kernel will run on many, but not all, single
1480 processor machines. On a single processor machine, the kernel will
1481 run faster if you say N here.
1483 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1484 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1485 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1487 If you don't know what to do here, say N.
1489 config SMP_ON_UP
1490 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1491 depends on EXPERIMENTAL
1492 depends on SMP && !XIP_KERNEL
1493 default y
1494 help
1495 SMP kernels contain instructions which fail on non-SMP processors.
1496 Enabling this option allows the kernel to modify itself to make
1497 these instructions safe. Disabling it allows about 1K of space
1498 savings.
1500 If you don't know what to do here, say Y.
1502 config ARM_CPU_TOPOLOGY
1503 bool "Support cpu topology definition"
1504 depends on SMP && CPU_V7
1505 default y
1506 help
1507 Support ARM cpu topology definition. The MPIDR register defines
1508 affinity between processors which is then used to describe the cpu
1509 topology of an ARM System.
1511 config SCHED_MC
1512 bool "Multi-core scheduler support"
1513 depends on ARM_CPU_TOPOLOGY
1514 help
1515 Multi-core scheduler support improves the CPU scheduler's decision
1516 making when dealing with multi-core CPU chips at a cost of slightly
1517 increased overhead in some places. If unsure say N here.
1519 config SCHED_SMT
1520 bool "SMT scheduler support"
1521 depends on ARM_CPU_TOPOLOGY
1522 help
1523 Improves the CPU scheduler's decision making when dealing with
1524 MultiThreading at a cost of slightly increased overhead in some
1525 places. If unsure say N here.
1527 config HAVE_ARM_SCU
1528 bool
1529 help
1530 This option enables support for the ARM system coherency unit
1532 config HAVE_ARM_TWD
1533 bool
1534 depends on SMP
1535 select TICK_ONESHOT
1536 help
1537 This options enables support for the ARM timer and watchdog unit
1539 choice
1540 prompt "Memory split"
1541 default VMSPLIT_3G
1542 help
1543 Select the desired split between kernel and user memory.
1545 If you are not absolutely sure what you are doing, leave this
1546 option alone!
1548 config VMSPLIT_3G
1549 bool "3G/1G user/kernel split"
1550 config VMSPLIT_2G
1551 bool "2G/2G user/kernel split"
1552 config VMSPLIT_1G
1553 bool "1G/3G user/kernel split"
1554 endchoice
1556 config PAGE_OFFSET
1557 hex
1558 default 0x40000000 if VMSPLIT_1G
1559 default 0x80000000 if VMSPLIT_2G
1560 default 0xC0000000
1562 config NR_CPUS
1563 int "Maximum number of CPUs (2-32)"
1564 range 2 32
1565 depends on SMP
1566 default "4"
1568 config HOTPLUG_CPU
1569 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1570 depends on SMP && HOTPLUG && EXPERIMENTAL
1571 help
1572 Say Y here to experiment with turning CPUs off and on. CPUs
1573 can be controlled through /sys/devices/system/cpu.
1575 config LOCAL_TIMERS
1576 bool "Use local timer interrupts"
1577 depends on SMP
1578 default y
1579 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1580 help
1581 Enable support for local timers on SMP platforms, rather then the
1582 legacy IPI broadcast method. Local timers allows the system
1583 accounting to be spread across the timer interval, preventing a
1584 "thundering herd" at every timer tick.
1586 config ARCH_NR_GPIO
1587 int
1588 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1589 default 350 if ARCH_U8500
1590 default 0
1591 help
1592 Maximum number of GPIOs in the system.
1594 If unsure, leave the default value.
1596 source kernel/Kconfig.preempt
1598 config HZ
1599 int
1600 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1601 ARCH_S5PV210 || ARCH_EXYNOS4
1602 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1603 default AT91_TIMER_HZ if ARCH_AT91
1604 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1605 default 100
1607 config THUMB2_KERNEL
1608 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1609 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1610 select AEABI
1611 select ARM_ASM_UNIFIED
1612 select ARM_UNWIND
1613 help
1614 By enabling this option, the kernel will be compiled in
1615 Thumb-2 mode. A compiler/assembler that understand the unified
1616 ARM-Thumb syntax is needed.
1618 If unsure, say N.
1620 config THUMB2_AVOID_R_ARM_THM_JUMP11
1621 bool "Work around buggy Thumb-2 short branch relocations in gas"
1622 depends on THUMB2_KERNEL && MODULES
1623 default y
1624 help
1625 Various binutils versions can resolve Thumb-2 branches to
1626 locally-defined, preemptible global symbols as short-range "b.n"
1627 branch instructions.
1629 This is a problem, because there's no guarantee the final
1630 destination of the symbol, or any candidate locations for a
1631 trampoline, are within range of the branch. For this reason, the
1632 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1633 relocation in modules at all, and it makes little sense to add
1634 support.
1636 The symptom is that the kernel fails with an "unsupported
1637 relocation" error when loading some modules.
1639 Until fixed tools are available, passing
1640 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1641 code which hits this problem, at the cost of a bit of extra runtime
1642 stack usage in some cases.
1644 The problem is described in more detail at:
1645 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1647 Only Thumb-2 kernels are affected.
1649 Unless you are sure your tools don't have this problem, say Y.
1651 config ARM_ASM_UNIFIED
1652 bool
1654 config AEABI
1655 bool "Use the ARM EABI to compile the kernel"
1656 help
1657 This option allows for the kernel to be compiled using the latest
1658 ARM ABI (aka EABI). This is only useful if you are using a user
1659 space environment that is also compiled with EABI.
1661 Since there are major incompatibilities between the legacy ABI and
1662 EABI, especially with regard to structure member alignment, this
1663 option also changes the kernel syscall calling convention to
1664 disambiguate both ABIs and allow for backward compatibility support
1665 (selected with CONFIG_OABI_COMPAT).
1667 To use this you need GCC version 4.0.0 or later.
1669 config OABI_COMPAT
1670 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1671 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1672 default y
1673 help
1674 This option preserves the old syscall interface along with the
1675 new (ARM EABI) one. It also provides a compatibility layer to
1676 intercept syscalls that have structure arguments which layout
1677 in memory differs between the legacy ABI and the new ARM EABI
1678 (only for non "thumb" binaries). This option adds a tiny
1679 overhead to all syscalls and produces a slightly larger kernel.
1680 If you know you'll be using only pure EABI user space then you
1681 can say N here. If this option is not selected and you attempt
1682 to execute a legacy ABI binary then the result will be
1683 UNPREDICTABLE (in fact it can be predicted that it won't work
1684 at all). If in doubt say Y.
1686 config ARCH_HAS_HOLES_MEMORYMODEL
1687 bool
1689 config ARCH_SPARSEMEM_ENABLE
1690 bool
1692 config ARCH_SPARSEMEM_DEFAULT
1693 def_bool ARCH_SPARSEMEM_ENABLE
1695 config ARCH_SELECT_MEMORY_MODEL
1696 def_bool ARCH_SPARSEMEM_ENABLE
1698 config HAVE_ARCH_PFN_VALID
1699 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1701 config HIGHMEM
1702 bool "High Memory Support"
1703 depends on MMU
1704 help
1705 The address space of ARM processors is only 4 Gigabytes large
1706 and it has to accommodate user address space, kernel address
1707 space as well as some memory mapped IO. That means that, if you
1708 have a large amount of physical memory and/or IO, not all of the
1709 memory can be "permanently mapped" by the kernel. The physical
1710 memory that is not permanently mapped is called "high memory".
1712 Depending on the selected kernel/user memory split, minimum
1713 vmalloc space and actual amount of RAM, you may not need this
1714 option which should result in a slightly faster kernel.
1716 If unsure, say n.
1718 config HIGHPTE
1719 bool "Allocate 2nd-level pagetables from highmem"
1720 depends on HIGHMEM
1722 config HW_PERF_EVENTS
1723 bool "Enable hardware performance counter support for perf events"
1724 depends on PERF_EVENTS && CPU_HAS_PMU
1725 default y
1726 help
1727 Enable hardware performance counter support for perf events. If
1728 disabled, perf events will use software events only.
1730 source "mm/Kconfig"
1732 config FORCE_MAX_ZONEORDER
1733 int "Maximum zone order" if ARCH_SHMOBILE
1734 range 11 64 if ARCH_SHMOBILE
1735 default "9" if SA1111
1736 default "11"
1737 help
1738 The kernel memory allocator divides physically contiguous memory
1739 blocks into "zones", where each zone is a power of two number of
1740 pages. This option selects the largest power of two that the kernel
1741 keeps in the memory allocator. If you need to allocate very large
1742 blocks of physically contiguous memory, then you may need to
1743 increase this value.
1745 This config option is actually maximum order plus one. For example,
1746 a value of 11 means that the largest free memory block is 2^10 pages.
1748 config LEDS
1749 bool "Timer and CPU usage LEDs"
1750 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1751 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1752 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1753 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1754 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1755 ARCH_AT91 || ARCH_DAVINCI || \
1756 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1757 help
1758 If you say Y here, the LEDs on your machine will be used
1759 to provide useful information about your current system status.
1761 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1762 be able to select which LEDs are active using the options below. If
1763 you are compiling a kernel for the EBSA-110 or the LART however, the
1764 red LED will simply flash regularly to indicate that the system is
1765 still functional. It is safe to say Y here if you have a CATS
1766 system, but the driver will do nothing.
1768 config LEDS_TIMER
1769 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1770 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1771 || MACH_OMAP_PERSEUS2
1772 depends on LEDS
1773 depends on !GENERIC_CLOCKEVENTS
1774 default y if ARCH_EBSA110
1775 help
1776 If you say Y here, one of the system LEDs (the green one on the
1777 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1778 will flash regularly to indicate that the system is still
1779 operational. This is mainly useful to kernel hackers who are
1780 debugging unstable kernels.
1782 The LART uses the same LED for both Timer LED and CPU usage LED
1783 functions. You may choose to use both, but the Timer LED function
1784 will overrule the CPU usage LED.
1786 config LEDS_CPU
1787 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1788 !ARCH_OMAP) \
1789 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1790 || MACH_OMAP_PERSEUS2
1791 depends on LEDS
1792 help
1793 If you say Y here, the red LED will be used to give a good real
1794 time indication of CPU usage, by lighting whenever the idle task
1795 is not currently executing.
1797 The LART uses the same LED for both Timer LED and CPU usage LED
1798 functions. You may choose to use both, but the Timer LED function
1799 will overrule the CPU usage LED.
1801 config ALIGNMENT_TRAP
1802 bool
1803 depends on CPU_CP15_MMU
1804 default y if !ARCH_EBSA110
1805 select HAVE_PROC_CPU if PROC_FS
1806 help
1807 ARM processors cannot fetch/store information which is not
1808 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1809 address divisible by 4. On 32-bit ARM processors, these non-aligned
1810 fetch/store instructions will be emulated in software if you say
1811 here, which has a severe performance impact. This is necessary for
1812 correct operation of some network protocols. With an IP-only
1813 configuration it is safe to say N, otherwise say Y.
1815 config UACCESS_WITH_MEMCPY
1816 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1817 depends on MMU && EXPERIMENTAL
1818 default y if CPU_FEROCEON
1819 help
1820 Implement faster copy_to_user and clear_user methods for CPU
1821 cores where a 8-word STM instruction give significantly higher
1822 memory write throughput than a sequence of individual 32bit stores.
1824 A possible side effect is a slight increase in scheduling latency
1825 between threads sharing the same address space if they invoke
1826 such copy operations with large buffers.
1828 However, if the CPU data cache is using a write-allocate mode,
1829 this option is unlikely to provide any performance gain.
1831 config SECCOMP
1832 bool
1833 prompt "Enable seccomp to safely compute untrusted bytecode"
1834 ---help---
1835 This kernel feature is useful for number crunching applications
1836 that may need to compute untrusted bytecode during their
1837 execution. By using pipes or other transports made available to
1838 the process as file descriptors supporting the read/write
1839 syscalls, it's possible to isolate those applications in
1840 their own address space using seccomp. Once seccomp is
1841 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1842 and the task is only allowed to execute a few safe syscalls
1843 defined by each seccomp mode.
1845 config CC_STACKPROTECTOR
1846 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1847 depends on EXPERIMENTAL
1848 help
1849 This option turns on the -fstack-protector GCC feature. This
1850 feature puts, at the beginning of functions, a canary value on
1851 the stack just before the return address, and validates
1852 the value just before actually returning. Stack based buffer
1853 overflows (that need to overwrite this return address) now also
1854 overwrite the canary, which gets detected and the attack is then
1855 neutralized via a kernel panic.
1856 This feature requires gcc version 4.2 or above.
1858 config DEPRECATED_PARAM_STRUCT
1859 bool "Provide old way to pass kernel parameters"
1860 help
1861 This was deprecated in 2001 and announced to live on for 5 years.
1862 Some old boot loaders still use this way.
1864 endmenu
1866 menu "Boot options"
1868 config USE_OF
1869 bool "Flattened Device Tree support"
1870 select OF
1871 select OF_EARLY_FLATTREE
1872 select IRQ_DOMAIN
1873 help
1874 Include support for flattened device tree machine descriptions.
1876 # Compressed boot loader in ROM. Yes, we really want to ask about
1877 # TEXT and BSS so we preserve their values in the config files.
1878 config ZBOOT_ROM_TEXT
1879 hex "Compressed ROM boot loader base address"
1880 default "0"
1881 help
1882 The physical address at which the ROM-able zImage is to be
1883 placed in the target. Platforms which normally make use of
1884 ROM-able zImage formats normally set this to a suitable
1885 value in their defconfig file.
1887 If ZBOOT_ROM is not enabled, this has no effect.
1889 config ZBOOT_ROM_BSS
1890 hex "Compressed ROM boot loader BSS address"
1891 default "0"
1892 help
1893 The base address of an area of read/write memory in the target
1894 for the ROM-able zImage which must be available while the
1895 decompressor is running. It must be large enough to hold the
1896 entire decompressed kernel plus an additional 128 KiB.
1897 Platforms which normally make use of ROM-able zImage formats
1898 normally set this to a suitable value in their defconfig file.
1900 If ZBOOT_ROM is not enabled, this has no effect.
1902 config ZBOOT_ROM
1903 bool "Compressed boot loader in ROM/flash"
1904 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1905 help
1906 Say Y here if you intend to execute your compressed kernel image
1907 (zImage) directly from ROM or flash. If unsure, say N.
1909 choice
1910 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1911 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1912 default ZBOOT_ROM_NONE
1913 help
1914 Include experimental SD/MMC loading code in the ROM-able zImage.
1915 With this enabled it is possible to write the the ROM-able zImage
1916 kernel image to an MMC or SD card and boot the kernel straight
1917 from the reset vector. At reset the processor Mask ROM will load
1918 the first part of the the ROM-able zImage which in turn loads the
1919 rest the kernel image to RAM.
1921 config ZBOOT_ROM_NONE
1922 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1923 help
1924 Do not load image from SD or MMC
1926 config ZBOOT_ROM_MMCIF
1927 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1928 help
1929 Load image from MMCIF hardware block.
1931 config ZBOOT_ROM_SH_MOBILE_SDHI
1932 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1933 help
1934 Load image from SDHI hardware block
1936 endchoice
1938 config ARM_APPENDED_DTB
1939 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1940 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1941 help
1942 With this option, the boot code will look for a device tree binary
1943 (DTB) appended to zImage
1944 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1946 This is meant as a backward compatibility convenience for those
1947 systems with a bootloader that can't be upgraded to accommodate
1948 the documented boot protocol using a device tree.
1950 Beware that there is very little in terms of protection against
1951 this option being confused by leftover garbage in memory that might
1952 look like a DTB header after a reboot if no actual DTB is appended
1953 to zImage. Do not leave this option active in a production kernel
1954 if you don't intend to always append a DTB. Proper passing of the
1955 location into r2 of a bootloader provided DTB is always preferable
1956 to this option.
1958 config ARM_ATAG_DTB_COMPAT
1959 bool "Supplement the appended DTB with traditional ATAG information"
1960 depends on ARM_APPENDED_DTB
1961 help
1962 Some old bootloaders can't be updated to a DTB capable one, yet
1963 they provide ATAGs with memory configuration, the ramdisk address,
1964 the kernel cmdline string, etc. Such information is dynamically
1965 provided by the bootloader and can't always be stored in a static
1966 DTB. To allow a device tree enabled kernel to be used with such
1967 bootloaders, this option allows zImage to extract the information
1968 from the ATAG list and store it at run time into the appended DTB.
1970 config CMDLINE
1971 string "Default kernel command string"
1972 default ""
1973 help
1974 On some architectures (EBSA110 and CATS), there is currently no way
1975 for the boot loader to pass arguments to the kernel. For these
1976 architectures, you should supply some command-line options at build
1977 time by entering them here. As a minimum, you should specify the
1978 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1980 choice
1981 prompt "Kernel command line type" if CMDLINE != ""
1982 default CMDLINE_FROM_BOOTLOADER
1984 config CMDLINE_FROM_BOOTLOADER
1985 bool "Use bootloader kernel arguments if available"
1986 help
1987 Uses the command-line options passed by the boot loader. If
1988 the boot loader doesn't provide any, the default kernel command
1989 string provided in CMDLINE will be used.
1991 config CMDLINE_EXTEND
1992 bool "Extend bootloader kernel arguments"
1993 help
1994 The command-line arguments provided by the boot loader will be
1995 appended to the default kernel command string.
1997 config CMDLINE_FORCE
1998 bool "Always use the default kernel command string"
1999 help
2000 Always use the default kernel command string, even if the boot
2001 loader passes other arguments to the kernel.
2002 This is useful if you cannot or don't want to change the
2003 command-line options your boot loader passes to the kernel.
2004 endchoice
2006 config XIP_KERNEL
2007 bool "Kernel Execute-In-Place from ROM"
2008 depends on !ZBOOT_ROM && !ARM_LPAE
2009 help
2010 Execute-In-Place allows the kernel to run from non-volatile storage
2011 directly addressable by the CPU, such as NOR flash. This saves RAM
2012 space since the text section of the kernel is not loaded from flash
2013 to RAM. Read-write sections, such as the data section and stack,
2014 are still copied to RAM. The XIP kernel is not compressed since
2015 it has to run directly from flash, so it will take more space to
2016 store it. The flash address used to link the kernel object files,
2017 and for storing it, is configuration dependent. Therefore, if you
2018 say Y here, you must know the proper physical address where to
2019 store the kernel image depending on your own flash memory usage.
2021 Also note that the make target becomes "make xipImage" rather than
2022 "make zImage" or "make Image". The final kernel binary to put in
2023 ROM memory will be arch/arm/boot/xipImage.
2025 If unsure, say N.
2027 config XIP_PHYS_ADDR
2028 hex "XIP Kernel Physical Location"
2029 depends on XIP_KERNEL
2030 default "0x00080000"
2031 help
2032 This is the physical address in your flash memory the kernel will
2033 be linked for and stored to. This address is dependent on your
2034 own flash usage.
2036 config KEXEC
2037 bool "Kexec system call (EXPERIMENTAL)"
2038 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2039 help
2040 kexec is a system call that implements the ability to shutdown your
2041 current kernel, and to start another kernel. It is like a reboot
2042 but it is independent of the system firmware. And like a reboot
2043 you can start any kernel with it, not just Linux.
2045 It is an ongoing process to be certain the hardware in a machine
2046 is properly shutdown, so do not be surprised if this code does not
2047 initially work for you. It may help to enable device hotplugging
2048 support.
2050 config ATAGS_PROC
2051 bool "Export atags in procfs"
2052 depends on KEXEC
2053 default y
2054 help
2055 Should the atags used to boot the kernel be exported in an "atags"
2056 file in procfs. Useful with kexec.
2058 config CRASH_DUMP
2059 bool "Build kdump crash kernel (EXPERIMENTAL)"
2060 depends on EXPERIMENTAL
2061 help
2062 Generate crash dump after being started by kexec. This should
2063 be normally only set in special crash dump kernels which are
2064 loaded in the main kernel with kexec-tools into a specially
2065 reserved region and then later executed after a crash by
2066 kdump/kexec. The crash dump kernel must be compiled to a
2067 memory address not used by the main kernel
2069 For more details see Documentation/kdump/kdump.txt
2071 config AUTO_ZRELADDR
2072 bool "Auto calculation of the decompressed kernel image address"
2073 depends on !ZBOOT_ROM && !ARCH_U300
2074 help
2075 ZRELADDR is the physical address where the decompressed kernel
2076 image will be placed. If AUTO_ZRELADDR is selected, the address
2077 will be determined at run-time by masking the current IP with
2078 0xf8000000. This assumes the zImage being placed in the first 128MB
2079 from start of memory.
2081 endmenu
2083 menu "CPU Power Management"
2085 if ARCH_HAS_CPUFREQ
2087 source "drivers/cpufreq/Kconfig"
2089 config CPU_FREQ_IMX
2090 tristate "CPUfreq driver for i.MX CPUs"
2091 depends on ARCH_MXC && CPU_FREQ
2092 help
2093 This enables the CPUfreq driver for i.MX CPUs.
2095 config CPU_FREQ_SA1100
2096 bool
2098 config CPU_FREQ_SA1110
2099 bool
2101 config CPU_FREQ_INTEGRATOR
2102 tristate "CPUfreq driver for ARM Integrator CPUs"
2103 depends on ARCH_INTEGRATOR && CPU_FREQ
2104 default y
2105 help
2106 This enables the CPUfreq driver for ARM Integrator CPUs.
2108 For details, take a look at <file:Documentation/cpu-freq>.
2110 If in doubt, say Y.
2112 config CPU_FREQ_PXA
2113 bool
2114 depends on CPU_FREQ && ARCH_PXA && PXA25x
2115 default y
2116 select CPU_FREQ_TABLE
2117 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2119 config CPU_FREQ_S3C
2120 bool
2121 help
2122 Internal configuration node for common cpufreq on Samsung SoC
2124 config CPU_FREQ_S3C24XX
2125 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2126 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
2127 select CPU_FREQ_S3C
2128 help
2129 This enables the CPUfreq driver for the Samsung S3C24XX family
2130 of CPUs.
2132 For details, take a look at <file:Documentation/cpu-freq>.
2134 If in doubt, say N.
2136 config CPU_FREQ_S3C24XX_PLL
2137 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2138 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2139 help
2140 Compile in support for changing the PLL frequency from the
2141 S3C24XX series CPUfreq driver. The PLL takes time to settle
2142 after a frequency change, so by default it is not enabled.
2144 This also means that the PLL tables for the selected CPU(s) will
2145 be built which may increase the size of the kernel image.
2147 config CPU_FREQ_S3C24XX_DEBUG
2148 bool "Debug CPUfreq Samsung driver core"
2149 depends on CPU_FREQ_S3C24XX
2150 help
2151 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2153 config CPU_FREQ_S3C24XX_IODEBUG
2154 bool "Debug CPUfreq Samsung driver IO timing"
2155 depends on CPU_FREQ_S3C24XX
2156 help
2157 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2159 config CPU_FREQ_S3C24XX_DEBUGFS
2160 bool "Export debugfs for CPUFreq"
2161 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2162 help
2163 Export status information via debugfs.
2165 endif
2167 source "drivers/cpuidle/Kconfig"
2169 endmenu
2171 menu "Floating point emulation"
2173 comment "At least one emulation must be selected"
2175 config FPE_NWFPE
2176 bool "NWFPE math emulation"
2177 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2178 ---help---
2179 Say Y to include the NWFPE floating point emulator in the kernel.
2180 This is necessary to run most binaries. Linux does not currently
2181 support floating point hardware so you need to say Y here even if
2182 your machine has an FPA or floating point co-processor podule.
2184 You may say N here if you are going to load the Acorn FPEmulator
2185 early in the bootup.
2187 config FPE_NWFPE_XP
2188 bool "Support extended precision"
2189 depends on FPE_NWFPE
2190 help
2191 Say Y to include 80-bit support in the kernel floating-point
2192 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2193 Note that gcc does not generate 80-bit operations by default,
2194 so in most cases this option only enlarges the size of the
2195 floating point emulator without any good reason.
2197 You almost surely want to say N here.
2199 config FPE_FASTFPE
2200 bool "FastFPE math emulation (EXPERIMENTAL)"
2201 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2202 ---help---
2203 Say Y here to include the FAST floating point emulator in the kernel.
2204 This is an experimental much faster emulator which now also has full
2205 precision for the mantissa. It does not support any exceptions.
2206 It is very simple, and approximately 3-6 times faster than NWFPE.
2208 It should be sufficient for most programs. It may be not suitable
2209 for scientific calculations, but you have to check this for yourself.
2210 If you do not feel you need a faster FP emulation you should better
2211 choose NWFPE.
2213 config VFP
2214 bool "VFP-format floating point maths"
2215 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2216 help
2217 Say Y to include VFP support code in the kernel. This is needed
2218 if your hardware includes a VFP unit.
2220 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2221 release notes and additional status information.
2223 Say N if your target does not have VFP hardware.
2225 config VFPv3
2226 bool
2227 depends on VFP
2228 default y if CPU_V7
2230 config NEON
2231 bool "Advanced SIMD (NEON) Extension support"
2232 depends on VFPv3 && CPU_V7
2233 help
2234 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2235 Extension.
2237 endmenu
2239 menu "Userspace binary formats"
2241 source "fs/Kconfig.binfmt"
2243 config ARTHUR
2244 tristate "RISC OS personality"
2245 depends on !AEABI
2246 help
2247 Say Y here to include the kernel code necessary if you want to run
2248 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2249 experimental; if this sounds frightening, say N and sleep in peace.
2250 You can also say M here to compile this support as a module (which
2251 will be called arthur).
2253 endmenu
2255 menu "Power management options"
2257 source "kernel/power/Kconfig"
2259 config ARCH_SUSPEND_POSSIBLE
2260 depends on !ARCH_S5PC100
2261 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2262 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2263 def_bool y
2265 config ARM_CPU_SUSPEND
2266 def_bool PM_SLEEP
2268 endmenu
2270 source "net/Kconfig"
2272 source "drivers/Kconfig"
2274 source "fs/Kconfig"
2276 source "arch/arm/Kconfig.debug"
2278 source "security/Kconfig"
2280 source "crypto/Kconfig"
2282 source "lib/Kconfig"