arch/arm/boot/dts/omap4.dtsi

   1 /*
   2  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /*
  10  * Carveout for multimedia usecases
  11  * It should be the last 48MB of the first 512MB memory part
  12  * In theory, it should not even exist. That zone should be reserved
  13  * dynamically during the .reserve callback.
  14  */
  15 /memreserve/ 0x9d000000 0x03000000;
  16
  17 /include/ "skeleton.dtsi"
  18
  19 / {
  20         compatible = "ti,omap4430", "ti,omap4";
  21         interrupt-parent = <&gic>;
  22
  23         aliases {
  24                 serial0 = &uart1;
  25                 serial1 = &uart2;
  26                 serial2 = &uart3;
  27                 serial3 = &uart4;
  28         };
  29
  30         cpus {
  31                 cpu@0 {
  32                         compatible = "arm,cortex-a9";
  33                 };
  34                 cpu@1 {
  35                         compatible = "arm,cortex-a9";
  36                 };
  37         };
  38
  39         /*
  40          * The soc node represents the soc top level view. It is uses for IPs
  41          * that are not memory mapped in the MPU view or for the MPU itself.
  42          */
  43         soc {
  44                 compatible = "ti,omap-infra";
  45                 mpu {
  46                         compatible = "ti,omap4-mpu";
  47                         ti,hwmods = "mpu";
  48                 };
  49
  50                 dsp {
  51                         compatible = "ti,omap3-c64";
  52                         ti,hwmods = "dsp";
  53                 };
  54
  55                 iva {
  56                         compatible = "ti,ivahd";
  57                         ti,hwmods = "iva";
  58                 };
  59         };
  60
  61         /*
  62          * XXX: Use a flat representation of the OMAP4 interconnect.
  63          * The real OMAP interconnect network is quite complex.
  64          *
  65          * MPU -+-- MPU_PRIVATE - GIC, L2
  66          *      |
  67          *      +----------------+----------+
  68          *      |                |          |
  69          *      +            +- EMIF - DDR  |
  70          *      |            |              |
  71          *      |            +     +--------+
  72          *      |            |     |
  73          *      |            +- L4_ABE - AESS, MCBSP, TIMERs...
  74          *      |            |
  75          *      +- L3_MAIN --+- L4_CORE - IPs...
  76          *                   |
  77          *                   +- L4_PER - IPs...
  78          *                   |
  79          *                   +- L4_CFG -+- L4_WKUP - IPs...
  80          *                   |          |
  81          *                   |          +- IPs...
  82          *                   +- IPU ----+
  83          *                   |          |
  84          *                   +- DSP ----+
  85          *                   |          |
  86          *                   +- DSS ----+
  87          *
  88          * Since that will not bring real advantage to represent that in DT for
  89          * the moment, just use a fake OCP bus entry to represent the whole bus
  90          * hierarchy.
  91          */
  92         ocp {
  93                 compatible = "ti,omap4-l3-noc", "simple-bus";
  94                 #address-cells = <1>;
  95                 #size-cells = <1>;
  96                 ranges;
  97                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
  98
  99                 gic: interrupt-controller@48241000 {
 100                         compatible = "arm,cortex-a9-gic";
 101                         interrupt-controller;
 102                         #interrupt-cells = <1>;
 103                         reg = <0x48241000 0x1000>,
 104                               <0x48240100 0x0100>;
 105                 };
 106
 107                 uart1: serial@0x4806a000 {
 108                         compatible = "ti,omap4-uart";
 109                         ti,hwmods = "uart1";
 110                         clock-frequency = <48000000>;
 111                 };
 112
 113                 uart2: serial@0x4806c000 {
 114                         compatible = "ti,omap4-uart";
 115                         ti,hwmods = "uart2";
 116                         clock-frequency = <48000000>;
 117                 };
 118
 119                 uart3: serial@0x48020000 {
 120                         compatible = "ti,omap4-uart";
 121                         ti,hwmods = "uart3";
 122                         clock-frequency = <48000000>;
 123                 };
 124
 125                 uart4: serial@0x4806e000 {
 126                         compatible = "ti,omap4-uart";
 127                         ti,hwmods = "uart4";
 128                         clock-frequency = <48000000>;
 129                 };
 130         };
 131 };