arch/arm/include/asm/hardware/iop_adma.h

   1 /*
   2  * Copyright © 2006, Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program; if not, write to the Free Software Foundation, Inc.,
  15  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  16  *
  17  */
  18 #ifndef IOP_ADMA_H
  19 #define IOP_ADMA_H
  20 #include <linux/types.h>
  21 #include <linux/dmaengine.h>
  22 #include <linux/interrupt.h>
  23
  24 #define IOP_ADMA_SLOT_SIZE 32
  25 #define IOP_ADMA_THRESHOLD 4
  26 #ifdef DEBUG
  27 #define IOP_PARANOIA 1
  28 #else
  29 #define IOP_PARANOIA 0
  30 #endif
  31 #define iop_paranoia(x) BUG_ON(IOP_PARANOIA && (x))
  32
  33 /**
  34  * struct iop_adma_device - internal representation of an ADMA device
  35  * @pdev: Platform device
  36  * @id: HW ADMA Device selector
  37  * @dma_desc_pool: base of DMA descriptor region (DMA address)
  38  * @dma_desc_pool_virt: base of DMA descriptor region (CPU address)
  39  * @common: embedded struct dma_device
  40  */
  41 struct iop_adma_device {
  42         struct platform_device *pdev;
  43         int id;
  44         dma_addr_t dma_desc_pool;
  45         void *dma_desc_pool_virt;
  46         struct dma_device common;
  47 };
  48
  49 /**
  50  * struct iop_adma_chan - internal representation of an ADMA device
  51  * @pending: allows batching of hardware operations
  52  * @completed_cookie: identifier for the most recently completed operation
  53  * @lock: serializes enqueue/dequeue operations to the slot pool
  54  * @mmr_base: memory mapped register base
  55  * @chain: device chain view of the descriptors
  56  * @device: parent device
  57  * @common: common dmaengine channel object members
  58  * @last_used: place holder for allocation to continue from where it left off
  59  * @all_slots: complete domain of slots usable by the channel
  60  * @slots_allocated: records the actual size of the descriptor slot pool
  61  * @irq_tasklet: bottom half where iop_adma_slot_cleanup runs
  62  */
  63 struct iop_adma_chan {
  64         int pending;
  65         dma_cookie_t completed_cookie;
  66         spinlock_t lock; /* protects the descriptor slot pool */
  67         void __iomem *mmr_base;
  68         struct list_head chain;
  69         struct iop_adma_device *device;
  70         struct dma_chan common;
  71         struct iop_adma_desc_slot *last_used;
  72         struct list_head all_slots;
  73         int slots_allocated;
  74         struct tasklet_struct irq_tasklet;
  75 };
  76
  77 /**
  78  * struct iop_adma_desc_slot - IOP-ADMA software descriptor
  79  * @slot_node: node on the iop_adma_chan.all_slots list
  80  * @chain_node: node on the op_adma_chan.chain list
  81  * @hw_desc: virtual address of the hardware descriptor chain
  82  * @phys: hardware address of the hardware descriptor chain
  83  * @group_head: first operation in a transaction
  84  * @slot_cnt: total slots used in an transaction (group of operations)
  85  * @slots_per_op: number of slots per operation
  86  * @idx: pool index
  87  * @unmap_src_cnt: number of xor sources
  88  * @unmap_len: transaction bytecount
  89  * @tx_list: list of descriptors that are associated with one operation
  90  * @async_tx: support for the async_tx api
  91  * @group_list: list of slots that make up a multi-descriptor transaction
  92  *      for example transfer lengths larger than the supported hw max
  93  * @xor_check_result: result of zero sum
  94  * @crc32_result: result crc calculation
  95  */
  96 struct iop_adma_desc_slot {
  97         struct list_head slot_node;
  98         struct list_head chain_node;
  99         void *hw_desc;
 100         struct iop_adma_desc_slot *group_head;
 101         u16 slot_cnt;
 102         u16 slots_per_op;
 103         u16 idx;
 104         u16 unmap_src_cnt;
 105         size_t unmap_len;
 106         struct list_head tx_list;
 107         struct dma_async_tx_descriptor async_tx;
 108         union {
 109                 u32 *xor_check_result;
 110                 u32 *crc32_result;
 111                 u32 *pq_check_result;
 112         };
 113 };
 114
 115 struct iop_adma_platform_data {
 116         int hw_id;
 117         dma_cap_mask_t cap_mask;
 118         size_t pool_size;
 119 };
 120
 121 #define to_iop_sw_desc(addr_hw_desc) \
 122         container_of(addr_hw_desc, struct iop_adma_desc_slot, hw_desc)
 123 #define iop_hw_desc_slot_idx(hw_desc, idx) \
 124         ( (void *) (((unsigned long) hw_desc) + ((idx) << 5)) )
 125 #endif