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Merge tag 'v3.3.7' into 3.3/master
[zen-stable.git] / arch / arm / mach-at91 / at91sam9261_devices.c
blob1e28bed8f425063e99af8ac417035e5e6d01900f
1 /*
2 * arch/arm/mach-at91/at91sam9261_devices.c
3 *
4 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
5 * Copyright (C) 2005 David Brownell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13 #include <asm/mach/arch.h>
14 #include <asm/mach/map.h>
15
16 #include <linux/dma-mapping.h>
17 #include <linux/gpio.h>
18 #include <linux/platform_device.h>
19 #include <linux/i2c-gpio.h>
20
21 #include <linux/fb.h>
22 #include <video/atmel_lcdc.h>
23
24 #include <mach/board.h>
25 #include <mach/at91sam9261.h>
26 #include <mach/at91sam9261_matrix.h>
27 #include <mach/at91sam9_smc.h>
28
29 #include "generic.h"
30
31
32 /* --------------------------------------------------------------------
33 * USB Host
34 * -------------------------------------------------------------------- */
35
36 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
37 static u64 ohci_dmamask = DMA_BIT_MASK(32);
38 static struct at91_usbh_data usbh_data;
39
40 static struct resource usbh_resources[] = {
41 [0] = {
42 .start = AT91SAM9261_UHP_BASE,
43 .end = AT91SAM9261_UHP_BASE + SZ_1M - 1,
44 .flags = IORESOURCE_MEM,
45 },
46 [1] = {
47 .start = AT91SAM9261_ID_UHP,
48 .end = AT91SAM9261_ID_UHP,
49 .flags = IORESOURCE_IRQ,
50 },
51 };
52
53 static struct platform_device at91sam9261_usbh_device = {
54 .name = "at91_ohci",
55 .id = -1,
56 .dev = {
57 .dma_mask = &ohci_dmamask,
58 .coherent_dma_mask = DMA_BIT_MASK(32),
59 .platform_data = &usbh_data,
60 },
61 .resource = usbh_resources,
62 .num_resources = ARRAY_SIZE(usbh_resources),
63 };
64
65 void __init at91_add_device_usbh(struct at91_usbh_data *data)
66 {
67 int i;
68
69 if (!data)
70 return;
71
72 /* Enable overcurrent notification */
73 for (i = 0; i < data->ports; i++) {
74 if (data->overcurrent_pin[i])
75 at91_set_gpio_input(data->overcurrent_pin[i], 1);
76 }
77
78 usbh_data = *data;
79 platform_device_register(&at91sam9261_usbh_device);
80 }
81 #else
82 void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
83 #endif
84
85
86 /* --------------------------------------------------------------------
87 * USB Device (Gadget)
88 * -------------------------------------------------------------------- */
89
90 #if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
91 static struct at91_udc_data udc_data;
92
93 static struct resource udc_resources[] = {
94 [0] = {
95 .start = AT91SAM9261_BASE_UDP,
96 .end = AT91SAM9261_BASE_UDP + SZ_16K - 1,
97 .flags = IORESOURCE_MEM,
98 },
99 [1] = {
100 .start = AT91SAM9261_ID_UDP,
101 .end = AT91SAM9261_ID_UDP,
102 .flags = IORESOURCE_IRQ,
103 },
104 };
105
106 static struct platform_device at91sam9261_udc_device = {
107 .name = "at91_udc",
108 .id = -1,
109 .dev = {
110 .platform_data = &udc_data,
111 },
112 .resource = udc_resources,
113 .num_resources = ARRAY_SIZE(udc_resources),
114 };
115
116 void __init at91_add_device_udc(struct at91_udc_data *data)
117 {
118 if (!data)
119 return;
120
121 if (gpio_is_valid(data->vbus_pin)) {
122 at91_set_gpio_input(data->vbus_pin, 0);
123 at91_set_deglitch(data->vbus_pin, 1);
124 }
125
126 /* Pullup pin is handled internally by USB device peripheral */
127
128 udc_data = *data;
129 platform_device_register(&at91sam9261_udc_device);
130 }
131 #else
132 void __init at91_add_device_udc(struct at91_udc_data *data) {}
133 #endif
134
135 /* --------------------------------------------------------------------
136 * MMC / SD
137 * -------------------------------------------------------------------- */
138
139 #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
140 static u64 mmc_dmamask = DMA_BIT_MASK(32);
141 static struct at91_mmc_data mmc_data;
142
143 static struct resource mmc_resources[] = {
144 [0] = {
145 .start = AT91SAM9261_BASE_MCI,
146 .end = AT91SAM9261_BASE_MCI + SZ_16K - 1,
147 .flags = IORESOURCE_MEM,
148 },
149 [1] = {
150 .start = AT91SAM9261_ID_MCI,
151 .end = AT91SAM9261_ID_MCI,
152 .flags = IORESOURCE_IRQ,
153 },
154 };
155
156 static struct platform_device at91sam9261_mmc_device = {
157 .name = "at91_mci",
158 .id = -1,
159 .dev = {
160 .dma_mask = &mmc_dmamask,
161 .coherent_dma_mask = DMA_BIT_MASK(32),
162 .platform_data = &mmc_data,
163 },
164 .resource = mmc_resources,
165 .num_resources = ARRAY_SIZE(mmc_resources),
166 };
167
168 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
169 {
170 if (!data)
171 return;
172
173 /* input/irq */
174 if (gpio_is_valid(data->det_pin)) {
175 at91_set_gpio_input(data->det_pin, 1);
176 at91_set_deglitch(data->det_pin, 1);
177 }
178 if (gpio_is_valid(data->wp_pin))
179 at91_set_gpio_input(data->wp_pin, 1);
180 if (gpio_is_valid(data->vcc_pin))
181 at91_set_gpio_output(data->vcc_pin, 0);
182
183 /* CLK */
184 at91_set_B_periph(AT91_PIN_PA2, 0);
185
186 /* CMD */
187 at91_set_B_periph(AT91_PIN_PA1, 1);
188
189 /* DAT0, maybe DAT1..DAT3 */
190 at91_set_B_periph(AT91_PIN_PA0, 1);
191 if (data->wire4) {
192 at91_set_B_periph(AT91_PIN_PA4, 1);
193 at91_set_B_periph(AT91_PIN_PA5, 1);
194 at91_set_B_periph(AT91_PIN_PA6, 1);
195 }
196
197 mmc_data = *data;
198 platform_device_register(&at91sam9261_mmc_device);
199 }
200 #else
201 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
202 #endif
203
204
205 /* --------------------------------------------------------------------
206 * NAND / SmartMedia
207 * -------------------------------------------------------------------- */
208
209 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
210 static struct atmel_nand_data nand_data;
211
212 #define NAND_BASE AT91_CHIPSELECT_3
213
214 static struct resource nand_resources[] = {
215 {
216 .start = NAND_BASE,
217 .end = NAND_BASE + SZ_256M - 1,
218 .flags = IORESOURCE_MEM,
219 }
220 };
221
222 static struct platform_device atmel_nand_device = {
223 .name = "atmel_nand",
224 .id = -1,
225 .dev = {
226 .platform_data = &nand_data,
227 },
228 .resource = nand_resources,
229 .num_resources = ARRAY_SIZE(nand_resources),
230 };
231
232 void __init at91_add_device_nand(struct atmel_nand_data *data)
233 {
234 unsigned long csa;
235
236 if (!data)
237 return;
238
239 csa = at91_sys_read(AT91_MATRIX_EBICSA);
240 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
241
242 /* enable pin */
243 if (gpio_is_valid(data->enable_pin))
244 at91_set_gpio_output(data->enable_pin, 1);
245
246 /* ready/busy pin */
247 if (gpio_is_valid(data->rdy_pin))
248 at91_set_gpio_input(data->rdy_pin, 1);
249
250 /* card detect pin */
251 if (gpio_is_valid(data->det_pin))
252 at91_set_gpio_input(data->det_pin, 1);
253
254 at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
255 at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
256
257 nand_data = *data;
258 platform_device_register(&atmel_nand_device);
259 }
260
261 #else
262 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
263 #endif
264
265
266 /* --------------------------------------------------------------------
267 * TWI (i2c)
268 * -------------------------------------------------------------------- */
269
270 /*
271 * Prefer the GPIO code since the TWI controller isn't robust
272 * (gets overruns and underruns under load) and can only issue
273 * repeated STARTs in one scenario (the driver doesn't yet handle them).
274 */
275 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
276
277 static struct i2c_gpio_platform_data pdata = {
278 .sda_pin = AT91_PIN_PA7,
279 .sda_is_open_drain = 1,
280 .scl_pin = AT91_PIN_PA8,
281 .scl_is_open_drain = 1,
282 .udelay = 2, /* ~100 kHz */
283 };
284
285 static struct platform_device at91sam9261_twi_device = {
286 .name = "i2c-gpio",
287 .id = -1,
288 .dev.platform_data = &pdata,
289 };
290
291 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
292 {
293 at91_set_GPIO_periph(AT91_PIN_PA7, 1); /* TWD (SDA) */
294 at91_set_multi_drive(AT91_PIN_PA7, 1);
295
296 at91_set_GPIO_periph(AT91_PIN_PA8, 1); /* TWCK (SCL) */
297 at91_set_multi_drive(AT91_PIN_PA8, 1);
298
299 i2c_register_board_info(0, devices, nr_devices);
300 platform_device_register(&at91sam9261_twi_device);
301 }
302
303 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
304
305 static struct resource twi_resources[] = {
306 [0] = {
307 .start = AT91SAM9261_BASE_TWI,
308 .end = AT91SAM9261_BASE_TWI + SZ_16K - 1,
309 .flags = IORESOURCE_MEM,
310 },
311 [1] = {
312 .start = AT91SAM9261_ID_TWI,
313 .end = AT91SAM9261_ID_TWI,
314 .flags = IORESOURCE_IRQ,
315 },
316 };
317
318 static struct platform_device at91sam9261_twi_device = {
319 .name = "at91_i2c",
320 .id = -1,
321 .resource = twi_resources,
322 .num_resources = ARRAY_SIZE(twi_resources),
323 };
324
325 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
326 {
327 /* pins used for TWI interface */
328 at91_set_A_periph(AT91_PIN_PA7, 0); /* TWD */
329 at91_set_multi_drive(AT91_PIN_PA7, 1);
330
331 at91_set_A_periph(AT91_PIN_PA8, 0); /* TWCK */
332 at91_set_multi_drive(AT91_PIN_PA8, 1);
333
334 i2c_register_board_info(0, devices, nr_devices);
335 platform_device_register(&at91sam9261_twi_device);
336 }
337 #else
338 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
339 #endif
340
341
342 /* --------------------------------------------------------------------
343 * SPI
344 * -------------------------------------------------------------------- */
345
346 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
347 static u64 spi_dmamask = DMA_BIT_MASK(32);
348
349 static struct resource spi0_resources[] = {
350 [0] = {
351 .start = AT91SAM9261_BASE_SPI0,
352 .end = AT91SAM9261_BASE_SPI0 + SZ_16K - 1,
353 .flags = IORESOURCE_MEM,
354 },
355 [1] = {
356 .start = AT91SAM9261_ID_SPI0,
357 .end = AT91SAM9261_ID_SPI0,
358 .flags = IORESOURCE_IRQ,
359 },
360 };
361
362 static struct platform_device at91sam9261_spi0_device = {
363 .name = "atmel_spi",
364 .id = 0,
365 .dev = {
366 .dma_mask = &spi_dmamask,
367 .coherent_dma_mask = DMA_BIT_MASK(32),
368 },
369 .resource = spi0_resources,
370 .num_resources = ARRAY_SIZE(spi0_resources),
371 };
372
373 static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
374
375 static struct resource spi1_resources[] = {
376 [0] = {
377 .start = AT91SAM9261_BASE_SPI1,
378 .end = AT91SAM9261_BASE_SPI1 + SZ_16K - 1,
379 .flags = IORESOURCE_MEM,
380 },
381 [1] = {
382 .start = AT91SAM9261_ID_SPI1,
383 .end = AT91SAM9261_ID_SPI1,
384 .flags = IORESOURCE_IRQ,
385 },
386 };
387
388 static struct platform_device at91sam9261_spi1_device = {
389 .name = "atmel_spi",
390 .id = 1,
391 .dev = {
392 .dma_mask = &spi_dmamask,
393 .coherent_dma_mask = DMA_BIT_MASK(32),
394 },
395 .resource = spi1_resources,
396 .num_resources = ARRAY_SIZE(spi1_resources),
397 };
398
399 static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB28, AT91_PIN_PA24, AT91_PIN_PA25, AT91_PIN_PA26 };
400
401 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
402 {
403 int i;
404 unsigned long cs_pin;
405 short enable_spi0 = 0;
406 short enable_spi1 = 0;
407
408 /* Choose SPI chip-selects */
409 for (i = 0; i < nr_devices; i++) {
410 if (devices[i].controller_data)
411 cs_pin = (unsigned long) devices[i].controller_data;
412 else if (devices[i].bus_num == 0)
413 cs_pin = spi0_standard_cs[devices[i].chip_select];
414 else
415 cs_pin = spi1_standard_cs[devices[i].chip_select];
416
417 if (devices[i].bus_num == 0)
418 enable_spi0 = 1;
419 else
420 enable_spi1 = 1;
421
422 /* enable chip-select pin */
423 at91_set_gpio_output(cs_pin, 1);
424
425 /* pass chip-select pin to driver */
426 devices[i].controller_data = (void *) cs_pin;
427 }
428
429 spi_register_board_info(devices, nr_devices);
430
431 /* Configure SPI bus(es) */
432 if (enable_spi0) {
433 at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
434 at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
435 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
436
437 platform_device_register(&at91sam9261_spi0_device);
438 }
439 if (enable_spi1) {
440 at91_set_A_periph(AT91_PIN_PB30, 0); /* SPI1_MISO */
441 at91_set_A_periph(AT91_PIN_PB31, 0); /* SPI1_MOSI */
442 at91_set_A_periph(AT91_PIN_PB29, 0); /* SPI1_SPCK */
443
444 platform_device_register(&at91sam9261_spi1_device);
445 }
446 }
447 #else
448 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
449 #endif
450
451
452 /* --------------------------------------------------------------------
453 * LCD Controller
454 * -------------------------------------------------------------------- */
455
456 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
457 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
458 static struct atmel_lcdfb_info lcdc_data;
459
460 static struct resource lcdc_resources[] = {
461 [0] = {
462 .start = AT91SAM9261_LCDC_BASE,
463 .end = AT91SAM9261_LCDC_BASE + SZ_4K - 1,
464 .flags = IORESOURCE_MEM,
465 },
466 [1] = {
467 .start = AT91SAM9261_ID_LCDC,
468 .end = AT91SAM9261_ID_LCDC,
469 .flags = IORESOURCE_IRQ,
470 },
471 #if defined(CONFIG_FB_INTSRAM)
472 [2] = {
473 .start = AT91SAM9261_SRAM_BASE,
474 .end = AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE - 1,
475 .flags = IORESOURCE_MEM,
476 },
477 #endif
478 };
479
480 static struct platform_device at91_lcdc_device = {
481 .name = "atmel_lcdfb",
482 .id = 0,
483 .dev = {
484 .dma_mask = &lcdc_dmamask,
485 .coherent_dma_mask = DMA_BIT_MASK(32),
486 .platform_data = &lcdc_data,
487 },
488 .resource = lcdc_resources,
489 .num_resources = ARRAY_SIZE(lcdc_resources),
490 };
491
492 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
493 {
494 if (!data) {
495 return;
496 }
497
498 #if defined(CONFIG_FB_ATMEL_STN)
499 at91_set_A_periph(AT91_PIN_PB0, 0); /* LCDVSYNC */
500 at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
501 at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
502 at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
503 at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
504 at91_set_A_periph(AT91_PIN_PB5, 0); /* LCDD0 */
505 at91_set_A_periph(AT91_PIN_PB6, 0); /* LCDD1 */
506 at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
507 at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
508 #else
509 at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
510 at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
511 at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
512 at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
513 at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
514 at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
515 at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
516 at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
517 at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
518 at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
519 at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
520 at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
521 at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
522 at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
523 at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
524 at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
525 at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
526 at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
527 at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
528 at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
529 at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
530 at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
531 #endif
532
533 if (ARRAY_SIZE(lcdc_resources) > 2) {
534 void __iomem *fb;
535 struct resource *fb_res = &lcdc_resources[2];
536 size_t fb_len = resource_size(fb_res);
537
538 fb = ioremap(fb_res->start, fb_len);
539 if (fb) {
540 memset(fb, 0, fb_len);
541 iounmap(fb);
542 }
543 }
544 lcdc_data = *data;
545 platform_device_register(&at91_lcdc_device);
546 }
547 #else
548 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
549 #endif
550
551
552 /* --------------------------------------------------------------------
553 * Timer/Counter block
554 * -------------------------------------------------------------------- */
555
556 #ifdef CONFIG_ATMEL_TCLIB
557
558 static struct resource tcb_resources[] = {
559 [0] = {
560 .start = AT91SAM9261_BASE_TCB0,
561 .end = AT91SAM9261_BASE_TCB0 + SZ_16K - 1,
562 .flags = IORESOURCE_MEM,
563 },
564 [1] = {
565 .start = AT91SAM9261_ID_TC0,
566 .end = AT91SAM9261_ID_TC0,
567 .flags = IORESOURCE_IRQ,
568 },
569 [2] = {
570 .start = AT91SAM9261_ID_TC1,
571 .end = AT91SAM9261_ID_TC1,
572 .flags = IORESOURCE_IRQ,
573 },
574 [3] = {
575 .start = AT91SAM9261_ID_TC2,
576 .end = AT91SAM9261_ID_TC2,
577 .flags = IORESOURCE_IRQ,
578 },
579 };
580
581 static struct platform_device at91sam9261_tcb_device = {
582 .name = "atmel_tcb",
583 .id = 0,
584 .resource = tcb_resources,
585 .num_resources = ARRAY_SIZE(tcb_resources),
586 };
587
588 static void __init at91_add_device_tc(void)
589 {
590 platform_device_register(&at91sam9261_tcb_device);
591 }
592 #else
593 static void __init at91_add_device_tc(void) { }
594 #endif
595
596
597 /* --------------------------------------------------------------------
598 * RTT
599 * -------------------------------------------------------------------- */
600
601 static struct resource rtt_resources[] = {
602 {
603 .start = AT91SAM9261_BASE_RTT,
604 .end = AT91SAM9261_BASE_RTT + SZ_16 - 1,
605 .flags = IORESOURCE_MEM,
606 }
607 };
608
609 static struct platform_device at91sam9261_rtt_device = {
610 .name = "at91_rtt",
611 .id = 0,
612 .resource = rtt_resources,
613 .num_resources = ARRAY_SIZE(rtt_resources),
614 };
615
616 static void __init at91_add_device_rtt(void)
617 {
618 platform_device_register(&at91sam9261_rtt_device);
619 }
620
621
622 /* --------------------------------------------------------------------
623 * Watchdog
624 * -------------------------------------------------------------------- */
625
626 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
627 static struct resource wdt_resources[] = {
628 {
629 .start = AT91SAM9261_BASE_WDT,
630 .end = AT91SAM9261_BASE_WDT + SZ_16 - 1,
631 .flags = IORESOURCE_MEM,
632 }
633 };
634
635 static struct platform_device at91sam9261_wdt_device = {
636 .name = "at91_wdt",
637 .id = -1,
638 .resource = wdt_resources,
639 .num_resources = ARRAY_SIZE(wdt_resources),
640 };
641
642 static void __init at91_add_device_watchdog(void)
643 {
644 platform_device_register(&at91sam9261_wdt_device);
645 }
646 #else
647 static void __init at91_add_device_watchdog(void) {}
648 #endif
649
650
651 /* --------------------------------------------------------------------
652 * SSC -- Synchronous Serial Controller
653 * -------------------------------------------------------------------- */
654
655 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
656 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
657
658 static struct resource ssc0_resources[] = {
659 [0] = {
660 .start = AT91SAM9261_BASE_SSC0,
661 .end = AT91SAM9261_BASE_SSC0 + SZ_16K - 1,
662 .flags = IORESOURCE_MEM,
663 },
664 [1] = {
665 .start = AT91SAM9261_ID_SSC0,
666 .end = AT91SAM9261_ID_SSC0,
667 .flags = IORESOURCE_IRQ,
668 },
669 };
670
671 static struct platform_device at91sam9261_ssc0_device = {
672 .name = "ssc",
673 .id = 0,
674 .dev = {
675 .dma_mask = &ssc0_dmamask,
676 .coherent_dma_mask = DMA_BIT_MASK(32),
677 },
678 .resource = ssc0_resources,
679 .num_resources = ARRAY_SIZE(ssc0_resources),
680 };
681
682 static inline void configure_ssc0_pins(unsigned pins)
683 {
684 if (pins & ATMEL_SSC_TF)
685 at91_set_A_periph(AT91_PIN_PB21, 1);
686 if (pins & ATMEL_SSC_TK)
687 at91_set_A_periph(AT91_PIN_PB22, 1);
688 if (pins & ATMEL_SSC_TD)
689 at91_set_A_periph(AT91_PIN_PB23, 1);
690 if (pins & ATMEL_SSC_RD)
691 at91_set_A_periph(AT91_PIN_PB24, 1);
692 if (pins & ATMEL_SSC_RK)
693 at91_set_A_periph(AT91_PIN_PB25, 1);
694 if (pins & ATMEL_SSC_RF)
695 at91_set_A_periph(AT91_PIN_PB26, 1);
696 }
697
698 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
699
700 static struct resource ssc1_resources[] = {
701 [0] = {
702 .start = AT91SAM9261_BASE_SSC1,
703 .end = AT91SAM9261_BASE_SSC1 + SZ_16K - 1,
704 .flags = IORESOURCE_MEM,
705 },
706 [1] = {
707 .start = AT91SAM9261_ID_SSC1,
708 .end = AT91SAM9261_ID_SSC1,
709 .flags = IORESOURCE_IRQ,
710 },
711 };
712
713 static struct platform_device at91sam9261_ssc1_device = {
714 .name = "ssc",
715 .id = 1,
716 .dev = {
717 .dma_mask = &ssc1_dmamask,
718 .coherent_dma_mask = DMA_BIT_MASK(32),
719 },
720 .resource = ssc1_resources,
721 .num_resources = ARRAY_SIZE(ssc1_resources),
722 };
723
724 static inline void configure_ssc1_pins(unsigned pins)
725 {
726 if (pins & ATMEL_SSC_TF)
727 at91_set_B_periph(AT91_PIN_PA17, 1);
728 if (pins & ATMEL_SSC_TK)
729 at91_set_B_periph(AT91_PIN_PA18, 1);
730 if (pins & ATMEL_SSC_TD)
731 at91_set_B_periph(AT91_PIN_PA19, 1);
732 if (pins & ATMEL_SSC_RD)
733 at91_set_B_periph(AT91_PIN_PA20, 1);
734 if (pins & ATMEL_SSC_RK)
735 at91_set_B_periph(AT91_PIN_PA21, 1);
736 if (pins & ATMEL_SSC_RF)
737 at91_set_B_periph(AT91_PIN_PA22, 1);
738 }
739
740 static u64 ssc2_dmamask = DMA_BIT_MASK(32);
741
742 static struct resource ssc2_resources[] = {
743 [0] = {
744 .start = AT91SAM9261_BASE_SSC2,
745 .end = AT91SAM9261_BASE_SSC2 + SZ_16K - 1,
746 .flags = IORESOURCE_MEM,
747 },
748 [1] = {
749 .start = AT91SAM9261_ID_SSC2,
750 .end = AT91SAM9261_ID_SSC2,
751 .flags = IORESOURCE_IRQ,
752 },
753 };
754
755 static struct platform_device at91sam9261_ssc2_device = {
756 .name = "ssc",
757 .id = 2,
758 .dev = {
759 .dma_mask = &ssc2_dmamask,
760 .coherent_dma_mask = DMA_BIT_MASK(32),
761 },
762 .resource = ssc2_resources,
763 .num_resources = ARRAY_SIZE(ssc2_resources),
764 };
765
766 static inline void configure_ssc2_pins(unsigned pins)
767 {
768 if (pins & ATMEL_SSC_TF)
769 at91_set_B_periph(AT91_PIN_PC25, 1);
770 if (pins & ATMEL_SSC_TK)
771 at91_set_B_periph(AT91_PIN_PC26, 1);
772 if (pins & ATMEL_SSC_TD)
773 at91_set_B_periph(AT91_PIN_PC27, 1);
774 if (pins & ATMEL_SSC_RD)
775 at91_set_B_periph(AT91_PIN_PC28, 1);
776 if (pins & ATMEL_SSC_RK)
777 at91_set_B_periph(AT91_PIN_PC29, 1);
778 if (pins & ATMEL_SSC_RF)
779 at91_set_B_periph(AT91_PIN_PC30, 1);
780 }
781
782 /*
783 * SSC controllers are accessed through library code, instead of any
784 * kind of all-singing/all-dancing driver. For example one could be
785 * used by a particular I2S audio codec's driver, while another one
786 * on the same system might be used by a custom data capture driver.
787 */
788 void __init at91_add_device_ssc(unsigned id, unsigned pins)
789 {
790 struct platform_device *pdev;
791
792 /*
793 * NOTE: caller is responsible for passing information matching
794 * "pins" to whatever will be using each particular controller.
795 */
796 switch (id) {
797 case AT91SAM9261_ID_SSC0:
798 pdev = &at91sam9261_ssc0_device;
799 configure_ssc0_pins(pins);
800 break;
801 case AT91SAM9261_ID_SSC1:
802 pdev = &at91sam9261_ssc1_device;
803 configure_ssc1_pins(pins);
804 break;
805 case AT91SAM9261_ID_SSC2:
806 pdev = &at91sam9261_ssc2_device;
807 configure_ssc2_pins(pins);
808 break;
809 default:
810 return;
811 }
812
813 platform_device_register(pdev);
814 }
815
816 #else
817 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
818 #endif
819
820
821 /* --------------------------------------------------------------------
822 * UART
823 * -------------------------------------------------------------------- */
824
825 #if defined(CONFIG_SERIAL_ATMEL)
826 static struct resource dbgu_resources[] = {
827 [0] = {
828 .start = AT91SAM9261_BASE_DBGU,
829 .end = AT91SAM9261_BASE_DBGU + SZ_512 - 1,
830 .flags = IORESOURCE_MEM,
831 },
832 [1] = {
833 .start = AT91_ID_SYS,
834 .end = AT91_ID_SYS,
835 .flags = IORESOURCE_IRQ,
836 },
837 };
838
839 static struct atmel_uart_data dbgu_data = {
840 .use_dma_tx = 0,
841 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
842 };
843
844 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
845
846 static struct platform_device at91sam9261_dbgu_device = {
847 .name = "atmel_usart",
848 .id = 0,
849 .dev = {
850 .dma_mask = &dbgu_dmamask,
851 .coherent_dma_mask = DMA_BIT_MASK(32),
852 .platform_data = &dbgu_data,
853 },
854 .resource = dbgu_resources,
855 .num_resources = ARRAY_SIZE(dbgu_resources),
856 };
857
858 static inline void configure_dbgu_pins(void)
859 {
860 at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */
861 at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */
862 }
863
864 static struct resource uart0_resources[] = {
865 [0] = {
866 .start = AT91SAM9261_BASE_US0,
867 .end = AT91SAM9261_BASE_US0 + SZ_16K - 1,
868 .flags = IORESOURCE_MEM,
869 },
870 [1] = {
871 .start = AT91SAM9261_ID_US0,
872 .end = AT91SAM9261_ID_US0,
873 .flags = IORESOURCE_IRQ,
874 },
875 };
876
877 static struct atmel_uart_data uart0_data = {
878 .use_dma_tx = 1,
879 .use_dma_rx = 1,
880 };
881
882 static u64 uart0_dmamask = DMA_BIT_MASK(32);
883
884 static struct platform_device at91sam9261_uart0_device = {
885 .name = "atmel_usart",
886 .id = 1,
887 .dev = {
888 .dma_mask = &uart0_dmamask,
889 .coherent_dma_mask = DMA_BIT_MASK(32),
890 .platform_data = &uart0_data,
891 },
892 .resource = uart0_resources,
893 .num_resources = ARRAY_SIZE(uart0_resources),
894 };
895
896 static inline void configure_usart0_pins(unsigned pins)
897 {
898 at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */
899 at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */
900
901 if (pins & ATMEL_UART_RTS)
902 at91_set_A_periph(AT91_PIN_PC10, 0); /* RTS0 */
903 if (pins & ATMEL_UART_CTS)
904 at91_set_A_periph(AT91_PIN_PC11, 0); /* CTS0 */
905 }
906
907 static struct resource uart1_resources[] = {
908 [0] = {
909 .start = AT91SAM9261_BASE_US1,
910 .end = AT91SAM9261_BASE_US1 + SZ_16K - 1,
911 .flags = IORESOURCE_MEM,
912 },
913 [1] = {
914 .start = AT91SAM9261_ID_US1,
915 .end = AT91SAM9261_ID_US1,
916 .flags = IORESOURCE_IRQ,
917 },
918 };
919
920 static struct atmel_uart_data uart1_data = {
921 .use_dma_tx = 1,
922 .use_dma_rx = 1,
923 };
924
925 static u64 uart1_dmamask = DMA_BIT_MASK(32);
926
927 static struct platform_device at91sam9261_uart1_device = {
928 .name = "atmel_usart",
929 .id = 2,
930 .dev = {
931 .dma_mask = &uart1_dmamask,
932 .coherent_dma_mask = DMA_BIT_MASK(32),
933 .platform_data = &uart1_data,
934 },
935 .resource = uart1_resources,
936 .num_resources = ARRAY_SIZE(uart1_resources),
937 };
938
939 static inline void configure_usart1_pins(unsigned pins)
940 {
941 at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */
942 at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */
943
944 if (pins & ATMEL_UART_RTS)
945 at91_set_B_periph(AT91_PIN_PA12, 0); /* RTS1 */
946 if (pins & ATMEL_UART_CTS)
947 at91_set_B_periph(AT91_PIN_PA13, 0); /* CTS1 */
948 }
949
950 static struct resource uart2_resources[] = {
951 [0] = {
952 .start = AT91SAM9261_BASE_US2,
953 .end = AT91SAM9261_BASE_US2 + SZ_16K - 1,
954 .flags = IORESOURCE_MEM,
955 },
956 [1] = {
957 .start = AT91SAM9261_ID_US2,
958 .end = AT91SAM9261_ID_US2,
959 .flags = IORESOURCE_IRQ,
960 },
961 };
962
963 static struct atmel_uart_data uart2_data = {
964 .use_dma_tx = 1,
965 .use_dma_rx = 1,
966 };
967
968 static u64 uart2_dmamask = DMA_BIT_MASK(32);
969
970 static struct platform_device at91sam9261_uart2_device = {
971 .name = "atmel_usart",
972 .id = 3,
973 .dev = {
974 .dma_mask = &uart2_dmamask,
975 .coherent_dma_mask = DMA_BIT_MASK(32),
976 .platform_data = &uart2_data,
977 },
978 .resource = uart2_resources,
979 .num_resources = ARRAY_SIZE(uart2_resources),
980 };
981
982 static inline void configure_usart2_pins(unsigned pins)
983 {
984 at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */
985 at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */
986
987 if (pins & ATMEL_UART_RTS)
988 at91_set_B_periph(AT91_PIN_PA15, 0); /* RTS2*/
989 if (pins & ATMEL_UART_CTS)
990 at91_set_B_periph(AT91_PIN_PA16, 0); /* CTS2 */
991 }
992
993 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
994 struct platform_device *atmel_default_console_device; /* the serial console device */
995
996 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
997 {
998 struct platform_device *pdev;
999 struct atmel_uart_data *pdata;
1000
1001 switch (id) {
1002 case 0: /* DBGU */
1003 pdev = &at91sam9261_dbgu_device;
1004 configure_dbgu_pins();
1005 break;
1006 case AT91SAM9261_ID_US0:
1007 pdev = &at91sam9261_uart0_device;
1008 configure_usart0_pins(pins);
1009 break;
1010 case AT91SAM9261_ID_US1:
1011 pdev = &at91sam9261_uart1_device;
1012 configure_usart1_pins(pins);
1013 break;
1014 case AT91SAM9261_ID_US2:
1015 pdev = &at91sam9261_uart2_device;
1016 configure_usart2_pins(pins);
1017 break;
1018 default:
1019 return;
1020 }
1021 pdata = pdev->dev.platform_data;
1022 pdata->num = portnr; /* update to mapped ID */
1023
1024 if (portnr < ATMEL_MAX_UART)
1025 at91_uarts[portnr] = pdev;
1026 }
1027
1028 void __init at91_set_serial_console(unsigned portnr)
1029 {
1030 if (portnr < ATMEL_MAX_UART) {
1031 atmel_default_console_device = at91_uarts[portnr];
1032 at91sam9261_set_console_clock(at91_uarts[portnr]->id);
1033 }
1034 }
1035
1036 void __init at91_add_device_serial(void)
1037 {
1038 int i;
1039
1040 for (i = 0; i < ATMEL_MAX_UART; i++) {
1041 if (at91_uarts[i])
1042 platform_device_register(at91_uarts[i]);
1043 }
1044
1045 if (!atmel_default_console_device)
1046 printk(KERN_INFO "AT91: No default serial console defined.\n");
1047 }
1048 #else
1049 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1050 void __init at91_set_serial_console(unsigned portnr) {}
1051 void __init at91_add_device_serial(void) {}
1052 #endif
1053
1054
1055 /* -------------------------------------------------------------------- */
1056
1057 /*
1058 * These devices are always present and don't need any board-specific
1059 * setup.
1060 */
1061 static int __init at91_add_standard_devices(void)
1062 {
1063 at91_add_device_rtt();
1064 at91_add_device_watchdog();
1065 at91_add_device_tc();
1066 return 0;
1067 }
1068
1069 arch_initcall(at91_add_standard_devices);