arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h

   1 /*****************************************************************************
   2 * Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
   3 *
   4 * Unless you and Broadcom execute a separate written software license
   5 * agreement governing use of this software, this software is licensed to you
   6 * under the terms of the GNU General Public License version 2, available at
   7 * http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
   8 *
   9 * Notwithstanding the above, under no circumstances may you combine this
  10 * software in any way with any other Broadcom software provided under a
  11 * license other than the GPL, without Broadcom's express prior written
  12 * consent.
  13 *****************************************************************************/
  14
  15 /****************************************************************************/
  16 /**
  17 *  @file    tmrHw_reg.h
  18 *
  19 *  @brief   Definitions for low level Timer registers
  20 *
  21 */
  22 /****************************************************************************/
  23 #ifndef _TMRHW_REG_H
  24 #define _TMRHW_REG_H
  25
  26 #include <mach/csp/mm_io.h>
  27 #include <mach/csp/hw_cfg.h>
  28 /* Base address */
  29 #define tmrHw_MODULE_BASE_ADDR          MM_IO_BASE_TMR
  30
  31 /*
  32 This platform has four different timers running at different clock speed
  33
  34 Timer one   (Timer ID 0) runs at  25 MHz
  35 Timer two   (Timer ID 1) runs at  25 MHz
  36 Timer three (Timer ID 2) runs at 150 MHz
  37 Timer four  (Timer ID 3) runs at 150 MHz
  38 */
  39 #define tmrHw_LOW_FREQUENCY_MHZ         25      /* Always 25MHz from XTAL */
  40 #define tmrHw_LOW_FREQUENCY_HZ          25000000
  41
  42 #if defined(CFG_GLOBAL_CHIP) && (CFG_GLOBAL_CHIP == FPGA11107)
  43 #define tmrHw_HIGH_FREQUENCY_MHZ        150     /* Always 150MHz for FPGA */
  44 #define tmrHw_HIGH_FREQUENCY_HZ         150000000
  45 #else
  46 #define tmrHw_HIGH_FREQUENCY_HZ         HW_CFG_BUS_CLK_HZ
  47 #define tmrHw_HIGH_FREQUENCY_MHZ        (HW_CFG_BUS_CLK_HZ / 1000000)
  48 #endif
  49
  50 #define tmrHw_LOW_RESOLUTION_CLOCK      tmrHw_LOW_FREQUENCY_HZ
  51 #define tmrHw_HIGH_RESOLUTION_CLOCK     tmrHw_HIGH_FREQUENCY_HZ
  52 #define tmrHw_MAX_COUNT                 (0xFFFFFFFF)    /* maximum number of count a timer can count */
  53 #define tmrHw_TIMER_NUM_COUNT           (4)     /* Number of timer module supported */
  54
  55 typedef struct {
  56         uint32_t LoadValue;     /* Load value for timer */
  57         uint32_t CurrentValue;  /* Current value for timer */
  58         uint32_t Control;       /* Control register */
  59         uint32_t InterruptClear;        /* Interrupt clear register */
  60         uint32_t RawInterruptStatus;    /* Raw interrupt status */
  61         uint32_t InterruptStatus;       /* Masked interrupt status */
  62         uint32_t BackgroundLoad;        /* Background load value */
  63         uint32_t padding;       /* Padding register */
  64 } tmrHw_REG_t;
  65
  66 /* Control bot masks */
  67 #define tmrHw_CONTROL_TIMER_ENABLE            0x00000080
  68 #define tmrHw_CONTROL_PERIODIC                0x00000040
  69 #define tmrHw_CONTROL_INTERRUPT_ENABLE        0x00000020
  70 #define tmrHw_CONTROL_PRESCALE_MASK           0x0000000C
  71 #define tmrHw_CONTROL_PRESCALE_1              0x00000000
  72 #define tmrHw_CONTROL_PRESCALE_16             0x00000004
  73 #define tmrHw_CONTROL_PRESCALE_256            0x00000008
  74 #define tmrHw_CONTROL_32BIT                   0x00000002
  75 #define tmrHw_CONTROL_ONESHOT                 0x00000001
  76 #define tmrHw_CONTROL_FREE_RUNNING            0x00000000
  77
  78 #define tmrHw_CONTROL_MODE_MASK               (tmrHw_CONTROL_PERIODIC | tmrHw_CONTROL_ONESHOT)
  79
  80 #define pTmrHw ((volatile tmrHw_REG_t *)tmrHw_MODULE_BASE_ADDR)
  81
  82 #endif /* _TMRHW_REG_H */