arch/arm/mach-bcmring/include/mach/reg_umi.h

   1 /*****************************************************************************
   2 * Copyright 2005 - 2008 Broadcom Corporation.  All rights reserved.
   3 *
   4 * Unless you and Broadcom execute a separate written software license
   5 * agreement governing use of this software, this software is licensed to you
   6 * under the terms of the GNU General Public License version 2, available at
   7 * http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
   8 *
   9 * Notwithstanding the above, under no circumstances may you combine this
  10 * software in any way with any other Broadcom software provided under a
  11 * license other than the GPL, without Broadcom's express prior written
  12 * consent.
  13 *****************************************************************************/
  14
  15 /*
  16 *
  17 *****************************************************************************
  18 *
  19 *  REG_UMI.h
  20 *
  21 *  PURPOSE:
  22 *
  23 *     This file contains definitions for the nand registers:
  24 *
  25 *  NOTES:
  26 *
  27 *****************************************************************************/
  28
  29 #if !defined(__ASM_ARCH_REG_UMI_H)
  30 #define __ASM_ARCH_REG_UMI_H
  31
  32 /* ---- Include Files ---------------------------------------------------- */
  33 #include <csp/reg.h>
  34 #include <mach/csp/mm_io.h>
  35
  36 /* ---- Constants and Types ---------------------------------------------- */
  37
  38 /* Unified Memory Interface Ctrl Register */
  39 #define HW_UMI_BASE       MM_IO_BASE_UMI
  40
  41 /* Flash bank 0 timing and control register */
  42 #define REG_UMI_FLASH0_TCR         __REG32(HW_UMI_BASE  + 0x00)
  43 /* Flash bank 1 timing and control register */
  44 #define REG_UMI_FLASH1_TCR         __REG32(HW_UMI_BASE  + 0x04)
  45 /* Flash bank 2 timing and control register */
  46 #define REG_UMI_FLASH2_TCR         __REG32(HW_UMI_BASE  + 0x08)
  47 /* MMD interface and control register */
  48 #define REG_UMI_MMD_ICR            __REG32(HW_UMI_BASE  + 0x0c)
  49 /* NAND timing and control register */
  50 #define REG_UMI_NAND_TCR           __REG32(HW_UMI_BASE  + 0x18)
  51 /* NAND ready/chip select register */
  52 #define REG_UMI_NAND_RCSR          __REG32(HW_UMI_BASE  + 0x1c)
  53 /* NAND ECC control & status register */
  54 #define REG_UMI_NAND_ECC_CSR       __REG32(HW_UMI_BASE  + 0x20)
  55 /* NAND ECC data register XXB2B1B0 */
  56 #define REG_UMI_NAND_ECC_DATA      __REG32(HW_UMI_BASE  + 0x24)
  57 /* BCH ECC Parameter N */
  58 #define REG_UMI_BCH_N              __REG32(HW_UMI_BASE  + 0x40)
  59 /* BCH ECC Parameter T */
  60 #define REG_UMI_BCH_K              __REG32(HW_UMI_BASE  + 0x44)
  61 /* BCH ECC Parameter K */
  62 #define REG_UMI_BCH_T              __REG32(HW_UMI_BASE  + 0x48)
  63 /* BCH ECC Contro Status */
  64 #define REG_UMI_BCH_CTRL_STATUS    __REG32(HW_UMI_BASE  + 0x4C)
  65 /* BCH WR ECC 31:0 */
  66 #define REG_UMI_BCH_WR_ECC_0       __REG32(HW_UMI_BASE  + 0x50)
  67 /* BCH WR ECC 63:32 */
  68 #define REG_UMI_BCH_WR_ECC_1       __REG32(HW_UMI_BASE  + 0x54)
  69 /* BCH WR ECC 95:64 */
  70 #define REG_UMI_BCH_WR_ECC_2       __REG32(HW_UMI_BASE  + 0x58)
  71 /* BCH WR ECC 127:96 */
  72 #define REG_UMI_BCH_WR_ECC_3       __REG32(HW_UMI_BASE  + 0x5c)
  73 /* BCH WR ECC 155:128 */
  74 #define REG_UMI_BCH_WR_ECC_4       __REG32(HW_UMI_BASE  + 0x60)
  75 /* BCH Read Error Location 1,0 */
  76 #define REG_UMI_BCH_RD_ERR_LOC_1_0 __REG32(HW_UMI_BASE  + 0x64)
  77 /* BCH Read Error Location 3,2 */
  78 #define REG_UMI_BCH_RD_ERR_LOC_3_2 __REG32(HW_UMI_BASE  + 0x68)
  79 /* BCH Read Error Location 5,4 */
  80 #define REG_UMI_BCH_RD_ERR_LOC_5_4 __REG32(HW_UMI_BASE  + 0x6c)
  81 /* BCH Read Error Location 7,6 */
  82 #define REG_UMI_BCH_RD_ERR_LOC_7_6 __REG32(HW_UMI_BASE  + 0x70)
  83 /* BCH Read Error Location 9,8 */
  84 #define REG_UMI_BCH_RD_ERR_LOC_9_8 __REG32(HW_UMI_BASE  + 0x74)
  85 /* BCH Read Error Location 11,10 */
  86 #define REG_UMI_BCH_RD_ERR_LOC_B_A __REG32(HW_UMI_BASE  + 0x78)
  87
  88 /* REG_UMI_FLASH0/1/2_TCR, REG_UMI_SRAM0/1_TCR bits */
  89 /* Enable wait pin during burst write or read */
  90 #define REG_UMI_TCR_WAITEN              0x80000000
  91 /* Enable mem ctrlr to work with ext mem of lower freq than AHB clk */
  92 #define REG_UMI_TCR_LOWFREQ             0x40000000
  93 /* 1=synch write, 0=async write */
  94 #define REG_UMI_TCR_MEMTYPE_SYNCWRITE   0x20000000
  95 /* 1=synch read, 0=async read */
  96 #define REG_UMI_TCR_MEMTYPE_SYNCREAD    0x10000000
  97 /* 1=page mode read, 0=normal mode read */
  98 #define REG_UMI_TCR_MEMTYPE_PAGEREAD    0x08000000
  99 /* page size/burst size (wrap only) */
 100 #define REG_UMI_TCR_MEMTYPE_PGSZ_MASK   0x07000000
 101 /* 4 word */
 102 #define REG_UMI_TCR_MEMTYPE_PGSZ_4      0x00000000
 103 /* 8 word */
 104 #define REG_UMI_TCR_MEMTYPE_PGSZ_8      0x01000000
 105 /* 16 word */
 106 #define REG_UMI_TCR_MEMTYPE_PGSZ_16     0x02000000
 107 /* 32 word */
 108 #define REG_UMI_TCR_MEMTYPE_PGSZ_32     0x03000000
 109 /* 64 word */
 110 #define REG_UMI_TCR_MEMTYPE_PGSZ_64     0x04000000
 111 /* 128 word */
 112 #define REG_UMI_TCR_MEMTYPE_PGSZ_128    0x05000000
 113 /* 256 word */
 114 #define REG_UMI_TCR_MEMTYPE_PGSZ_256    0x06000000
 115 /* 512 word */
 116 #define REG_UMI_TCR_MEMTYPE_PGSZ_512    0x07000000
 117 /* Page read access cycle / Burst write latency (n+2 / n+1) */
 118 #define REG_UMI_TCR_TPRC_TWLC_MASK      0x00f80000
 119 /* Bus turnaround cycle (n) */
 120 #define REG_UMI_TCR_TBTA_MASK           0x00070000
 121 /* Write pulse width cycle (n+1) */
 122 #define REG_UMI_TCR_TWP_MASK            0x0000f800
 123 /* Write recovery cycle (n+1) */
 124 #define REG_UMI_TCR_TWR_MASK            0x00000600
 125 /* Write address setup cycle (n+1) */
 126 #define REG_UMI_TCR_TAS_MASK            0x00000180
 127 /* Output enable delay cycle (n) */
 128 #define REG_UMI_TCR_TOE_MASK            0x00000060
 129 /* Read access cycle / Burst read latency (n+2 / n+1) */
 130 #define REG_UMI_TCR_TRC_TLC_MASK        0x0000001f
 131
 132 /* REG_UMI_MMD_ICR bits */
 133 /* Flash write protection pin control */
 134 #define REG_UMI_MMD_ICR_FLASH_WP            0x8000
 135 /* Extend hold time for sram0, sram1 csn (39 MHz operation) */
 136 #define REG_UMI_MMD_ICR_XHCS                0x4000
 137 /* Enable SDRAM 2 interface control */
 138 #define REG_UMI_MMD_ICR_SDRAM2EN            0x2000
 139 /* Enable merge of flash banks 0/1 to 512 MBit bank */
 140 #define REG_UMI_MMD_ICR_INST512             0x1000
 141 /* Enable merge of flash banks 1/2 to 512 MBit bank */
 142 #define REG_UMI_MMD_ICR_DATA512             0x0800
 143 /* Enable SDRAM interface control */
 144 #define REG_UMI_MMD_ICR_SDRAMEN             0x0400
 145 /* Polarity of busy state of Burst Wait Signal */
 146 #define REG_UMI_MMD_ICR_WAITPOL             0x0200
 147 /* Enable burst clock stopped when not accessing external burst flash/sram */
 148 #define REG_UMI_MMD_ICR_BCLKSTOP            0x0100
 149 /* Enable the peri1_csn to replace flash1_csn in 512 Mb flash mode */
 150 #define REG_UMI_MMD_ICR_PERI1EN             0x0080
 151 /* Enable the peri2_csn to replace sdram_csn */
 152 #define REG_UMI_MMD_ICR_PERI2EN             0x0040
 153 /* Enable the peri3_csn to replace sdram2_csn */
 154 #define REG_UMI_MMD_ICR_PERI3EN             0x0020
 155 /* Enable sram bank1 for H/W controlled MRS */
 156 #define REG_UMI_MMD_ICR_MRSB1               0x0010
 157 /* Enable sram bank0 for H/W controlled MRS */
 158 #define REG_UMI_MMD_ICR_MRSB0               0x0008
 159 /* Polarity for assert3ed state of H/W controlled MRS */
 160 #define REG_UMI_MMD_ICR_MRSPOL              0x0004
 161 /* 0: S/W controllable ZZ/MRS/CRE/P-Mode pin */
 162 /* 1: H/W controlled ZZ/MRS/CRE/P-Mode, same timing as CS */
 163 #define REG_UMI_MMD_ICR_MRSMODE             0x0002
 164 /* MRS state for S/W controlled mode */
 165 #define REG_UMI_MMD_ICR_MRSSTATE            0x0001
 166
 167 /* REG_UMI_NAND_TCR bits */
 168 /* Enable software to control CS */
 169 #define REG_UMI_NAND_TCR_CS_SWCTRL          0x80000000
 170 /* 16-bit nand wordsize if set */
 171 #define REG_UMI_NAND_TCR_WORD16             0x40000000
 172 /* Bus turnaround cycle (n) */
 173 #define REG_UMI_NAND_TCR_TBTA_MASK          0x00070000
 174 /* Write pulse width cycle (n+1) */
 175 #define REG_UMI_NAND_TCR_TWP_MASK           0x0000f800
 176 /* Write recovery cycle (n+1) */
 177 #define REG_UMI_NAND_TCR_TWR_MASK           0x00000600
 178 /* Write address setup cycle (n+1) */
 179 #define REG_UMI_NAND_TCR_TAS_MASK           0x00000180
 180 /* Output enable delay cycle (n) */
 181 #define REG_UMI_NAND_TCR_TOE_MASK           0x00000060
 182 /* Read access cycle (n+2) */
 183 #define REG_UMI_NAND_TCR_TRC_TLC_MASK       0x0000001f
 184
 185 /* REG_UMI_NAND_RCSR bits */
 186 /* Status: Ready=1, Busy=0 */
 187 #define REG_UMI_NAND_RCSR_RDY               0x02
 188 /* Keep CS asserted during operation */
 189 #define REG_UMI_NAND_RCSR_CS_ASSERTED       0x01
 190
 191 /* REG_UMI_NAND_ECC_CSR bits */
 192 /* Interrupt status - read-only */
 193 #define REG_UMI_NAND_ECC_CSR_NANDINT        0x80000000
 194 /* Read: Status of ECC done, Write: clear ECC interrupt */
 195 #define REG_UMI_NAND_ECC_CSR_ECCINT_RAW     0x00800000
 196 /* Read: Status of R/B, Write: clear R/B interrupt */
 197 #define REG_UMI_NAND_ECC_CSR_RBINT_RAW      0x00400000
 198 /* 1 = Enable ECC Interrupt */
 199 #define REG_UMI_NAND_ECC_CSR_ECCINT_ENABLE  0x00008000
 200 /* 1 = Assert interrupt at rising edge of R/B_ */
 201 #define REG_UMI_NAND_ECC_CSR_RBINT_ENABLE   0x00004000
 202 /* Calculate ECC by 0=512 bytes, 1=256 bytes */
 203 #define REG_UMI_NAND_ECC_CSR_256BYTE        0x00000080
 204 /* Enable ECC in hardware */
 205 #define REG_UMI_NAND_ECC_CSR_ECC_ENABLE     0x00000001
 206
 207 /* REG_UMI_BCH_CTRL_STATUS bits */
 208 /* Shift to Indicate Number of correctable errors detected */
 209 #define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR_SHIFT 20
 210 /* Indicate Number of correctable errors detected */
 211 #define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR 0x00F00000
 212 /* Indicate Errors detected during read but uncorrectable */
 213 #define REG_UMI_BCH_CTRL_STATUS_UNCORR_ERR    0x00080000
 214 /* Indicate Errors detected during read and are correctable */
 215 #define REG_UMI_BCH_CTRL_STATUS_CORR_ERR      0x00040000
 216 /* Flag indicates BCH's ECC status of read process are valid */
 217 #define REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID  0x00020000
 218 /* Flag indicates BCH's ECC status of write process are valid */
 219 #define REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID  0x00010000
 220 /* Pause ECC calculation */
 221 #define REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC 0x00000010
 222 /* Enable Interrupt */
 223 #define REG_UMI_BCH_CTRL_STATUS_INT_EN        0x00000004
 224 /* Enable ECC during read */
 225 #define REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN     0x00000002
 226 /* Enable ECC during write */
 227 #define REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN     0x00000001
 228 /* Mask for location */
 229 #define REG_UMI_BCH_ERR_LOC_MASK              0x00001FFF
 230 /* location within a byte */
 231 #define REG_UMI_BCH_ERR_LOC_BYTE              0x00000007
 232 /* location within a word */
 233 #define REG_UMI_BCH_ERR_LOC_WORD              0x00000018
 234 /* location within a page (512 byte) */
 235 #define REG_UMI_BCH_ERR_LOC_PAGE              0x00001FE0
 236 #define REG_UMI_BCH_ERR_LOC_ADDR(index)     (__REG32(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16))
 237 #endif