arch/arm/mach-exynos/include/mach/regs-clock.h

   1 /* linux/arch/arm/mach-exynos4/include/mach/regs-clock.h
   2  *
   3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * EXYNOS4 - Clock register definitions
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #ifndef __ASM_ARCH_REGS_CLOCK_H
  14 #define __ASM_ARCH_REGS_CLOCK_H __FILE__
  15
  16 #include <plat/cpu.h>
  17 #include <mach/map.h>
  18
  19 #define S5P_CLKREG(x)                   (S5P_VA_CMU + (x))
  20
  21 #define S5P_CLKDIV_LEFTBUS              S5P_CLKREG(0x04500)
  22 #define S5P_CLKDIV_STAT_LEFTBUS         S5P_CLKREG(0x04600)
  23 #define S5P_CLKGATE_IP_LEFTBUS          S5P_CLKREG(0x04800)
  24
  25 #define S5P_CLKDIV_RIGHTBUS             S5P_CLKREG(0x08500)
  26 #define S5P_CLKDIV_STAT_RIGHTBUS        S5P_CLKREG(0x08600)
  27 #define S5P_CLKGATE_IP_RIGHTBUS         S5P_CLKREG(0x08800)
  28
  29 #define S5P_EPLL_LOCK                   S5P_CLKREG(0x0C010)
  30 #define S5P_VPLL_LOCK                   S5P_CLKREG(0x0C020)
  31
  32 #define S5P_EPLL_CON0                   S5P_CLKREG(0x0C110)
  33 #define S5P_EPLL_CON1                   S5P_CLKREG(0x0C114)
  34 #define S5P_VPLL_CON0                   S5P_CLKREG(0x0C120)
  35 #define S5P_VPLL_CON1                   S5P_CLKREG(0x0C124)
  36
  37 #define S5P_CLKSRC_TOP0                 S5P_CLKREG(0x0C210)
  38 #define S5P_CLKSRC_TOP1                 S5P_CLKREG(0x0C214)
  39 #define S5P_CLKSRC_CAM                  S5P_CLKREG(0x0C220)
  40 #define S5P_CLKSRC_TV                   S5P_CLKREG(0x0C224)
  41 #define S5P_CLKSRC_MFC                  S5P_CLKREG(0x0C228)
  42 #define S5P_CLKSRC_G3D                  S5P_CLKREG(0x0C22C)
  43 #define S5P_CLKSRC_IMAGE                S5P_CLKREG(0x0C230)
  44 #define S5P_CLKSRC_LCD0                 S5P_CLKREG(0x0C234)
  45 #define S5P_CLKSRC_MAUDIO               S5P_CLKREG(0x0C23C)
  46 #define S5P_CLKSRC_FSYS                 S5P_CLKREG(0x0C240)
  47 #define S5P_CLKSRC_PERIL0               S5P_CLKREG(0x0C250)
  48 #define S5P_CLKSRC_PERIL1               S5P_CLKREG(0x0C254)
  49
  50 #define S5P_CLKSRC_MASK_TOP             S5P_CLKREG(0x0C310)
  51 #define S5P_CLKSRC_MASK_CAM             S5P_CLKREG(0x0C320)
  52 #define S5P_CLKSRC_MASK_TV              S5P_CLKREG(0x0C324)
  53 #define S5P_CLKSRC_MASK_LCD0            S5P_CLKREG(0x0C334)
  54 #define S5P_CLKSRC_MASK_MAUDIO          S5P_CLKREG(0x0C33C)
  55 #define S5P_CLKSRC_MASK_FSYS            S5P_CLKREG(0x0C340)
  56 #define S5P_CLKSRC_MASK_PERIL0          S5P_CLKREG(0x0C350)
  57 #define S5P_CLKSRC_MASK_PERIL1          S5P_CLKREG(0x0C354)
  58
  59 #define S5P_CLKDIV_TOP                  S5P_CLKREG(0x0C510)
  60 #define S5P_CLKDIV_CAM                  S5P_CLKREG(0x0C520)
  61 #define S5P_CLKDIV_TV                   S5P_CLKREG(0x0C524)
  62 #define S5P_CLKDIV_MFC                  S5P_CLKREG(0x0C528)
  63 #define S5P_CLKDIV_G3D                  S5P_CLKREG(0x0C52C)
  64 #define S5P_CLKDIV_IMAGE                S5P_CLKREG(0x0C530)
  65 #define S5P_CLKDIV_LCD0                 S5P_CLKREG(0x0C534)
  66 #define S5P_CLKDIV_MAUDIO               S5P_CLKREG(0x0C53C)
  67 #define S5P_CLKDIV_FSYS0                S5P_CLKREG(0x0C540)
  68 #define S5P_CLKDIV_FSYS1                S5P_CLKREG(0x0C544)
  69 #define S5P_CLKDIV_FSYS2                S5P_CLKREG(0x0C548)
  70 #define S5P_CLKDIV_FSYS3                S5P_CLKREG(0x0C54C)
  71 #define S5P_CLKDIV_PERIL0               S5P_CLKREG(0x0C550)
  72 #define S5P_CLKDIV_PERIL1               S5P_CLKREG(0x0C554)
  73 #define S5P_CLKDIV_PERIL2               S5P_CLKREG(0x0C558)
  74 #define S5P_CLKDIV_PERIL3               S5P_CLKREG(0x0C55C)
  75 #define S5P_CLKDIV_PERIL4               S5P_CLKREG(0x0C560)
  76 #define S5P_CLKDIV_PERIL5               S5P_CLKREG(0x0C564)
  77 #define S5P_CLKDIV2_RATIO               S5P_CLKREG(0x0C580)
  78
  79 #define S5P_CLKDIV_STAT_TOP             S5P_CLKREG(0x0C610)
  80
  81 #define S5P_CLKGATE_SCLKCAM             S5P_CLKREG(0x0C820)
  82 #define S5P_CLKGATE_IP_CAM              S5P_CLKREG(0x0C920)
  83 #define S5P_CLKGATE_IP_TV               S5P_CLKREG(0x0C924)
  84 #define S5P_CLKGATE_IP_MFC              S5P_CLKREG(0x0C928)
  85 #define S5P_CLKGATE_IP_G3D              S5P_CLKREG(0x0C92C)
  86 #define S5P_CLKGATE_IP_IMAGE            (soc_is_exynos4210() ? \
  87                                         S5P_CLKREG(0x0C930) : \
  88                                         S5P_CLKREG(0x04930))
  89 #define S5P_CLKGATE_IP_IMAGE_4210       S5P_CLKREG(0x0C930)
  90 #define S5P_CLKGATE_IP_IMAGE_4212       S5P_CLKREG(0x04930)
  91 #define S5P_CLKGATE_IP_LCD0             S5P_CLKREG(0x0C934)
  92 #define S5P_CLKGATE_IP_FSYS             S5P_CLKREG(0x0C940)
  93 #define S5P_CLKGATE_IP_GPS              S5P_CLKREG(0x0C94C)
  94 #define S5P_CLKGATE_IP_PERIL            S5P_CLKREG(0x0C950)
  95 #define S5P_CLKGATE_IP_PERIR            (soc_is_exynos4210() ? \
  96                                         S5P_CLKREG(0x0C960) : \
  97                                         S5P_CLKREG(0x08960))
  98 #define S5P_CLKGATE_IP_PERIR_4210       S5P_CLKREG(0x0C960)
  99 #define S5P_CLKGATE_IP_PERIR_4212       S5P_CLKREG(0x08960)
 100 #define S5P_CLKGATE_BLOCK               S5P_CLKREG(0x0C970)
 101
 102 #define S5P_CLKSRC_MASK_DMC             S5P_CLKREG(0x10300)
 103 #define S5P_CLKSRC_DMC                  S5P_CLKREG(0x10200)
 104 #define S5P_CLKDIV_DMC0                 S5P_CLKREG(0x10500)
 105 #define S5P_CLKDIV_DMC1                 S5P_CLKREG(0x10504)
 106 #define S5P_CLKDIV_STAT_DMC0            S5P_CLKREG(0x10600)
 107 #define S5P_CLKGATE_IP_DMC              S5P_CLKREG(0x10900)
 108
 109 #define S5P_APLL_LOCK                   S5P_CLKREG(0x14000)
 110 #define S5P_MPLL_LOCK                   (soc_is_exynos4210() ? \
 111                                         S5P_CLKREG(0x14004) :  \
 112                                         S5P_CLKREG(0x10008))
 113 #define S5P_APLL_CON0                   S5P_CLKREG(0x14100)
 114 #define S5P_APLL_CON1                   S5P_CLKREG(0x14104)
 115 #define S5P_MPLL_CON0                   (soc_is_exynos4210() ? \
 116                                         S5P_CLKREG(0x14108) : \
 117                                         S5P_CLKREG(0x10108))
 118 #define S5P_MPLL_CON1                   (soc_is_exynos4210() ? \
 119                                         S5P_CLKREG(0x1410C) : \
 120                                         S5P_CLKREG(0x1010C))
 121
 122 #define S5P_CLKSRC_CPU                  S5P_CLKREG(0x14200)
 123 #define S5P_CLKMUX_STATCPU              S5P_CLKREG(0x14400)
 124
 125 #define S5P_CLKDIV_CPU                  S5P_CLKREG(0x14500)
 126 #define S5P_CLKDIV_CPU1                 S5P_CLKREG(0x14504)
 127 #define S5P_CLKDIV_STATCPU              S5P_CLKREG(0x14600)
 128 #define S5P_CLKDIV_STATCPU1             S5P_CLKREG(0x14604)
 129
 130 #define S5P_CLKGATE_SCLKCPU             S5P_CLKREG(0x14800)
 131 #define S5P_CLKGATE_IP_CPU              S5P_CLKREG(0x14900)
 132
 133 #define S5P_APLL_LOCKTIME               (0x1C20)        /* 300us */
 134
 135 #define S5P_APLLCON0_ENABLE_SHIFT       (31)
 136 #define S5P_APLLCON0_LOCKED_SHIFT       (29)
 137 #define S5P_APLL_VAL_1000               ((250 << 16) | (6 << 8) | 1)
 138 #define S5P_APLL_VAL_800                ((200 << 16) | (6 << 8) | 1)
 139
 140 #define S5P_EPLLCON0_ENABLE_SHIFT       (31)
 141 #define S5P_EPLLCON0_LOCKED_SHIFT       (29)
 142
 143 #define S5P_VPLLCON0_ENABLE_SHIFT       (31)
 144 #define S5P_VPLLCON0_LOCKED_SHIFT       (29)
 145
 146 #define S5P_CLKSRC_CPU_MUXCORE_SHIFT    (16)
 147 #define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
 148
 149 #define S5P_CLKDIV_CPU0_CORE_SHIFT      (0)
 150 #define S5P_CLKDIV_CPU0_CORE_MASK       (0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT)
 151 #define S5P_CLKDIV_CPU0_COREM0_SHIFT    (4)
 152 #define S5P_CLKDIV_CPU0_COREM0_MASK     (0x7 << S5P_CLKDIV_CPU0_COREM0_SHIFT)
 153 #define S5P_CLKDIV_CPU0_COREM1_SHIFT    (8)
 154 #define S5P_CLKDIV_CPU0_COREM1_MASK     (0x7 << S5P_CLKDIV_CPU0_COREM1_SHIFT)
 155 #define S5P_CLKDIV_CPU0_PERIPH_SHIFT    (12)
 156 #define S5P_CLKDIV_CPU0_PERIPH_MASK     (0x7 << S5P_CLKDIV_CPU0_PERIPH_SHIFT)
 157 #define S5P_CLKDIV_CPU0_ATB_SHIFT       (16)
 158 #define S5P_CLKDIV_CPU0_ATB_MASK        (0x7 << S5P_CLKDIV_CPU0_ATB_SHIFT)
 159 #define S5P_CLKDIV_CPU0_PCLKDBG_SHIFT   (20)
 160 #define S5P_CLKDIV_CPU0_PCLKDBG_MASK    (0x7 << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT)
 161 #define S5P_CLKDIV_CPU0_APLL_SHIFT      (24)
 162 #define S5P_CLKDIV_CPU0_APLL_MASK       (0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT)
 163
 164 #define S5P_CLKDIV_DMC0_ACP_SHIFT       (0)
 165 #define S5P_CLKDIV_DMC0_ACP_MASK        (0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT)
 166 #define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT   (4)
 167 #define S5P_CLKDIV_DMC0_ACPPCLK_MASK    (0x7 << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT)
 168 #define S5P_CLKDIV_DMC0_DPHY_SHIFT      (8)
 169 #define S5P_CLKDIV_DMC0_DPHY_MASK       (0x7 << S5P_CLKDIV_DMC0_DPHY_SHIFT)
 170 #define S5P_CLKDIV_DMC0_DMC_SHIFT       (12)
 171 #define S5P_CLKDIV_DMC0_DMC_MASK        (0x7 << S5P_CLKDIV_DMC0_DMC_SHIFT)
 172 #define S5P_CLKDIV_DMC0_DMCD_SHIFT      (16)
 173 #define S5P_CLKDIV_DMC0_DMCD_MASK       (0x7 << S5P_CLKDIV_DMC0_DMCD_SHIFT)
 174 #define S5P_CLKDIV_DMC0_DMCP_SHIFT      (20)
 175 #define S5P_CLKDIV_DMC0_DMCP_MASK       (0x7 << S5P_CLKDIV_DMC0_DMCP_SHIFT)
 176 #define S5P_CLKDIV_DMC0_COPY2_SHIFT     (24)
 177 #define S5P_CLKDIV_DMC0_COPY2_MASK      (0x7 << S5P_CLKDIV_DMC0_COPY2_SHIFT)
 178 #define S5P_CLKDIV_DMC0_CORETI_SHIFT    (28)
 179 #define S5P_CLKDIV_DMC0_CORETI_MASK     (0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT)
 180
 181 #define S5P_CLKDIV_TOP_ACLK200_SHIFT    (0)
 182 #define S5P_CLKDIV_TOP_ACLK200_MASK     (0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT)
 183 #define S5P_CLKDIV_TOP_ACLK100_SHIFT    (4)
 184 #define S5P_CLKDIV_TOP_ACLK100_MASK     (0xf << S5P_CLKDIV_TOP_ACLK100_SHIFT)
 185 #define S5P_CLKDIV_TOP_ACLK160_SHIFT    (8)
 186 #define S5P_CLKDIV_TOP_ACLK160_MASK     (0x7 << S5P_CLKDIV_TOP_ACLK160_SHIFT)
 187 #define S5P_CLKDIV_TOP_ACLK133_SHIFT    (12)
 188 #define S5P_CLKDIV_TOP_ACLK133_MASK     (0x7 << S5P_CLKDIV_TOP_ACLK133_SHIFT)
 189 #define S5P_CLKDIV_TOP_ONENAND_SHIFT    (16)
 190 #define S5P_CLKDIV_TOP_ONENAND_MASK     (0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT)
 191
 192 #define S5P_CLKDIV_BUS_GDLR_SHIFT       (0)
 193 #define S5P_CLKDIV_BUS_GDLR_MASK        (0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT)
 194 #define S5P_CLKDIV_BUS_GPLR_SHIFT       (4)
 195 #define S5P_CLKDIV_BUS_GPLR_MASK        (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
 196
 197 /* Only for EXYNOS4210 */
 198
 199 #define S5P_CLKSRC_LCD1                 S5P_CLKREG(0x0C238)
 200 #define S5P_CLKSRC_MASK_LCD1            S5P_CLKREG(0x0C338)
 201 #define S5P_CLKDIV_LCD1                 S5P_CLKREG(0x0C538)
 202 #define S5P_CLKGATE_IP_LCD1             S5P_CLKREG(0x0C938)
 203
 204 /* Compatibility defines and inclusion */
 205
 206 #include <mach/regs-pmu.h>
 207
 208 #define S5P_EPLL_CON                    S5P_EPLL_CON0
 209
 210 #endif /* __ASM_ARCH_REGS_CLOCK_H */