arch/arm/mach-exynos/include/mach/regs-pmu.h

   1 /* linux/arch/arm/mach-exynos4/include/mach/regs-pmu.h
   2  *
   3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * EXYNOS4 - Power management unit definition
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #ifndef __ASM_ARCH_REGS_PMU_H
  14 #define __ASM_ARCH_REGS_PMU_H __FILE__
  15
  16 #include <mach/map.h>
  17
  18 #define S5P_PMUREG(x)                           (S5P_VA_PMU + (x))
  19
  20 #define S5P_CENTRAL_SEQ_CONFIGURATION           S5P_PMUREG(0x0200)
  21
  22 #define S5P_CENTRAL_LOWPWR_CFG                  (1 << 16)
  23
  24 #define S5P_CENTRAL_SEQ_OPTION                  S5P_PMUREG(0x0208)
  25
  26 #define S5P_USE_STANDBY_WFI0                    (1 << 16)
  27 #define S5P_USE_STANDBY_WFI1                    (1 << 17)
  28 #define S5P_USE_STANDBYWFI_ISP_ARM              (1 << 18)
  29 #define S5P_USE_STANDBY_WFE0                    (1 << 24)
  30 #define S5P_USE_STANDBY_WFE1                    (1 << 25)
  31 #define S5P_USE_STANDBYWFE_ISP_ARM              (1 << 26)
  32
  33 #define S5P_SWRESET                             S5P_PMUREG(0x0400)
  34
  35 #define S5P_WAKEUP_STAT                         S5P_PMUREG(0x0600)
  36 #define S5P_EINT_WAKEUP_MASK                    S5P_PMUREG(0x0604)
  37 #define S5P_WAKEUP_MASK                         S5P_PMUREG(0x0608)
  38
  39 #define S5P_HDMI_PHY_CONTROL                    S5P_PMUREG(0x0700)
  40 #define S5P_HDMI_PHY_ENABLE                     (1 << 0)
  41
  42 #define S5P_DAC_PHY_CONTROL                     S5P_PMUREG(0x070C)
  43 #define S5P_DAC_PHY_ENABLE                      (1 << 0)
  44
  45 #define S5P_MIPI_DPHY_CONTROL(n)                S5P_PMUREG(0x0710 + (n) * 4)
  46 #define S5P_MIPI_DPHY_ENABLE                    (1 << 0)
  47 #define S5P_MIPI_DPHY_SRESETN                   (1 << 1)
  48 #define S5P_MIPI_DPHY_MRESETN                   (1 << 2)
  49
  50 #define S5P_INFORM0                             S5P_PMUREG(0x0800)
  51 #define S5P_INFORM1                             S5P_PMUREG(0x0804)
  52 #define S5P_INFORM2                             S5P_PMUREG(0x0808)
  53 #define S5P_INFORM3                             S5P_PMUREG(0x080C)
  54 #define S5P_INFORM4                             S5P_PMUREG(0x0810)
  55 #define S5P_INFORM5                             S5P_PMUREG(0x0814)
  56 #define S5P_INFORM6                             S5P_PMUREG(0x0818)
  57 #define S5P_INFORM7                             S5P_PMUREG(0x081C)
  58
  59 #define S5P_ARM_CORE0_LOWPWR                    S5P_PMUREG(0x1000)
  60 #define S5P_DIS_IRQ_CORE0                       S5P_PMUREG(0x1004)
  61 #define S5P_DIS_IRQ_CENTRAL0                    S5P_PMUREG(0x1008)
  62 #define S5P_ARM_CORE1_LOWPWR                    S5P_PMUREG(0x1010)
  63 #define S5P_DIS_IRQ_CORE1                       S5P_PMUREG(0x1014)
  64 #define S5P_DIS_IRQ_CENTRAL1                    S5P_PMUREG(0x1018)
  65 #define S5P_ARM_COMMON_LOWPWR                   S5P_PMUREG(0x1080)
  66 #define S5P_L2_0_LOWPWR                         S5P_PMUREG(0x10C0)
  67 #define S5P_L2_1_LOWPWR                         S5P_PMUREG(0x10C4)
  68 #define S5P_CMU_ACLKSTOP_LOWPWR                 S5P_PMUREG(0x1100)
  69 #define S5P_CMU_SCLKSTOP_LOWPWR                 S5P_PMUREG(0x1104)
  70 #define S5P_CMU_RESET_LOWPWR                    S5P_PMUREG(0x110C)
  71 #define S5P_APLL_SYSCLK_LOWPWR                  S5P_PMUREG(0x1120)
  72 #define S5P_MPLL_SYSCLK_LOWPWR                  S5P_PMUREG(0x1124)
  73 #define S5P_VPLL_SYSCLK_LOWPWR                  S5P_PMUREG(0x1128)
  74 #define S5P_EPLL_SYSCLK_LOWPWR                  S5P_PMUREG(0x112C)
  75 #define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR        S5P_PMUREG(0x1138)
  76 #define S5P_CMU_RESET_GPSALIVE_LOWPWR           S5P_PMUREG(0x113C)
  77 #define S5P_CMU_CLKSTOP_CAM_LOWPWR              S5P_PMUREG(0x1140)
  78 #define S5P_CMU_CLKSTOP_TV_LOWPWR               S5P_PMUREG(0x1144)
  79 #define S5P_CMU_CLKSTOP_MFC_LOWPWR              S5P_PMUREG(0x1148)
  80 #define S5P_CMU_CLKSTOP_G3D_LOWPWR              S5P_PMUREG(0x114C)
  81 #define S5P_CMU_CLKSTOP_LCD0_LOWPWR             S5P_PMUREG(0x1150)
  82 #define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR           S5P_PMUREG(0x1158)
  83 #define S5P_CMU_CLKSTOP_GPS_LOWPWR              S5P_PMUREG(0x115C)
  84 #define S5P_CMU_RESET_CAM_LOWPWR                S5P_PMUREG(0x1160)
  85 #define S5P_CMU_RESET_TV_LOWPWR                 S5P_PMUREG(0x1164)
  86 #define S5P_CMU_RESET_MFC_LOWPWR                S5P_PMUREG(0x1168)
  87 #define S5P_CMU_RESET_G3D_LOWPWR                S5P_PMUREG(0x116C)
  88 #define S5P_CMU_RESET_LCD0_LOWPWR               S5P_PMUREG(0x1170)
  89 #define S5P_CMU_RESET_MAUDIO_LOWPWR             S5P_PMUREG(0x1178)
  90 #define S5P_CMU_RESET_GPS_LOWPWR                S5P_PMUREG(0x117C)
  91 #define S5P_TOP_BUS_LOWPWR                      S5P_PMUREG(0x1180)
  92 #define S5P_TOP_RETENTION_LOWPWR                S5P_PMUREG(0x1184)
  93 #define S5P_TOP_PWR_LOWPWR                      S5P_PMUREG(0x1188)
  94 #define S5P_LOGIC_RESET_LOWPWR                  S5P_PMUREG(0x11A0)
  95 #define S5P_ONENAND_MEM_LOWPWR                  S5P_PMUREG(0x11C0)
  96 #define S5P_G2D_ACP_MEM_LOWPWR                  S5P_PMUREG(0x11C8)
  97 #define S5P_USBOTG_MEM_LOWPWR                   S5P_PMUREG(0x11CC)
  98 #define S5P_HSMMC_MEM_LOWPWR                    S5P_PMUREG(0x11D0)
  99 #define S5P_CSSYS_MEM_LOWPWR                    S5P_PMUREG(0x11D4)
 100 #define S5P_SECSS_MEM_LOWPWR                    S5P_PMUREG(0x11D8)
 101 #define S5P_PAD_RETENTION_DRAM_LOWPWR           S5P_PMUREG(0x1200)
 102 #define S5P_PAD_RETENTION_MAUDIO_LOWPWR         S5P_PMUREG(0x1204)
 103 #define S5P_PAD_RETENTION_GPIO_LOWPWR           S5P_PMUREG(0x1220)
 104 #define S5P_PAD_RETENTION_UART_LOWPWR           S5P_PMUREG(0x1224)
 105 #define S5P_PAD_RETENTION_MMCA_LOWPWR           S5P_PMUREG(0x1228)
 106 #define S5P_PAD_RETENTION_MMCB_LOWPWR           S5P_PMUREG(0x122C)
 107 #define S5P_PAD_RETENTION_EBIA_LOWPWR           S5P_PMUREG(0x1230)
 108 #define S5P_PAD_RETENTION_EBIB_LOWPWR           S5P_PMUREG(0x1234)
 109 #define S5P_PAD_RETENTION_ISOLATION_LOWPWR      S5P_PMUREG(0x1240)
 110 #define S5P_PAD_RETENTION_ALV_SEL_LOWPWR        S5P_PMUREG(0x1260)
 111 #define S5P_XUSBXTI_LOWPWR                      S5P_PMUREG(0x1280)
 112 #define S5P_XXTI_LOWPWR                         S5P_PMUREG(0x1284)
 113 #define S5P_EXT_REGULATOR_LOWPWR                S5P_PMUREG(0x12C0)
 114 #define S5P_GPIO_MODE_LOWPWR                    S5P_PMUREG(0x1300)
 115 #define S5P_GPIO_MODE_MAUDIO_LOWPWR             S5P_PMUREG(0x1340)
 116 #define S5P_CAM_LOWPWR                          S5P_PMUREG(0x1380)
 117 #define S5P_TV_LOWPWR                           S5P_PMUREG(0x1384)
 118 #define S5P_MFC_LOWPWR                          S5P_PMUREG(0x1388)
 119 #define S5P_G3D_LOWPWR                          S5P_PMUREG(0x138C)
 120 #define S5P_LCD0_LOWPWR                         S5P_PMUREG(0x1390)
 121 #define S5P_MAUDIO_LOWPWR                       S5P_PMUREG(0x1398)
 122 #define S5P_GPS_LOWPWR                          S5P_PMUREG(0x139C)
 123 #define S5P_GPS_ALIVE_LOWPWR                    S5P_PMUREG(0x13A0)
 124
 125 #define S5P_ARM_CORE0_CONFIGURATION             S5P_PMUREG(0x2000)
 126 #define S5P_ARM_CORE0_OPTION                    S5P_PMUREG(0x2008)
 127 #define S5P_ARM_CORE1_CONFIGURATION             S5P_PMUREG(0x2080)
 128 #define S5P_ARM_CORE1_STATUS                    S5P_PMUREG(0x2084)
 129 #define S5P_ARM_CORE1_OPTION                    S5P_PMUREG(0x2088)
 130
 131 #define S5P_ARM_COMMON_OPTION                   S5P_PMUREG(0x2408)
 132 #define S5P_TOP_PWR_OPTION                      S5P_PMUREG(0x2C48)
 133 #define S5P_CAM_OPTION                          S5P_PMUREG(0x3C08)
 134 #define S5P_TV_OPTION                           S5P_PMUREG(0x3C28)
 135 #define S5P_MFC_OPTION                          S5P_PMUREG(0x3C48)
 136 #define S5P_G3D_OPTION                          S5P_PMUREG(0x3C68)
 137 #define S5P_LCD0_OPTION                         S5P_PMUREG(0x3C88)
 138 #define S5P_LCD1_OPTION                         S5P_PMUREG(0x3CA8)
 139 #define S5P_MAUDIO_OPTION                       S5P_PMUREG(0x3CC8)
 140 #define S5P_GPS_OPTION                          S5P_PMUREG(0x3CE8)
 141 #define S5P_GPS_ALIVE_OPTION                    S5P_PMUREG(0x3D08)
 142
 143 #define S5P_PAD_RET_MAUDIO_OPTION               S5P_PMUREG(0x3028)
 144 #define S5P_PAD_RET_GPIO_OPTION                 S5P_PMUREG(0x3108)
 145 #define S5P_PAD_RET_UART_OPTION                 S5P_PMUREG(0x3128)
 146 #define S5P_PAD_RET_MMCA_OPTION                 S5P_PMUREG(0x3148)
 147 #define S5P_PAD_RET_MMCB_OPTION                 S5P_PMUREG(0x3168)
 148 #define S5P_PAD_RET_EBIA_OPTION                 S5P_PMUREG(0x3188)
 149 #define S5P_PAD_RET_EBIB_OPTION                 S5P_PMUREG(0x31A8)
 150
 151 #define S5P_PMU_CAM_CONF                        S5P_PMUREG(0x3C00)
 152 #define S5P_PMU_TV_CONF                         S5P_PMUREG(0x3C20)
 153 #define S5P_PMU_MFC_CONF                        S5P_PMUREG(0x3C40)
 154 #define S5P_PMU_G3D_CONF                        S5P_PMUREG(0x3C60)
 155 #define S5P_PMU_LCD0_CONF                       S5P_PMUREG(0x3C80)
 156 #define S5P_PMU_GPS_CONF                        S5P_PMUREG(0x3CE0)
 157
 158 #define S5P_PMU_SATA_PHY_CONTROL_EN             0x1
 159 #define S5P_CORE_LOCAL_PWR_EN                   0x3
 160 #define S5P_INT_LOCAL_PWR_EN                    0x7
 161
 162 #define S5P_CHECK_SLEEP                         0x00000BAD
 163
 164 /* Only for EXYNOS4210 */
 165 #define S5P_USBHOST_PHY_CONTROL         S5P_PMUREG(0x0708)
 166 #define S5P_USBHOST_PHY_ENABLE          (1 << 0)
 167
 168 #define S5P_PMU_SATA_PHY_CONTROL        S5P_PMUREG(0x0720)
 169
 170 #define S5P_CMU_CLKSTOP_LCD1_LOWPWR     S5P_PMUREG(0x1154)
 171 #define S5P_CMU_RESET_LCD1_LOWPWR       S5P_PMUREG(0x1174)
 172 #define S5P_MODIMIF_MEM_LOWPWR          S5P_PMUREG(0x11C4)
 173 #define S5P_PCIE_MEM_LOWPWR             S5P_PMUREG(0x11E0)
 174 #define S5P_SATA_MEM_LOWPWR             S5P_PMUREG(0x11E4)
 175 #define S5P_LCD1_LOWPWR                 S5P_PMUREG(0x1394)
 176
 177 #define S5P_PMU_LCD1_CONF               S5P_PMUREG(0x3CA0)
 178
 179 /* Only for EXYNOS4212 */
 180 #define S5P_ISP_ARM_LOWPWR                      S5P_PMUREG(0x1050)
 181 #define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR        S5P_PMUREG(0x1054)
 182 #define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR      S5P_PMUREG(0x1058)
 183 #define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR         S5P_PMUREG(0x1110)
 184 #define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR         S5P_PMUREG(0x1114)
 185 #define S5P_CMU_RESET_COREBLK_LOWPWR            S5P_PMUREG(0x111C)
 186 #define S5P_MPLLUSER_SYSCLK_LOWPWR              S5P_PMUREG(0x1130)
 187 #define S5P_CMU_CLKSTOP_ISP_LOWPWR              S5P_PMUREG(0x1154)
 188 #define S5P_CMU_RESET_ISP_LOWPWR                S5P_PMUREG(0x1174)
 189 #define S5P_TOP_BUS_COREBLK_LOWPWR              S5P_PMUREG(0x1190)
 190 #define S5P_TOP_RETENTION_COREBLK_LOWPWR        S5P_PMUREG(0x1194)
 191 #define S5P_TOP_PWR_COREBLK_LOWPWR              S5P_PMUREG(0x1198)
 192 #define S5P_OSCCLK_GATE_LOWPWR                  S5P_PMUREG(0x11A4)
 193 #define S5P_LOGIC_RESET_COREBLK_LOWPWR          S5P_PMUREG(0x11B0)
 194 #define S5P_OSCCLK_GATE_COREBLK_LOWPWR          S5P_PMUREG(0x11B4)
 195 #define S5P_HSI_MEM_LOWPWR                      S5P_PMUREG(0x11C4)
 196 #define S5P_ROTATOR_MEM_LOWPWR                  S5P_PMUREG(0x11DC)
 197 #define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR   S5P_PMUREG(0x123C)
 198 #define S5P_PAD_ISOLATION_COREBLK_LOWPWR        S5P_PMUREG(0x1250)
 199 #define S5P_GPIO_MODE_COREBLK_LOWPWR            S5P_PMUREG(0x1320)
 200 #define S5P_TOP_ASB_RESET_LOWPWR                S5P_PMUREG(0x1344)
 201 #define S5P_TOP_ASB_ISOLATION_LOWPWR            S5P_PMUREG(0x1348)
 202 #define S5P_ISP_LOWPWR                          S5P_PMUREG(0x1394)
 203 #define S5P_DRAM_FREQ_DOWN_LOWPWR               S5P_PMUREG(0x13B0)
 204 #define S5P_DDRPHY_DLLOFF_LOWPWR                S5P_PMUREG(0x13B4)
 205 #define S5P_CMU_SYSCLK_ISP_LOWPWR               S5P_PMUREG(0x13B8)
 206 #define S5P_CMU_SYSCLK_GPS_LOWPWR               S5P_PMUREG(0x13BC)
 207 #define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR           S5P_PMUREG(0x13C0)
 208
 209 #define S5P_ARM_L2_0_OPTION                     S5P_PMUREG(0x2608)
 210 #define S5P_ARM_L2_1_OPTION                     S5P_PMUREG(0x2628)
 211 #define S5P_ONENAND_MEM_OPTION                  S5P_PMUREG(0x2E08)
 212 #define S5P_HSI_MEM_OPTION                      S5P_PMUREG(0x2E28)
 213 #define S5P_G2D_ACP_MEM_OPTION                  S5P_PMUREG(0x2E48)
 214 #define S5P_USBOTG_MEM_OPTION                   S5P_PMUREG(0x2E68)
 215 #define S5P_HSMMC_MEM_OPTION                    S5P_PMUREG(0x2E88)
 216 #define S5P_CSSYS_MEM_OPTION                    S5P_PMUREG(0x2EA8)
 217 #define S5P_SECSS_MEM_OPTION                    S5P_PMUREG(0x2EC8)
 218 #define S5P_ROTATOR_MEM_OPTION                  S5P_PMUREG(0x2F48)
 219
 220 #endif /* __ASM_ARCH_REGS_PMU_H */