arch/arm/mach-ixp4xx/common.c

   1 /*
   2  * arch/arm/mach-ixp4xx/common.c
   3  *
   4  * Generic code shared across all IXP4XX platforms
   5  *
   6  * Maintainer: Deepak Saxena <dsaxena@plexity.net>
   7  *
   8  * Copyright 2002 (c) Intel Corporation
   9  * Copyright 2003-2004 (c) MontaVista, Software, Inc.
  10  *
  11  * This file is licensed under  the terms of the GNU General Public
  12  * License version 2. This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/mm.h>
  18 #include <linux/init.h>
  19 #include <linux/serial.h>
  20 #include <linux/tty.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/serial_core.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/bitops.h>
  25 #include <linux/time.h>
  26 #include <linux/timex.h>
  27 #include <linux/clocksource.h>
  28 #include <linux/clockchips.h>
  29 #include <linux/io.h>
  30 #include <linux/export.h>
  31
  32 #include <mach/udc.h>
  33 #include <mach/hardware.h>
  34 #include <asm/uaccess.h>
  35 #include <asm/pgtable.h>
  36 #include <asm/page.h>
  37 #include <asm/irq.h>
  38 #include <asm/sched_clock.h>
  39
  40 #include <asm/mach/map.h>
  41 #include <asm/mach/irq.h>
  42 #include <asm/mach/time.h>
  43
  44 static void __init ixp4xx_clocksource_init(void);
  45 static void __init ixp4xx_clockevent_init(void);
  46 static struct clock_event_device clockevent_ixp4xx;
  47
  48 /*************************************************************************
  49  * IXP4xx chipset I/O mapping
  50  *************************************************************************/
  51 static struct map_desc ixp4xx_io_desc[] __initdata = {
  52         {       /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
  53                 .virtual        = IXP4XX_PERIPHERAL_BASE_VIRT,
  54                 .pfn            = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
  55                 .length         = IXP4XX_PERIPHERAL_REGION_SIZE,
  56                 .type           = MT_DEVICE
  57         }, {    /* Expansion Bus Config Registers */
  58                 .virtual        = IXP4XX_EXP_CFG_BASE_VIRT,
  59                 .pfn            = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
  60                 .length         = IXP4XX_EXP_CFG_REGION_SIZE,
  61                 .type           = MT_DEVICE
  62         }, {    /* PCI Registers */
  63                 .virtual        = IXP4XX_PCI_CFG_BASE_VIRT,
  64                 .pfn            = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
  65                 .length         = IXP4XX_PCI_CFG_REGION_SIZE,
  66                 .type           = MT_DEVICE
  67         },
  68 #ifdef CONFIG_DEBUG_LL
  69         {       /* Debug UART mapping */
  70                 .virtual        = IXP4XX_DEBUG_UART_BASE_VIRT,
  71                 .pfn            = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),
  72                 .length         = IXP4XX_DEBUG_UART_REGION_SIZE,
  73                 .type           = MT_DEVICE
  74         }
  75 #endif
  76 };
  77
  78 void __init ixp4xx_map_io(void)
  79 {
  80         iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
  81 }
  82
  83
  84 /*************************************************************************
  85  * IXP4xx chipset IRQ handling
  86  *
  87  * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
  88  *       (be it PCI or something else) configures that GPIO line
  89  *       as an IRQ.
  90  **************************************************************************/
  91 enum ixp4xx_irq_type {
  92         IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
  93 };
  94
  95 /* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */
  96 static unsigned long long ixp4xx_irq_edge = 0;
  97
  98 /*
  99  * IRQ -> GPIO mapping table
 100  */
 101 static signed char irq2gpio[32] = {
 102         -1, -1, -1, -1, -1, -1,  0,  1,
 103         -1, -1, -1, -1, -1, -1, -1, -1,
 104         -1, -1, -1,  2,  3,  4,  5,  6,
 105          7,  8,  9, 10, 11, 12, -1, -1,
 106 };
 107
 108 int gpio_to_irq(int gpio)
 109 {
 110         int irq;
 111
 112         for (irq = 0; irq < 32; irq++) {
 113                 if (irq2gpio[irq] == gpio)
 114                         return irq;
 115         }
 116         return -EINVAL;
 117 }
 118 EXPORT_SYMBOL(gpio_to_irq);
 119
 120 int irq_to_gpio(unsigned int irq)
 121 {
 122         int gpio = (irq < 32) ? irq2gpio[irq] : -EINVAL;
 123
 124         if (gpio == -1)
 125                 return -EINVAL;
 126
 127         return gpio;
 128 }
 129 EXPORT_SYMBOL(irq_to_gpio);
 130
 131 static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type)
 132 {
 133         int line = irq2gpio[d->irq];
 134         u32 int_style;
 135         enum ixp4xx_irq_type irq_type;
 136         volatile u32 *int_reg;
 137
 138         /*
 139          * Only for GPIO IRQs
 140          */
 141         if (line < 0)
 142                 return -EINVAL;
 143
 144         switch (type){
 145         case IRQ_TYPE_EDGE_BOTH:
 146                 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
 147                 irq_type = IXP4XX_IRQ_EDGE;
 148                 break;
 149         case IRQ_TYPE_EDGE_RISING:
 150                 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
 151                 irq_type = IXP4XX_IRQ_EDGE;
 152                 break;
 153         case IRQ_TYPE_EDGE_FALLING:
 154                 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
 155                 irq_type = IXP4XX_IRQ_EDGE;
 156                 break;
 157         case IRQ_TYPE_LEVEL_HIGH:
 158                 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
 159                 irq_type = IXP4XX_IRQ_LEVEL;
 160                 break;
 161         case IRQ_TYPE_LEVEL_LOW:
 162                 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
 163                 irq_type = IXP4XX_IRQ_LEVEL;
 164                 break;
 165         default:
 166                 return -EINVAL;
 167         }
 168
 169         if (irq_type == IXP4XX_IRQ_EDGE)
 170                 ixp4xx_irq_edge |= (1 << d->irq);
 171         else
 172                 ixp4xx_irq_edge &= ~(1 << d->irq);
 173
 174         if (line >= 8) {        /* pins 8-15 */
 175                 line -= 8;
 176                 int_reg = IXP4XX_GPIO_GPIT2R;
 177         } else {                /* pins 0-7 */
 178                 int_reg = IXP4XX_GPIO_GPIT1R;
 179         }
 180
 181         /* Clear the style for the appropriate pin */
 182         *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
 183                         (line * IXP4XX_GPIO_STYLE_SIZE));
 184
 185         *IXP4XX_GPIO_GPISR = (1 << line);
 186
 187         /* Set the new style */
 188         *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
 189
 190         /* Configure the line as an input */
 191         gpio_line_config(irq2gpio[d->irq], IXP4XX_GPIO_IN);
 192
 193         return 0;
 194 }
 195
 196 static void ixp4xx_irq_mask(struct irq_data *d)
 197 {
 198         if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
 199                 *IXP4XX_ICMR2 &= ~(1 << (d->irq - 32));
 200         else
 201                 *IXP4XX_ICMR &= ~(1 << d->irq);
 202 }
 203
 204 static void ixp4xx_irq_ack(struct irq_data *d)
 205 {
 206         int line = (d->irq < 32) ? irq2gpio[d->irq] : -1;
 207
 208         if (line >= 0)
 209                 *IXP4XX_GPIO_GPISR = (1 << line);
 210 }
 211
 212 /*
 213  * Level triggered interrupts on GPIO lines can only be cleared when the
 214  * interrupt condition disappears.
 215  */
 216 static void ixp4xx_irq_unmask(struct irq_data *d)
 217 {
 218         if (!(ixp4xx_irq_edge & (1 << d->irq)))
 219                 ixp4xx_irq_ack(d);
 220
 221         if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
 222                 *IXP4XX_ICMR2 |= (1 << (d->irq - 32));
 223         else
 224                 *IXP4XX_ICMR |= (1 << d->irq);
 225 }
 226
 227 static struct irq_chip ixp4xx_irq_chip = {
 228         .name           = "IXP4xx",
 229         .irq_ack        = ixp4xx_irq_ack,
 230         .irq_mask       = ixp4xx_irq_mask,
 231         .irq_unmask     = ixp4xx_irq_unmask,
 232         .irq_set_type   = ixp4xx_set_irq_type,
 233 };
 234
 235 void __init ixp4xx_init_irq(void)
 236 {
 237         int i = 0;
 238
 239         /* Route all sources to IRQ instead of FIQ */
 240         *IXP4XX_ICLR = 0x0;
 241
 242         /* Disable all interrupt */
 243         *IXP4XX_ICMR = 0x0;
 244
 245         if (cpu_is_ixp46x() || cpu_is_ixp43x()) {
 246                 /* Route upper 32 sources to IRQ instead of FIQ */
 247                 *IXP4XX_ICLR2 = 0x00;
 248
 249                 /* Disable upper 32 interrupts */
 250                 *IXP4XX_ICMR2 = 0x00;
 251         }
 252
 253         /* Default to all level triggered */
 254         for(i = 0; i < NR_IRQS; i++) {
 255                 irq_set_chip_and_handler(i, &ixp4xx_irq_chip,
 256                                          handle_level_irq);
 257                 set_irq_flags(i, IRQF_VALID);
 258         }
 259 }
 260
 261
 262 /*************************************************************************
 263  * IXP4xx timer tick
 264  * We use OS timer1 on the CPU for the timer tick and the timestamp
 265  * counter as a source of real clock ticks to account for missed jiffies.
 266  *************************************************************************/
 267
 268 static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
 269 {
 270         struct clock_event_device *evt = dev_id;
 271
 272         /* Clear Pending Interrupt by writing '1' to it */
 273         *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
 274
 275         evt->event_handler(evt);
 276
 277         return IRQ_HANDLED;
 278 }
 279
 280 static struct irqaction ixp4xx_timer_irq = {
 281         .name           = "timer1",
 282         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 283         .handler        = ixp4xx_timer_interrupt,
 284         .dev_id         = &clockevent_ixp4xx,
 285 };
 286
 287 void __init ixp4xx_timer_init(void)
 288 {
 289         /* Reset/disable counter */
 290         *IXP4XX_OSRT1 = 0;
 291
 292         /* Clear Pending Interrupt by writing '1' to it */
 293         *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
 294
 295         /* Reset time-stamp counter */
 296         *IXP4XX_OSTS = 0;
 297
 298         /* Connect the interrupt handler and enable the interrupt */
 299         setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
 300
 301         ixp4xx_clocksource_init();
 302         ixp4xx_clockevent_init();
 303 }
 304
 305 struct sys_timer ixp4xx_timer = {
 306         .init           = ixp4xx_timer_init,
 307 };
 308
 309 static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
 310
 311 void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
 312 {
 313         memcpy(&ixp4xx_udc_info, info, sizeof *info);
 314 }
 315
 316 static struct resource ixp4xx_udc_resources[] = {
 317         [0] = {
 318                 .start  = 0xc800b000,
 319                 .end    = 0xc800bfff,
 320                 .flags  = IORESOURCE_MEM,
 321         },
 322         [1] = {
 323                 .start  = IRQ_IXP4XX_USB,
 324                 .end    = IRQ_IXP4XX_USB,
 325                 .flags  = IORESOURCE_IRQ,
 326         },
 327 };
 328
 329 /*
 330  * USB device controller. The IXP4xx uses the same controller as PXA25X,
 331  * so we just use the same device.
 332  */
 333 static struct platform_device ixp4xx_udc_device = {
 334         .name           = "pxa25x-udc",
 335         .id             = -1,
 336         .num_resources  = 2,
 337         .resource       = ixp4xx_udc_resources,
 338         .dev            = {
 339                 .platform_data = &ixp4xx_udc_info,
 340         },
 341 };
 342
 343 static struct platform_device *ixp4xx_devices[] __initdata = {
 344         &ixp4xx_udc_device,
 345 };
 346
 347 static struct resource ixp46x_i2c_resources[] = {
 348         [0] = {
 349                 .start  = 0xc8011000,
 350                 .end    = 0xc801101c,
 351                 .flags  = IORESOURCE_MEM,
 352         },
 353         [1] = {
 354                 .start  = IRQ_IXP4XX_I2C,
 355                 .end    = IRQ_IXP4XX_I2C,
 356                 .flags  = IORESOURCE_IRQ
 357         }
 358 };
 359
 360 /*
 361  * I2C controller. The IXP46x uses the same block as the IOP3xx, so
 362  * we just use the same device name.
 363  */
 364 static struct platform_device ixp46x_i2c_controller = {
 365         .name           = "IOP3xx-I2C",
 366         .id             = 0,
 367         .num_resources  = 2,
 368         .resource       = ixp46x_i2c_resources
 369 };
 370
 371 static struct platform_device *ixp46x_devices[] __initdata = {
 372         &ixp46x_i2c_controller
 373 };
 374
 375 unsigned long ixp4xx_exp_bus_size;
 376 EXPORT_SYMBOL(ixp4xx_exp_bus_size);
 377
 378 void __init ixp4xx_sys_init(void)
 379 {
 380         ixp4xx_exp_bus_size = SZ_16M;
 381
 382         platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
 383
 384         if (cpu_is_ixp46x()) {
 385                 int region;
 386
 387                 platform_add_devices(ixp46x_devices,
 388                                 ARRAY_SIZE(ixp46x_devices));
 389
 390                 for (region = 0; region < 7; region++) {
 391                         if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
 392                                 ixp4xx_exp_bus_size = SZ_32M;
 393                                 break;
 394                         }
 395                 }
 396         }
 397
 398         printk("IXP4xx: Using %luMiB expansion bus window size\n",
 399                         ixp4xx_exp_bus_size >> 20);
 400 }
 401
 402 /*
 403  * sched_clock()
 404  */
 405 static u32 notrace ixp4xx_read_sched_clock(void)
 406 {
 407         return *IXP4XX_OSTS;
 408 }
 409
 410 /*
 411  * clocksource
 412  */
 413
 414 static cycle_t ixp4xx_clocksource_read(struct clocksource *c)
 415 {
 416         return *IXP4XX_OSTS;
 417 }
 418
 419 unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
 420 EXPORT_SYMBOL(ixp4xx_timer_freq);
 421 static void __init ixp4xx_clocksource_init(void)
 422 {
 423         setup_sched_clock(ixp4xx_read_sched_clock, 32, ixp4xx_timer_freq);
 424
 425         clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32,
 426                         ixp4xx_clocksource_read);
 427 }
 428
 429 /*
 430  * clockevents
 431  */
 432 static int ixp4xx_set_next_event(unsigned long evt,
 433                                  struct clock_event_device *unused)
 434 {
 435         unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
 436
 437         *IXP4XX_OSRT1 = (evt & ~IXP4XX_OST_RELOAD_MASK) | opts;
 438
 439         return 0;
 440 }
 441
 442 static void ixp4xx_set_mode(enum clock_event_mode mode,
 443                             struct clock_event_device *evt)
 444 {
 445         unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
 446         unsigned long osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK;
 447
 448         switch (mode) {
 449         case CLOCK_EVT_MODE_PERIODIC:
 450                 osrt = LATCH & ~IXP4XX_OST_RELOAD_MASK;
 451                 opts = IXP4XX_OST_ENABLE;
 452                 break;
 453         case CLOCK_EVT_MODE_ONESHOT:
 454                 /* period set by 'set next_event' */
 455                 osrt = 0;
 456                 opts = IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT;
 457                 break;
 458         case CLOCK_EVT_MODE_SHUTDOWN:
 459                 opts &= ~IXP4XX_OST_ENABLE;
 460                 break;
 461         case CLOCK_EVT_MODE_RESUME:
 462                 opts |= IXP4XX_OST_ENABLE;
 463                 break;
 464         case CLOCK_EVT_MODE_UNUSED:
 465         default:
 466                 osrt = opts = 0;
 467                 break;
 468         }
 469
 470         *IXP4XX_OSRT1 = osrt | opts;
 471 }
 472
 473 static struct clock_event_device clockevent_ixp4xx = {
 474         .name           = "ixp4xx timer1",
 475         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 476         .rating         = 200,
 477         .shift          = 24,
 478         .set_mode       = ixp4xx_set_mode,
 479         .set_next_event = ixp4xx_set_next_event,
 480 };
 481
 482 static void __init ixp4xx_clockevent_init(void)
 483 {
 484         clockevent_ixp4xx.mult = div_sc(IXP4XX_TIMER_FREQ, NSEC_PER_SEC,
 485                                         clockevent_ixp4xx.shift);
 486         clockevent_ixp4xx.max_delta_ns =
 487                 clockevent_delta2ns(0xfffffffe, &clockevent_ixp4xx);
 488         clockevent_ixp4xx.min_delta_ns =
 489                 clockevent_delta2ns(0xf, &clockevent_ixp4xx);
 490         clockevent_ixp4xx.cpumask = cpumask_of(0);
 491
 492         clockevents_register_device(&clockevent_ixp4xx);
 493 }
 494
 495 void ixp4xx_restart(char mode, const char *cmd)
 496 {
 497         if ( 1 && mode == 's') {
 498                 /* Jump into ROM at address 0 */
 499                 soft_restart(0);
 500         } else {
 501                 /* Use on-chip reset capability */
 502
 503                 /* set the "key" register to enable access to
 504                  * "timer" and "enable" registers
 505                  */
 506                 *IXP4XX_OSWK = IXP4XX_WDT_KEY;
 507
 508                 /* write 0 to the timer register for an immediate reset */
 509                 *IXP4XX_OSWT = 0;
 510
 511                 *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
 512         }
 513 }