arch/arm/mach-omap2/cpuidle34xx.c

   1 /*
   2  * linux/arch/arm/mach-omap2/cpuidle34xx.c
   3  *
   4  * OMAP3 CPU IDLE Routines
   5  *
   6  * Copyright (C) 2008 Texas Instruments, Inc.
   7  * Rajendra Nayak <rnayak@ti.com>
   8  *
   9  * Copyright (C) 2007 Texas Instruments, Inc.
  10  * Karthik Dasu <karthik-dp@ti.com>
  11  *
  12  * Copyright (C) 2006 Nokia Corporation
  13  * Tony Lindgren <tony@atomide.com>
  14  *
  15  * Copyright (C) 2005 Texas Instruments, Inc.
  16  * Richard Woodruff <r-woodruff2@ti.com>
  17  *
  18  * Based on pm.c for omap2
  19  *
  20  * This program is free software; you can redistribute it and/or modify
  21  * it under the terms of the GNU General Public License version 2 as
  22  * published by the Free Software Foundation.
  23  */
  24
  25 #include <linux/sched.h>
  26 #include <linux/cpuidle.h>
  27 #include <linux/export.h>
  28 #include <linux/cpu_pm.h>
  29
  30 #include <plat/prcm.h>
  31 #include <plat/irqs.h>
  32 #include "powerdomain.h"
  33 #include "clockdomain.h"
  34
  35 #include "pm.h"
  36 #include "control.h"
  37 #include "common.h"
  38
  39 #ifdef CONFIG_CPU_IDLE
  40
  41 /*
  42  * The latencies/thresholds for various C states have
  43  * to be configured from the respective board files.
  44  * These are some default values (which might not provide
  45  * the best power savings) used on boards which do not
  46  * pass these details from the board file.
  47  */
  48 static struct cpuidle_params cpuidle_params_table[] = {
  49         /* C1 */
  50         {2 + 2, 5, 1},
  51         /* C2 */
  52         {10 + 10, 30, 1},
  53         /* C3 */
  54         {50 + 50, 300, 1},
  55         /* C4 */
  56         {1500 + 1800, 4000, 1},
  57         /* C5 */
  58         {2500 + 7500, 12000, 1},
  59         /* C6 */
  60         {3000 + 8500, 15000, 1},
  61         /* C7 */
  62         {10000 + 30000, 300000, 1},
  63 };
  64 #define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
  65
  66 /* Mach specific information to be recorded in the C-state driver_data */
  67 struct omap3_idle_statedata {
  68         u32 mpu_state;
  69         u32 core_state;
  70         u8 valid;
  71 };
  72 struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];
  73
  74 struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
  75
  76 static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
  77                                 struct clockdomain *clkdm)
  78 {
  79         clkdm_allow_idle(clkdm);
  80         return 0;
  81 }
  82
  83 static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
  84                                 struct clockdomain *clkdm)
  85 {
  86         clkdm_deny_idle(clkdm);
  87         return 0;
  88 }
  89
  90 /**
  91  * omap3_enter_idle - Programs OMAP3 to enter the specified state
  92  * @dev: cpuidle device
  93  * @drv: cpuidle driver
  94  * @index: the index of state to be entered
  95  *
  96  * Called from the CPUidle framework to program the device to the
  97  * specified target state selected by the governor.
  98  */
  99 static int omap3_enter_idle(struct cpuidle_device *dev,
 100                                 struct cpuidle_driver *drv,
 101                                 int index)
 102 {
 103         struct omap3_idle_statedata *cx =
 104                         cpuidle_get_statedata(&dev->states_usage[index]);
 105         struct timespec ts_preidle, ts_postidle, ts_idle;
 106         u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
 107         int idle_time;
 108
 109         /* Used to keep track of the total time in idle */
 110         getnstimeofday(&ts_preidle);
 111
 112         local_irq_disable();
 113         local_fiq_disable();
 114
 115         pwrdm_set_next_pwrst(mpu_pd, mpu_state);
 116         pwrdm_set_next_pwrst(core_pd, core_state);
 117
 118         if (omap_irq_pending() || need_resched())
 119                 goto return_sleep_time;
 120
 121         /* Deny idle for C1 */
 122         if (index == 0) {
 123                 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
 124                 pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
 125         }
 126
 127         /*
 128          * Call idle CPU PM enter notifier chain so that
 129          * VFP context is saved.
 130          */
 131         if (mpu_state == PWRDM_POWER_OFF)
 132                 cpu_pm_enter();
 133
 134         /* Execute ARM wfi */
 135         omap_sram_idle();
 136
 137         /*
 138          * Call idle CPU PM enter notifier chain to restore
 139          * VFP context.
 140          */
 141         if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
 142                 cpu_pm_exit();
 143
 144         /* Re-allow idle for C1 */
 145         if (index == 0) {
 146                 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
 147                 pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
 148         }
 149
 150 return_sleep_time:
 151         getnstimeofday(&ts_postidle);
 152         ts_idle = timespec_sub(ts_postidle, ts_preidle);
 153
 154         local_irq_enable();
 155         local_fiq_enable();
 156
 157         idle_time = ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * \
 158                                                                 USEC_PER_SEC;
 159
 160         /* Update cpuidle counters */
 161         dev->last_residency = idle_time;
 162
 163         return index;
 164 }
 165
 166 /**
 167  * next_valid_state - Find next valid C-state
 168  * @dev: cpuidle device
 169  * @drv: cpuidle driver
 170  * @index: Index of currently selected c-state
 171  *
 172  * If the state corresponding to index is valid, index is returned back
 173  * to the caller. Else, this function searches for a lower c-state which is
 174  * still valid (as defined in omap3_power_states[]) and returns its index.
 175  *
 176  * A state is valid if the 'valid' field is enabled and
 177  * if it satisfies the enable_off_mode condition.
 178  */
 179 static int next_valid_state(struct cpuidle_device *dev,
 180                         struct cpuidle_driver *drv,
 181                                 int index)
 182 {
 183         struct cpuidle_state_usage *curr_usage = &dev->states_usage[index];
 184         struct cpuidle_state *curr = &drv->states[index];
 185         struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr_usage);
 186         u32 mpu_deepest_state = PWRDM_POWER_RET;
 187         u32 core_deepest_state = PWRDM_POWER_RET;
 188         int next_index = -1;
 189
 190         if (enable_off_mode) {
 191                 mpu_deepest_state = PWRDM_POWER_OFF;
 192                 /*
 193                  * Erratum i583: valable for ES rev < Es1.2 on 3630.
 194                  * CORE OFF mode is not supported in a stable form, restrict
 195                  * instead the CORE state to RET.
 196                  */
 197                 if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
 198                         core_deepest_state = PWRDM_POWER_OFF;
 199         }
 200
 201         /* Check if current state is valid */
 202         if ((cx->valid) &&
 203             (cx->mpu_state >= mpu_deepest_state) &&
 204             (cx->core_state >= core_deepest_state)) {
 205                 return index;
 206         } else {
 207                 int idx = OMAP3_NUM_STATES - 1;
 208
 209                 /* Reach the current state starting at highest C-state */
 210                 for (; idx >= 0; idx--) {
 211                         if (&drv->states[idx] == curr) {
 212                                 next_index = idx;
 213                                 break;
 214                         }
 215                 }
 216
 217                 /* Should never hit this condition */
 218                 WARN_ON(next_index == -1);
 219
 220                 /*
 221                  * Drop to next valid state.
 222                  * Start search from the next (lower) state.
 223                  */
 224                 idx--;
 225                 for (; idx >= 0; idx--) {
 226                         cx = cpuidle_get_statedata(&dev->states_usage[idx]);
 227                         if ((cx->valid) &&
 228                             (cx->mpu_state >= mpu_deepest_state) &&
 229                             (cx->core_state >= core_deepest_state)) {
 230                                 next_index = idx;
 231                                 break;
 232                         }
 233                 }
 234                 /*
 235                  * C1 is always valid.
 236                  * So, no need to check for 'next_index == -1' outside
 237                  * this loop.
 238                  */
 239         }
 240
 241         return next_index;
 242 }
 243
 244 /**
 245  * omap3_enter_idle_bm - Checks for any bus activity
 246  * @dev: cpuidle device
 247  * @drv: cpuidle driver
 248  * @index: array index of target state to be programmed
 249  *
 250  * This function checks for any pending activity and then programs
 251  * the device to the specified or a safer state.
 252  */
 253 static int omap3_enter_idle_bm(struct cpuidle_device *dev,
 254                                 struct cpuidle_driver *drv,
 255                                int index)
 256 {
 257         int new_state_idx;
 258         u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
 259         struct omap3_idle_statedata *cx;
 260         int ret;
 261
 262         /*
 263          * Prevent idle completely if CAM is active.
 264          * CAM does not have wakeup capability in OMAP3.
 265          */
 266         cam_state = pwrdm_read_pwrst(cam_pd);
 267         if (cam_state == PWRDM_POWER_ON) {
 268                 new_state_idx = drv->safe_state_index;
 269                 goto select_state;
 270         }
 271
 272         /*
 273          * FIXME: we currently manage device-specific idle states
 274          *        for PER and CORE in combination with CPU-specific
 275          *        idle states.  This is wrong, and device-specific
 276          *        idle management needs to be separated out into
 277          *        its own code.
 278          */
 279
 280         /*
 281          * Prevent PER off if CORE is not in retention or off as this
 282          * would disable PER wakeups completely.
 283          */
 284         cx = cpuidle_get_statedata(&dev->states_usage[index]);
 285         core_next_state = cx->core_state;
 286         per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
 287         if ((per_next_state == PWRDM_POWER_OFF) &&
 288             (core_next_state > PWRDM_POWER_RET))
 289                 per_next_state = PWRDM_POWER_RET;
 290
 291         /* Are we changing PER target state? */
 292         if (per_next_state != per_saved_state)
 293                 pwrdm_set_next_pwrst(per_pd, per_next_state);
 294
 295         new_state_idx = next_valid_state(dev, drv, index);
 296
 297 select_state:
 298         ret = omap3_enter_idle(dev, drv, new_state_idx);
 299
 300         /* Restore original PER state if it was modified */
 301         if (per_next_state != per_saved_state)
 302                 pwrdm_set_next_pwrst(per_pd, per_saved_state);
 303
 304         return ret;
 305 }
 306
 307 DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
 308
 309 void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
 310 {
 311         int i;
 312
 313         if (!cpuidle_board_params)
 314                 return;
 315
 316         for (i = 0; i < OMAP3_NUM_STATES; i++) {
 317                 cpuidle_params_table[i].valid = cpuidle_board_params[i].valid;
 318                 cpuidle_params_table[i].exit_latency =
 319                         cpuidle_board_params[i].exit_latency;
 320                 cpuidle_params_table[i].target_residency =
 321                         cpuidle_board_params[i].target_residency;
 322         }
 323         return;
 324 }
 325
 326 struct cpuidle_driver omap3_idle_driver = {
 327         .name =         "omap3_idle",
 328         .owner =        THIS_MODULE,
 329 };
 330
 331 /* Helper to fill the C-state common data*/
 332 static inline void _fill_cstate(struct cpuidle_driver *drv,
 333                                         int idx, const char *descr)
 334 {
 335         struct cpuidle_state *state = &drv->states[idx];
 336
 337         state->exit_latency     = cpuidle_params_table[idx].exit_latency;
 338         state->target_residency = cpuidle_params_table[idx].target_residency;
 339         state->flags            = CPUIDLE_FLAG_TIME_VALID;
 340         state->enter            = omap3_enter_idle_bm;
 341         sprintf(state->name, "C%d", idx + 1);
 342         strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
 343
 344 }
 345
 346 /* Helper to register the driver_data */
 347 static inline struct omap3_idle_statedata *_fill_cstate_usage(
 348                                         struct cpuidle_device *dev,
 349                                         int idx)
 350 {
 351         struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
 352         struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
 353
 354         cx->valid               = cpuidle_params_table[idx].valid;
 355         cpuidle_set_statedata(state_usage, cx);
 356
 357         return cx;
 358 }
 359
 360 /**
 361  * omap3_idle_init - Init routine for OMAP3 idle
 362  *
 363  * Registers the OMAP3 specific cpuidle driver to the cpuidle
 364  * framework with the valid set of states.
 365  */
 366 int __init omap3_idle_init(void)
 367 {
 368         struct cpuidle_device *dev;
 369         struct cpuidle_driver *drv = &omap3_idle_driver;
 370         struct omap3_idle_statedata *cx;
 371
 372         mpu_pd = pwrdm_lookup("mpu_pwrdm");
 373         core_pd = pwrdm_lookup("core_pwrdm");
 374         per_pd = pwrdm_lookup("per_pwrdm");
 375         cam_pd = pwrdm_lookup("cam_pwrdm");
 376
 377
 378         drv->safe_state_index = -1;
 379         dev = &per_cpu(omap3_idle_dev, smp_processor_id());
 380
 381         /* C1 . MPU WFI + Core active */
 382         _fill_cstate(drv, 0, "MPU ON + CORE ON");
 383         (&drv->states[0])->enter = omap3_enter_idle;
 384         drv->safe_state_index = 0;
 385         cx = _fill_cstate_usage(dev, 0);
 386         cx->valid = 1;  /* C1 is always valid */
 387         cx->mpu_state = PWRDM_POWER_ON;
 388         cx->core_state = PWRDM_POWER_ON;
 389
 390         /* C2 . MPU WFI + Core inactive */
 391         _fill_cstate(drv, 1, "MPU ON + CORE ON");
 392         cx = _fill_cstate_usage(dev, 1);
 393         cx->mpu_state = PWRDM_POWER_ON;
 394         cx->core_state = PWRDM_POWER_ON;
 395
 396         /* C3 . MPU CSWR + Core inactive */
 397         _fill_cstate(drv, 2, "MPU RET + CORE ON");
 398         cx = _fill_cstate_usage(dev, 2);
 399         cx->mpu_state = PWRDM_POWER_RET;
 400         cx->core_state = PWRDM_POWER_ON;
 401
 402         /* C4 . MPU OFF + Core inactive */
 403         _fill_cstate(drv, 3, "MPU OFF + CORE ON");
 404         cx = _fill_cstate_usage(dev, 3);
 405         cx->mpu_state = PWRDM_POWER_OFF;
 406         cx->core_state = PWRDM_POWER_ON;
 407
 408         /* C5 . MPU RET + Core RET */
 409         _fill_cstate(drv, 4, "MPU RET + CORE RET");
 410         cx = _fill_cstate_usage(dev, 4);
 411         cx->mpu_state = PWRDM_POWER_RET;
 412         cx->core_state = PWRDM_POWER_RET;
 413
 414         /* C6 . MPU OFF + Core RET */
 415         _fill_cstate(drv, 5, "MPU OFF + CORE RET");
 416         cx = _fill_cstate_usage(dev, 5);
 417         cx->mpu_state = PWRDM_POWER_OFF;
 418         cx->core_state = PWRDM_POWER_RET;
 419
 420         /* C7 . MPU OFF + Core OFF */
 421         _fill_cstate(drv, 6, "MPU OFF + CORE OFF");
 422         cx = _fill_cstate_usage(dev, 6);
 423         /*
 424          * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
 425          * enable OFF mode in a stable form for previous revisions.
 426          * We disable C7 state as a result.
 427          */
 428         if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
 429                 cx->valid = 0;
 430                 pr_warn("%s: core off state C7 disabled due to i583\n",
 431                         __func__);
 432         }
 433         cx->mpu_state = PWRDM_POWER_OFF;
 434         cx->core_state = PWRDM_POWER_OFF;
 435
 436         drv->state_count = OMAP3_NUM_STATES;
 437         cpuidle_register_driver(&omap3_idle_driver);
 438
 439         dev->state_count = OMAP3_NUM_STATES;
 440         if (cpuidle_register_device(dev)) {
 441                 printk(KERN_ERR "%s: CPUidle register device failed\n",
 442                        __func__);
 443                 return -EIO;
 444         }
 445
 446         return 0;
 447 }
 448 #else
 449 int __init omap3_idle_init(void)
 450 {
 451         return 0;
 452 }
 453 #endif /* CONFIG_CPU_IDLE */