Merge tag 'v3.3.7' into 3.3/master
[zen-stable.git] / arch / arm / mach-pxa / include / mach / hx4700.h
blob8bc02913517cd14a6e96f05295ff94f9fd250ee3
1 /*
2 * GPIO and IRQ definitions for HP iPAQ hx4700
4 * Copyright (c) 2008 Philipp Zabel
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
12 #ifndef _HX4700_H_
13 #define _HX4700_H_
15 #include <linux/gpio.h>
16 #include <linux/mfd/asic3.h>
18 #define HX4700_ASIC3_GPIO_BASE PXA_NR_BUILTIN_GPIO
19 #define HX4700_EGPIO_BASE (HX4700_ASIC3_GPIO_BASE + ASIC3_NUM_GPIOS)
20 #define HX4700_NR_IRQS (IRQ_BOARD_START + 70)
23 * PXA GPIOs
26 #define GPIO0_HX4700_nKEY_POWER 0
27 #define GPIO12_HX4700_ASIC3_IRQ 12
28 #define GPIO13_HX4700_W3220_IRQ 13
29 #define GPIO14_HX4700_nWLAN_IRQ 14
30 #define GPIO18_HX4700_RDY 18
31 #define GPIO22_HX4700_LCD_RL 22
32 #define GPIO27_HX4700_CODEC_ON 27
33 #define GPIO32_HX4700_RS232_ON 32
34 #define GPIO52_HX4700_CPU_nBATT_FAULT 52
35 #define GPIO58_HX4700_TSC2046_nPENIRQ 58
36 #define GPIO59_HX4700_LCD_PC1 59
37 #define GPIO60_HX4700_CF_RNB 60
38 #define GPIO61_HX4700_W3220_nRESET 61
39 #define GPIO62_HX4700_LCD_nRESET 62
40 #define GPIO63_HX4700_CPU_SS_nRESET 63
41 #define GPIO65_HX4700_TSC2046_PEN_PU 65
42 #define GPIO66_HX4700_ASIC3_nSDIO_IRQ 66
43 #define GPIO67_HX4700_EUART_PS 67
44 #define GPIO70_HX4700_LCD_SLIN1 70
45 #define GPIO71_HX4700_ASIC3_nRESET 71
46 #define GPIO72_HX4700_BQ24022_nCHARGE_EN 72
47 #define GPIO73_HX4700_LCD_UD_1 73
48 #define GPIO75_HX4700_EARPHONE_nDET 75
49 #define GPIO76_HX4700_USBC_PUEN 76
50 #define GPIO81_HX4700_CPU_GP_nRESET 81
51 #define GPIO82_HX4700_EUART_RESET 82
52 #define GPIO83_HX4700_WLAN_nRESET 83
53 #define GPIO84_HX4700_LCD_SQN 84
54 #define GPIO85_HX4700_nPCE1 85
55 #define GPIO88_HX4700_TSC2046_CS 88
56 #define GPIO91_HX4700_FLASH_VPEN 91
57 #define GPIO92_HX4700_HP_DRIVER 92
58 #define GPIO93_HX4700_EUART_INT 93
59 #define GPIO94_HX4700_KEY_MAIL 94
60 #define GPIO95_HX4700_BATT_OFF 95
61 #define GPIO96_HX4700_BQ24022_ISET2 96
62 #define GPIO97_HX4700_nBL_DETECT 97
63 #define GPIO99_HX4700_KEY_CONTACTS 99
64 #define GPIO100_HX4700_AUTO_SENSE 100 /* BL auto brightness */
65 #define GPIO102_HX4700_SYNAPTICS_POWER_ON 102
66 #define GPIO103_HX4700_SYNAPTICS_INT 103
67 #define GPIO105_HX4700_nIR_ON 105
68 #define GPIO106_HX4700_CPU_BT_nRESET 106
69 #define GPIO107_HX4700_SPK_nSD 107
70 #define GPIO109_HX4700_CODEC_nPDN 109
71 #define GPIO110_HX4700_LCD_LVDD_3V3_ON 110
72 #define GPIO111_HX4700_LCD_AVDD_3V3_ON 111
73 #define GPIO112_HX4700_LCD_N2V7_7V3_ON 112
74 #define GPIO114_HX4700_CF_RESET 114
75 #define GPIO116_HX4700_CPU_HW_nRESET 116
78 * ASIC3 GPIOs
81 #define GPIOC_BASE (HX4700_ASIC3_GPIO_BASE + 32)
82 #define GPIOD_BASE (HX4700_ASIC3_GPIO_BASE + 48)
84 #define GPIOC0_LED_RED (GPIOC_BASE + 0)
85 #define GPIOC1_LED_GREEN (GPIOC_BASE + 1)
86 #define GPIOC2_LED_BLUE (GPIOC_BASE + 2)
87 #define GPIOC3_nSD_CS (GPIOC_BASE + 3)
88 #define GPIOC4_CF_nCD (GPIOC_BASE + 4) /* Input */
89 #define GPIOC5_nCIOW (GPIOC_BASE + 5) /* Output, to CF */
90 #define GPIOC6_nCIOR (GPIOC_BASE + 6) /* Output, to CF */
91 #define GPIOC7_nPCE1 (GPIOC_BASE + 7) /* Input, from CPU */
92 #define GPIOC8_nPCE2 (GPIOC_BASE + 8) /* Input, from CPU */
93 #define GPIOC9_nPOE (GPIOC_BASE + 9) /* Input, from CPU */
94 #define GPIOC10_CF_nPWE (GPIOC_BASE + 10) /* Input */
95 #define GPIOC11_PSKTSEL (GPIOC_BASE + 11) /* Input, from CPU */
96 #define GPIOC12_nPREG (GPIOC_BASE + 12) /* Input, from CPU */
97 #define GPIOC13_nPWAIT (GPIOC_BASE + 13) /* Output, to CPU */
98 #define GPIOC14_nPIOIS16 (GPIOC_BASE + 14) /* Output, to CPU */
99 #define GPIOC15_nPIOR (GPIOC_BASE + 15) /* Input, from CPU */
101 #define GPIOD0_CPU_SS_INT (GPIOD_BASE + 0) /* Input */
102 #define GPIOD1_nKEY_CALENDAR (GPIOD_BASE + 1)
103 #define GPIOD2_BLUETOOTH_WAKEUP (GPIOD_BASE + 2)
104 #define GPIOD3_nKEY_HOME (GPIOD_BASE + 3)
105 #define GPIOD4_CF_nCD (GPIOD_BASE + 4) /* Input, from CF */
106 #define GPIOD5_nPIO (GPIOD_BASE + 5) /* Input */
107 #define GPIOD6_nKEY_RECORD (GPIOD_BASE + 6)
108 #define GPIOD7_nSDIO_DETECT (GPIOD_BASE + 7)
109 #define GPIOD8_COM_DCD (GPIOD_BASE + 8) /* Input */
110 #define GPIOD9_nAC_IN (GPIOD_BASE + 9)
111 #define GPIOD10_nSDIO_IRQ (GPIOD_BASE + 10) /* Input */
112 #define GPIOD11_nCIOIS16 (GPIOD_BASE + 11) /* Input, from CF */
113 #define GPIOD12_nCWAIT (GPIOD_BASE + 12) /* Input, from CF */
114 #define GPIOD13_CF_RNB (GPIOD_BASE + 13) /* Input */
115 #define GPIOD14_nUSBC_DETECT (GPIOD_BASE + 14)
116 #define GPIOD15_nPIOW (GPIOD_BASE + 15) /* Input, from CPU */
119 * EGPIOs
122 #define EGPIO0_VCC_3V3_EN (HX4700_EGPIO_BASE + 0) /* WLAN support chip */
123 #define EGPIO1_WL_VREG_EN (HX4700_EGPIO_BASE + 1) /* WLAN power */
124 #define EGPIO2_VCC_2V1_WL_EN (HX4700_EGPIO_BASE + 2) /* unused */
125 #define EGPIO3_SS_PWR_ON (HX4700_EGPIO_BASE + 3) /* smart slot power */
126 #define EGPIO4_CF_3V3_ON (HX4700_EGPIO_BASE + 4) /* CF 3.3V enable */
127 #define EGPIO5_BT_3V3_ON (HX4700_EGPIO_BASE + 5) /* BT 3.3V enable */
128 #define EGPIO6_WL1V8_EN (HX4700_EGPIO_BASE + 6) /* WLAN 1.8V enable */
129 #define EGPIO7_VCC_3V3_WL_EN (HX4700_EGPIO_BASE + 7) /* WLAN 3.3V enable */
130 #define EGPIO8_USB_3V3_ON (HX4700_EGPIO_BASE + 8) /* unused */
132 #endif /* _HX4700_H_ */