arch/arm/mach-pxa/time.c

   1 /*
   2  * arch/arm/mach-pxa/time.c
   3  *
   4  * PXA clocksource, clockevents, and OST interrupt handlers.
   5  * Copyright (c) 2007 by Bill Gatliff <bgat@billgatliff.com>.
   6  *
   7  * Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001
   8  * by MontaVista Software, Inc.  (Nico, your code rocks!)
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/clockchips.h>
  19
  20 #include <asm/div64.h>
  21 #include <asm/mach/irq.h>
  22 #include <asm/mach/time.h>
  23 #include <asm/sched_clock.h>
  24 #include <mach/regs-ost.h>
  25
  26 /*
  27  * This is PXA's sched_clock implementation. This has a resolution
  28  * of at least 308 ns and a maximum value of 208 days.
  29  *
  30  * The return value is guaranteed to be monotonic in that range as
  31  * long as there is always less than 582 seconds between successive
  32  * calls to sched_clock() which should always be the case in practice.
  33  */
  34
  35 static u32 notrace pxa_read_sched_clock(void)
  36 {
  37         return OSCR;
  38 }
  39
  40
  41 #define MIN_OSCR_DELTA 16
  42
  43 static irqreturn_t
  44 pxa_ost0_interrupt(int irq, void *dev_id)
  45 {
  46         struct clock_event_device *c = dev_id;
  47
  48         /* Disarm the compare/match, signal the event. */
  49         OIER &= ~OIER_E0;
  50         OSSR = OSSR_M0;
  51         c->event_handler(c);
  52
  53         return IRQ_HANDLED;
  54 }
  55
  56 static int
  57 pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
  58 {
  59         unsigned long next, oscr;
  60
  61         OIER |= OIER_E0;
  62         next = OSCR + delta;
  63         OSMR0 = next;
  64         oscr = OSCR;
  65
  66         return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
  67 }
  68
  69 static void
  70 pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
  71 {
  72         switch (mode) {
  73         case CLOCK_EVT_MODE_ONESHOT:
  74                 OIER &= ~OIER_E0;
  75                 OSSR = OSSR_M0;
  76                 break;
  77
  78         case CLOCK_EVT_MODE_UNUSED:
  79         case CLOCK_EVT_MODE_SHUTDOWN:
  80                 /* initializing, released, or preparing for suspend */
  81                 OIER &= ~OIER_E0;
  82                 OSSR = OSSR_M0;
  83                 break;
  84
  85         case CLOCK_EVT_MODE_RESUME:
  86         case CLOCK_EVT_MODE_PERIODIC:
  87                 break;
  88         }
  89 }
  90
  91 static struct clock_event_device ckevt_pxa_osmr0 = {
  92         .name           = "osmr0",
  93         .features       = CLOCK_EVT_FEAT_ONESHOT,
  94         .rating         = 200,
  95         .set_next_event = pxa_osmr0_set_next_event,
  96         .set_mode       = pxa_osmr0_set_mode,
  97 };
  98
  99 static struct irqaction pxa_ost0_irq = {
 100         .name           = "ost0",
 101         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 102         .handler        = pxa_ost0_interrupt,
 103         .dev_id         = &ckevt_pxa_osmr0,
 104 };
 105
 106 static void __init pxa_timer_init(void)
 107 {
 108         unsigned long clock_tick_rate = get_clock_tick_rate();
 109
 110         OIER = 0;
 111         OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
 112
 113         setup_sched_clock(pxa_read_sched_clock, 32, clock_tick_rate);
 114
 115         clockevents_calc_mult_shift(&ckevt_pxa_osmr0, clock_tick_rate, 4);
 116         ckevt_pxa_osmr0.max_delta_ns =
 117                 clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
 118         ckevt_pxa_osmr0.min_delta_ns =
 119                 clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1;
 120         ckevt_pxa_osmr0.cpumask = cpumask_of(0);
 121
 122         setup_irq(IRQ_OST0, &pxa_ost0_irq);
 123
 124         clocksource_mmio_init(&OSCR, "oscr0", clock_tick_rate, 200, 32,
 125                 clocksource_mmio_readl_up);
 126         clockevents_register_device(&ckevt_pxa_osmr0);
 127 }
 128
 129 #ifdef CONFIG_PM
 130 static unsigned long osmr[4], oier, oscr;
 131
 132 static void pxa_timer_suspend(void)
 133 {
 134         osmr[0] = OSMR0;
 135         osmr[1] = OSMR1;
 136         osmr[2] = OSMR2;
 137         osmr[3] = OSMR3;
 138         oier = OIER;
 139         oscr = OSCR;
 140 }
 141
 142 static void pxa_timer_resume(void)
 143 {
 144         /*
 145          * Ensure that we have at least MIN_OSCR_DELTA between match
 146          * register 0 and the OSCR, to guarantee that we will receive
 147          * the one-shot timer interrupt.  We adjust OSMR0 in preference
 148          * to OSCR to guarantee that OSCR is monotonically incrementing.
 149          */
 150         if (osmr[0] - oscr < MIN_OSCR_DELTA)
 151                 osmr[0] += MIN_OSCR_DELTA;
 152
 153         OSMR0 = osmr[0];
 154         OSMR1 = osmr[1];
 155         OSMR2 = osmr[2];
 156         OSMR3 = osmr[3];
 157         OIER = oier;
 158         OSCR = oscr;
 159 }
 160 #else
 161 #define pxa_timer_suspend NULL
 162 #define pxa_timer_resume NULL
 163 #endif
 164
 165 struct sys_timer pxa_timer = {
 166         .init           = pxa_timer_init,
 167         .suspend        = pxa_timer_suspend,
 168         .resume         = pxa_timer_resume,
 169 };