arch/arm/mach-s3c64xx/include/mach/regs-srom.h

   1 /* arch/arm/plat-s3c64xx/include/plat/regs-srom.h
   2  *
   3  * Copyright 2009 Andy Green <andy@warmcat.com>
   4  *
   5  * S3C64XX SROM definitions
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #ifndef __PLAT_REGS_SROM_H
  13 #define __PLAT_REGS_SROM_H __FILE__
  14
  15 #define S3C64XX_SROMREG(x)      (S3C_VA_MEM + (x))
  16
  17 #define S3C64XX_SROM_BW         S3C64XX_SROMREG(0)
  18 #define S3C64XX_SROM_BC0        S3C64XX_SROMREG(4)
  19 #define S3C64XX_SROM_BC1        S3C64XX_SROMREG(8)
  20 #define S3C64XX_SROM_BC2        S3C64XX_SROMREG(0xc)
  21 #define S3C64XX_SROM_BC3        S3C64XX_SROMREG(0x10)
  22 #define S3C64XX_SROM_BC4        S3C64XX_SROMREG(0x14)
  23 #define S3C64XX_SROM_BC5        S3C64XX_SROMREG(0x18)
  24
  25 /*
  26  * one register BW holds 5 x 4-bit packed settings for NCS0 - NCS4
  27  */
  28
  29 #define S3C64XX_SROM_BW__DATAWIDTH__SHIFT       0
  30 #define S3C64XX_SROM_BW__WAITENABLE__SHIFT      2
  31 #define S3C64XX_SROM_BW__BYTEENABLE__SHIFT      3
  32 #define S3C64XX_SROM_BW__CS_MASK 0xf
  33
  34 #define S3C64XX_SROM_BW__NCS0__SHIFT    0
  35 #define S3C64XX_SROM_BW__NCS1__SHIFT    4
  36 #define S3C64XX_SROM_BW__NCS2__SHIFT    8
  37 #define S3C64XX_SROM_BW__NCS3__SHIFT    0xc
  38 #define S3C64XX_SROM_BW__NCS4__SHIFT    0x10
  39
  40 /*
  41  * applies to same to BCS0 - BCS4
  42  */
  43
  44 #define S3C64XX_SROM_BCX__PMC__SHIFT    0
  45 #define S3C64XX_SROM_BCX__PMC__MASK     3
  46 #define S3C64XX_SROM_BCX__TACP__SHIFT   4
  47 #define S3C64XX_SROM_BCX__TACP__MASK    0xf
  48 #define S3C64XX_SROM_BCX__TCAH__SHIFT   8
  49 #define S3C64XX_SROM_BCX__TCAH__MASK    0xf
  50 #define S3C64XX_SROM_BCX__TCOH__SHIFT   12
  51 #define S3C64XX_SROM_BCX__TCOH__MASK    0xf
  52 #define S3C64XX_SROM_BCX__TACC__SHIFT   16
  53 #define S3C64XX_SROM_BCX__TACC__MASK    0x1f
  54 #define S3C64XX_SROM_BCX__TCOS__SHIFT   24
  55 #define S3C64XX_SROM_BCX__TCOS__MASK    0xf
  56 #define S3C64XX_SROM_BCX__TACS__SHIFT   28
  57 #define S3C64XX_SROM_BCX__TACS__MASK    0xf
  58
  59 #endif /* _PLAT_REGS_SROM_H */