arch/arm/mach-shmobile/intc-sh7377.c

   1 /*
   2  * sh7377 processor support - INTC hardware block
   3  *
   4  * Copyright (C) 2010  Magnus Damm
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  18  */
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/irq.h>
  23 #include <linux/io.h>
  24 #include <linux/sh_intc.h>
  25 #include <mach/intc.h>
  26 #include <asm/mach-types.h>
  27 #include <asm/mach/arch.h>
  28
  29 enum {
  30         UNUSED_INTCA = 0,
  31         ENABLED,
  32         DISABLED,
  33
  34         /* interrupt sources INTCA */
  35         DIRC,
  36         _2DG,
  37         CRYPT_STD,
  38         IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
  39         AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX,
  40         MFI_MFIM, MFI_MFIS,
  41         BBIF1, BBIF2,
  42         USBDMAC_USHDMI,
  43         USBHS_USHI0, USBHS_USHI1,
  44         _3DG_SGX540,
  45         CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3,
  46         KEYSC_KEY,
  47         SCIFA0, SCIFA1, SCIFA2, SCIFA3,
  48         MSIOF2, MSIOF1,
  49         SCIFA4, SCIFA5, SCIFB,
  50         FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
  51         SDHI0,
  52         SDHI1,
  53         MSU_MSU, MSU_MSU2,
  54         IRREM,
  55         MSUG,
  56         IRDA,
  57         TPU0, TPU1, TPU2, TPU3, TPU4,
  58         LCRC,
  59         PINTCA_PINT1, PINTCA_PINT2,
  60         TTI20,
  61         MISTY,
  62         DDM,
  63         RWDT0, RWDT1,
  64         DMAC_1_DEI0, DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3,
  65         DMAC_2_DEI4, DMAC_2_DEI5, DMAC_2_DADERR,
  66         DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
  67         DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
  68         DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
  69         DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
  70         SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
  71         ICUSB_ICUSB0, ICUSB_ICUSB1,
  72         ICUDMC_ICUDMC1, ICUDMC_ICUDMC2,
  73         SPU2_SPU0, SPU2_SPU1,
  74         FSI,
  75         FMSI,
  76         SCUV,
  77         IPMMU_IPMMUB,
  78         AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, AP_ARM_DMAIRQ, AP_ARM_DMASIRQ,
  79         MFIS2,
  80         CPORTR2S,
  81         CMT14, CMT15,
  82         SCIFA6,
  83
  84         /* interrupt groups INTCA */
  85         DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT,
  86         AP_ARM1, AP_ARM2, USBHS, SPU2, FLCTL, IIC1,
  87         ICUSB, ICUDMC
  88 };
  89
  90 static struct intc_vect intca_vectors[] __initdata = {
  91         INTC_VECT(DIRC, 0x0560),
  92         INTC_VECT(_2DG, 0x05e0),
  93         INTC_VECT(CRYPT_STD, 0x0700),
  94         INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0),
  95         INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0),
  96         INTC_VECT(AP_ARM_IRQPMU, 0x0800), INTC_VECT(AP_ARM_COMMTX, 0x0840),
  97         INTC_VECT(AP_ARM_COMMRX, 0x0860),
  98         INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920),
  99         INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960),
 100         INTC_VECT(USBDMAC_USHDMI, 0x0a00),
 101         INTC_VECT(USBHS_USHI0, 0x0a20), INTC_VECT(USBHS_USHI1, 0x0a40),
 102         INTC_VECT(_3DG_SGX540, 0x0a60),
 103         INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20),
 104         INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60),
 105         INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0),
 106         INTC_VECT(KEYSC_KEY, 0x0be0),
 107         INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20),
 108         INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
 109         INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00),
 110         INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40),
 111         INTC_VECT(SCIFB, 0x0d60),
 112         INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
 113         INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
 114         INTC_VECT(SDHI0, 0x0e00), INTC_VECT(SDHI0, 0x0e20),
 115         INTC_VECT(SDHI0, 0x0e40), INTC_VECT(SDHI0, 0x0e60),
 116         INTC_VECT(SDHI1, 0x0e80), INTC_VECT(SDHI1, 0x0ea0),
 117         INTC_VECT(SDHI1, 0x0ec0), INTC_VECT(SDHI1, 0x0ee0),
 118         INTC_VECT(MSU_MSU, 0x0f20), INTC_VECT(MSU_MSU2, 0x0f40),
 119         INTC_VECT(IRREM, 0x0f60),
 120         INTC_VECT(MSUG, 0x0fa0),
 121         INTC_VECT(IRDA, 0x0480),
 122         INTC_VECT(TPU0, 0x04a0), INTC_VECT(TPU1, 0x04c0),
 123         INTC_VECT(TPU2, 0x04e0), INTC_VECT(TPU3, 0x0500),
 124         INTC_VECT(TPU4, 0x0520),
 125         INTC_VECT(LCRC, 0x0540),
 126         INTC_VECT(PINTCA_PINT1, 0x1000), INTC_VECT(PINTCA_PINT2, 0x1020),
 127         INTC_VECT(TTI20, 0x1100),
 128         INTC_VECT(MISTY, 0x1120),
 129         INTC_VECT(DDM, 0x1140),
 130         INTC_VECT(RWDT0, 0x1280), INTC_VECT(RWDT1, 0x12a0),
 131         INTC_VECT(DMAC_1_DEI0, 0x2000), INTC_VECT(DMAC_1_DEI1, 0x2020),
 132         INTC_VECT(DMAC_1_DEI2, 0x2040), INTC_VECT(DMAC_1_DEI3, 0x2060),
 133         INTC_VECT(DMAC_2_DEI4, 0x2080), INTC_VECT(DMAC_2_DEI5, 0x20a0),
 134         INTC_VECT(DMAC_2_DADERR, 0x20c0),
 135         INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120),
 136         INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160),
 137         INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0),
 138         INTC_VECT(DMAC2_2_DADERR, 0x21c0),
 139         INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220),
 140         INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260),
 141         INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0),
 142         INTC_VECT(DMAC3_2_DADERR, 0x22c0),
 143         INTC_VECT(SHWYSTAT_RT, 0x1300), INTC_VECT(SHWYSTAT_HS, 0x1d20),
 144         INTC_VECT(SHWYSTAT_COM, 0x1340),
 145         INTC_VECT(ICUSB_ICUSB0, 0x1700), INTC_VECT(ICUSB_ICUSB1, 0x1720),
 146         INTC_VECT(ICUDMC_ICUDMC1, 0x1780), INTC_VECT(ICUDMC_ICUDMC2, 0x17a0),
 147         INTC_VECT(SPU2_SPU0, 0x1800), INTC_VECT(SPU2_SPU1, 0x1820),
 148         INTC_VECT(FSI, 0x1840),
 149         INTC_VECT(FMSI, 0x1860),
 150         INTC_VECT(SCUV, 0x1880),
 151         INTC_VECT(IPMMU_IPMMUB, 0x1900),
 152         INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
 153         INTC_VECT(AP_ARM_DMAEXTERRIRQ, 0x19a0),
 154         INTC_VECT(AP_ARM_DMAIRQ, 0x19c0),
 155         INTC_VECT(AP_ARM_DMASIRQ, 0x19e0),
 156         INTC_VECT(MFIS2, 0x1a00),
 157         INTC_VECT(CPORTR2S, 0x1a20),
 158         INTC_VECT(CMT14, 0x1a40), INTC_VECT(CMT15, 0x1a60),
 159         INTC_VECT(SCIFA6, 0x1a80),
 160 };
 161
 162 static struct intc_group intca_groups[] __initdata = {
 163         INTC_GROUP(DMAC_1, DMAC_1_DEI0,
 164                    DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3),
 165         INTC_GROUP(DMAC_2, DMAC_2_DEI4,
 166                    DMAC_2_DEI5, DMAC_2_DADERR),
 167         INTC_GROUP(DMAC2_1, DMAC2_1_DEI0,
 168                    DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
 169         INTC_GROUP(DMAC2_2, DMAC2_2_DEI4,
 170                    DMAC2_2_DEI5, DMAC2_2_DADERR),
 171         INTC_GROUP(DMAC3_1, DMAC3_1_DEI0,
 172                    DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
 173         INTC_GROUP(DMAC3_2, DMAC3_2_DEI4,
 174                    DMAC3_2_DEI5, DMAC3_2_DADERR),
 175         INTC_GROUP(AP_ARM1, AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMTX),
 176         INTC_GROUP(USBHS, USBHS_USHI0, USBHS_USHI1),
 177         INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1),
 178         INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
 179                    FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
 180         INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
 181         INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
 182         INTC_GROUP(ICUSB, ICUSB_ICUSB0, ICUSB_ICUSB1),
 183         INTC_GROUP(ICUDMC, ICUDMC_ICUDMC1, ICUDMC_ICUDMC2),
 184 };
 185
 186 static struct intc_mask_reg intca_mask_registers[] __initdata = {
 187         { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
 188           { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
 189             AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
 190         { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */
 191           { _2DG, CRYPT_STD, DIRC, 0,
 192             DMAC_1_DEI3, DMAC_1_DEI2, DMAC_1_DEI1, DMAC_1_DEI0 } },
 193         { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */
 194           { PINTCA_PINT1, PINTCA_PINT2, 0, 0,
 195             BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } },
 196         { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */
 197           { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
 198             DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
 199         { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */
 200           { DDM, 0, 0, 0,
 201             0, 0, 0, 0 } },
 202         { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */
 203           { KEYSC_KEY, DMAC_2_DADERR, DMAC_2_DEI5, DMAC_2_DEI4,
 204             SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
 205         { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */
 206           { SCIFB, SCIFA5, SCIFA4, MSIOF1,
 207             0, 0, MSIOF2, 0 } },
 208         { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
 209           { DISABLED, ENABLED, ENABLED, ENABLED,
 210             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
 211         { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
 212           { DISABLED, ENABLED, ENABLED, ENABLED,
 213             TTI20, USBDMAC_USHDMI, 0, MSUG } },
 214         { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
 215           { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
 216             CMT2, USBHS_USHI1, USBHS_USHI0, _3DG_SGX540 } },
 217         { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */
 218           { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
 219             0, 0, 0, 0 } },
 220         { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */
 221           { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1,
 222             LCRC, MSU_MSU2, IRREM, MSU_MSU } },
 223         { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */
 224           { 0, 0, TPU0, TPU1,
 225             TPU2, TPU3, TPU4, 0 } },
 226         { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
 227           { 0, 0, 0, 0,
 228             MISTY, CMT3, RWDT1, RWDT0 } },
 229         { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */
 230           { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
 231             0, 0, 0, 0 } },
 232         { 0xe6950090, 0xe69500d0, 8, /* IMR4A3 / IMCR4A3 */
 233           { ICUSB_ICUSB0, ICUSB_ICUSB1, 0, 0,
 234             ICUDMC_ICUDMC1, ICUDMC_ICUDMC2, 0, 0 } },
 235         { 0xe6950094, 0xe69500d4, 8, /* IMR5A3 / IMCR5A3 */
 236           { SPU2_SPU0, SPU2_SPU1, FSI, FMSI,
 237             SCUV, 0, 0, 0 } },
 238         { 0xe6950098, 0xe69500d8, 8, /* IMR6A3 / IMCR6A3 */
 239           { IPMMU_IPMMUB, 0, 0, 0,
 240             AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ,
 241             AP_ARM_DMAIRQ, AP_ARM_DMASIRQ } },
 242         { 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */
 243           { MFIS2, CPORTR2S, CMT14, CMT15,
 244             SCIFA6, 0, 0, 0 } },
 245 };
 246
 247 static struct intc_prio_reg intca_prio_registers[] __initdata = {
 248         { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } },
 249         { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
 250         { 0xe6940008, 0, 16, 4, /* IPRCA */ { _2DG, CRYPT_STD,
 251                                               CMT1_CMT11, AP_ARM1 } },
 252         { 0xe694000c, 0, 16, 4, /* IPRDA */ { PINTCA_PINT1, PINTCA_PINT2,
 253                                               CMT1_CMT12, TPU4 } },
 254         { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC_1, MFI_MFIS,
 255                                               MFI_MFIM, USBHS } },
 256         { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC_2,
 257                                               _3DG_SGX540, CMT1_CMT10 } },
 258         { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
 259                                               SCIFA2, SCIFA3 } },
 260         { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBDMAC_USHDMI,
 261                                               FLCTL, SDHI0 } },
 262         { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, MSU_MSU, IIC1 } },
 263         { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, MSUG, TTI20 } },
 264         { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IRREM, SDHI1 } },
 265         { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, TPU1, TPU2, TPU3 } },
 266         { 0xe6940030, 0, 16, 4, /* IPRMA */ { MISTY, CMT3, RWDT1, RWDT0 } },
 267         { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
 268         { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, 0 } },
 269         { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
 270         { 0xe6950020, 0, 16, 4, /* IPRIA3 */ { ICUSB, 0, 0, 0 } },
 271         { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { ICUDMC, 0, 0, 0 } },
 272         { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
 273         { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { SCUV, 0, 0, 0 } },
 274         { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU_IPMMUB, 0, 0, 0 } },
 275         { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
 276         { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
 277                                                CMT14, CMT15 } },
 278         { 0xe694003c, 0, 16, 4, /* IPRPA3 */ { SCIFA6, 0, 0, 0 } },
 279 };
 280
 281 static struct intc_desc intca_desc __initdata = {
 282         .name = "sh7377-intca",
 283         .force_enable = ENABLED,
 284         .force_disable = DISABLED,
 285         .hw = INTC_HW_DESC(intca_vectors, intca_groups,
 286                            intca_mask_registers, intca_prio_registers,
 287                            NULL, NULL),
 288 };
 289
 290 INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
 291                  INTC_VECT, "sh7377-intca-irq-pins");
 292
 293 /* this macro ignore entry which is also in INTCA */
 294 #define __IGNORE(a...)
 295 #define __IGNORE0(a...) 0
 296
 297 enum {
 298         UNUSED_INTCS = 0,
 299
 300         INTCS,
 301
 302         /* interrupt sources INTCS */
 303         VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3,
 304         RTDMAC1_1_DEI0, RTDMAC1_1_DEI1, RTDMAC1_1_DEI2, RTDMAC1_1_DEI3,
 305         CEU,
 306         BEU_BEU0, BEU_BEU1, BEU_BEU2,
 307         __IGNORE(MFI)
 308         __IGNORE(BBIF2)
 309         VPU,
 310         TSIF1,
 311         __IGNORE(SGX540)
 312         _2DDMAC,
 313         IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
 314         IPMMU_IPMMUR, IPMMU_IPMMUR2,
 315         RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR,
 316         __IGNORE(KEYSC)
 317         __IGNORE(TTI20)
 318         __IGNORE(MSIOF)
 319         IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
 320         TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
 321         CMT0,
 322         TSIF0,
 323         __IGNORE(CMT2)
 324         LMB,
 325         __IGNORE(MSUG)
 326         __IGNORE(MSU_MSU, MSU_MSU2)
 327         __IGNORE(CTI)
 328         MVI3,
 329         __IGNORE(RWDT0)
 330         __IGNORE(RWDT1)
 331         ICB,
 332         PEP,
 333         ASA,
 334         __IGNORE(_2DG)
 335         HQE,
 336         JPU,
 337         LCDC0,
 338         __IGNORE(LCRC)
 339         RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
 340         RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR,
 341         FRC,
 342         LCDC1,
 343         CSIRX,
 344         DSITX_DSITX0, DSITX_DSITX1,
 345         __IGNORE(SPU2_SPU0, SPU2_SPU1)
 346         __IGNORE(FSI)
 347         __IGNORE(FMSI)
 348         __IGNORE(SCUV)
 349         TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12,
 350         TSIF2,
 351         CMT4,
 352         __IGNORE(MFIS2)
 353         CPORTS2R,
 354
 355         /* interrupt groups INTCS */
 356         RTDMAC1_1, RTDMAC1_2, VEU, BEU, IIC0, __IGNORE(MSU) IPMMU,
 357         IIC2, RTDMAC2_1, RTDMAC2_2, DSITX, __IGNORE(SPU2) TMU1,
 358 };
 359
 360 #define INTCS_INTVECT 0x0F80
 361 static struct intc_vect intcs_vectors[] __initdata = {
 362         INTCS_VECT(VEU_VEU0, 0x0700), INTCS_VECT(VEU_VEU1, 0x0720),
 363         INTCS_VECT(VEU_VEU2, 0x0740), INTCS_VECT(VEU_VEU3, 0x0760),
 364         INTCS_VECT(RTDMAC1_1_DEI0, 0x0800), INTCS_VECT(RTDMAC1_1_DEI1, 0x0820),
 365         INTCS_VECT(RTDMAC1_1_DEI2, 0x0840), INTCS_VECT(RTDMAC1_1_DEI3, 0x0860),
 366         INTCS_VECT(CEU, 0x0880),
 367         INTCS_VECT(BEU_BEU0, 0x08A0),
 368         INTCS_VECT(BEU_BEU1, 0x08C0),
 369         INTCS_VECT(BEU_BEU2, 0x08E0),
 370         __IGNORE(INTCS_VECT(MFI, 0x0900))
 371         __IGNORE(INTCS_VECT(BBIF2, 0x0960))
 372         INTCS_VECT(VPU, 0x0980),
 373         INTCS_VECT(TSIF1, 0x09A0),
 374         __IGNORE(INTCS_VECT(SGX540, 0x09E0))
 375         INTCS_VECT(_2DDMAC, 0x0A00),
 376         INTCS_VECT(IIC2_ALI2, 0x0A80), INTCS_VECT(IIC2_TACKI2, 0x0AA0),
 377         INTCS_VECT(IIC2_WAITI2, 0x0AC0), INTCS_VECT(IIC2_DTEI2, 0x0AE0),
 378         INTCS_VECT(IPMMU_IPMMUR, 0x0B00), INTCS_VECT(IPMMU_IPMMUR2, 0x0B20),
 379         INTCS_VECT(RTDMAC1_2_DEI4, 0x0B80),
 380         INTCS_VECT(RTDMAC1_2_DEI5, 0x0BA0),
 381         INTCS_VECT(RTDMAC1_2_DADERR, 0x0BC0),
 382         __IGNORE(INTCS_VECT(KEYSC 0x0BE0))
 383         __IGNORE(INTCS_VECT(TTI20, 0x0C80))
 384         __IGNORE(INTCS_VECT(MSIOF, 0x0D20))
 385         INTCS_VECT(IIC0_ALI0, 0x0E00), INTCS_VECT(IIC0_TACKI0, 0x0E20),
 386         INTCS_VECT(IIC0_WAITI0, 0x0E40), INTCS_VECT(IIC0_DTEI0, 0x0E60),
 387         INTCS_VECT(TMU_TUNI0, 0x0E80),
 388         INTCS_VECT(TMU_TUNI1, 0x0EA0),
 389         INTCS_VECT(TMU_TUNI2, 0x0EC0),
 390         INTCS_VECT(CMT0, 0x0F00),
 391         INTCS_VECT(TSIF0, 0x0F20),
 392         __IGNORE(INTCS_VECT(CMT2, 0x0F40))
 393         INTCS_VECT(LMB, 0x0F60),
 394         __IGNORE(INTCS_VECT(MSUG, 0x0F80))
 395         __IGNORE(INTCS_VECT(MSU_MSU, 0x0FA0))
 396         __IGNORE(INTCS_VECT(MSU_MSU2, 0x0FC0))
 397         __IGNORE(INTCS_VECT(CTI, 0x0400))
 398         INTCS_VECT(MVI3, 0x0420),
 399         __IGNORE(INTCS_VECT(RWDT0, 0x0440))
 400         __IGNORE(INTCS_VECT(RWDT1, 0x0460))
 401         INTCS_VECT(ICB, 0x0480),
 402         INTCS_VECT(PEP, 0x04A0),
 403         INTCS_VECT(ASA, 0x04C0),
 404         __IGNORE(INTCS_VECT(_2DG, 0x04E0))
 405         INTCS_VECT(HQE, 0x0540),
 406         INTCS_VECT(JPU, 0x0560),
 407         INTCS_VECT(LCDC0, 0x0580),
 408         __IGNORE(INTCS_VECT(LCRC, 0x05A0))
 409         INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320),
 410         INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360),
 411         INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13A0),
 412         INTCS_VECT(RTDMAC2_2_DADERR, 0x13C0),
 413         INTCS_VECT(FRC, 0x1700),
 414         INTCS_VECT(LCDC1, 0x1780),
 415         INTCS_VECT(CSIRX, 0x17A0),
 416         INTCS_VECT(DSITX_DSITX0, 0x17C0), INTCS_VECT(DSITX_DSITX1, 0x17E0),
 417         __IGNORE(INTCS_VECT(SPU2_SPU0, 0x1800))
 418         __IGNORE(INTCS_VECT(SPU2_SPU1, 0x1820))
 419         __IGNORE(INTCS_VECT(FSI, 0x1840))
 420         __IGNORE(INTCS_VECT(FMSI, 0x1860))
 421         __IGNORE(INTCS_VECT(SCUV, 0x1880))
 422         INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920),
 423         INTCS_VECT(TMU1_TUNI12, 0x1940),
 424         INTCS_VECT(TSIF2, 0x1960),
 425         INTCS_VECT(CMT4, 0x1980),
 426         __IGNORE(INTCS_VECT(MFIS2, 0x1A00))
 427         INTCS_VECT(CPORTS2R, 0x1A20),
 428
 429         INTC_VECT(INTCS, INTCS_INTVECT),
 430 };
 431
 432 static struct intc_group intcs_groups[] __initdata = {
 433         INTC_GROUP(RTDMAC1_1,
 434                    RTDMAC1_1_DEI0, RTDMAC1_1_DEI1,
 435                    RTDMAC1_1_DEI2, RTDMAC1_1_DEI3),
 436         INTC_GROUP(RTDMAC1_2,
 437                    RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR),
 438         INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3),
 439         INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2),
 440         INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
 441         __IGNORE(INTC_GROUP(MSU, MSU_MSU, MSU_MSU2))
 442         INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2),
 443         INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
 444         INTC_GROUP(RTDMAC2_1,
 445                    RTDMAC2_1_DEI0, RTDMAC2_1_DEI1,
 446                    RTDMAC2_1_DEI2, RTDMAC2_1_DEI3),
 447         INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR),
 448         INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1),
 449         __IGNORE(INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1))
 450         INTC_GROUP(TMU1, TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12),
 451 };
 452
 453 static struct intc_mask_reg intcs_mask_registers[] __initdata = {
 454         { 0xE6940184, 0xE69401C4, 8, /* IMR1AS / IMCR1AS  */
 455           { BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU,
 456             VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } },
 457         { 0xE6940188, 0xE69401C8, 8, /* IMR2AS / IMCR2AS */
 458           { 0, 0, 0, VPU,
 459             __IGNORE0(BBIF2), 0, 0, __IGNORE0(MFI) } },
 460         { 0xE694018C, 0xE69401CC, 8, /* IMR3AS / IMCR3AS */
 461           { 0, 0, 0, _2DDMAC,
 462             __IGNORE0(_2DG), ASA, PEP, ICB } },
 463         { 0xE6940190, 0xE69401D0, 8, /* IMR4AS / IMCR4AS */
 464           { 0, 0, MVI3, __IGNORE0(CTI),
 465             JPU, HQE, __IGNORE0(LCRC), LCDC0 } },
 466         { 0xE6940194, 0xE69401D4, 8, /* IMR5AS / IMCR5AS */
 467           { __IGNORE0(KEYSC), RTDMAC1_2_DADERR, RTDMAC1_2_DEI5, RTDMAC1_2_DEI4,
 468             RTDMAC1_1_DEI3, RTDMAC1_1_DEI2, RTDMAC1_1_DEI1, RTDMAC1_1_DEI0 } },
 469         __IGNORE({ 0xE6940198, 0xE69401D8, 8, /* IMR6AS / IMCR6AS */
 470           { 0, 0, MSIOF, 0,
 471             SGX540, 0, TTI20, 0 } })
 472         { 0xE694019C, 0xE69401DC, 8, /* IMR7AS / IMCR7AS */
 473           { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
 474             0, 0, 0, 0 } },
 475         __IGNORE({ 0xE69401A0, 0xE69401E0, 8, /* IMR8AS / IMCR8AS */
 476           { 0, 0, 0, 0,
 477             0, MSU_MSU, MSU_MSU2, MSUG } })
 478         { 0xE69401A4, 0xE69401E4, 8, /* IMR9AS / IMCR9AS */
 479           { __IGNORE0(RWDT1), __IGNORE0(RWDT0), __IGNORE0(CMT2), CMT0,
 480             IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
 481         { 0xE69401A8, 0xE69401E8, 8, /* IMR10AS / IMCR10AS */
 482           { 0, 0, IPMMU_IPMMUR, IPMMU_IPMMUR2,
 483             0, 0, 0, 0 } },
 484         { 0xE69401AC, 0xE69401EC, 8, /* IMR11AS / IMCR11AS */
 485           { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
 486             0, TSIF1, LMB, TSIF0 } },
 487         { 0xE6950180, 0xE69501C0, 8, /* IMR0AS3 / IMCR0AS3 */
 488           { RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
 489             RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR, 0 } },
 490         { 0xE6950190, 0xE69501D0, 8, /* IMR4AS3 / IMCR4AS3 */
 491           { FRC, 0, 0, 0,
 492             LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } },
 493         __IGNORE({ 0xE6950194, 0xE69501D4, 8, /* IMR5AS3 / IMCR5AS3 */
 494           {SPU2_SPU0, SPU2_SPU1, FSI, FMSI,
 495            SCUV, 0, 0, 0 } })
 496         { 0xE6950198, 0xE69501D8, 8, /* IMR6AS3 / IMCR6AS3 */
 497           { TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, TSIF2,
 498             CMT4, 0, 0, 0 } },
 499         { 0xE695019C, 0xE69501DC, 8, /* IMR7AS3 / IMCR7AS3 */
 500           { __IGNORE0(MFIS2), CPORTS2R, 0, 0,
 501             0, 0, 0, 0 } },
 502         { 0xFFD20104, 0, 16, /* INTAMASK */
 503           { 0, 0, 0, 0, 0, 0, 0, 0,
 504             0, 0, 0, 0, 0, 0, 0, INTCS } }
 505 };
 506
 507 static struct intc_prio_reg intcs_prio_registers[] __initdata = {
 508         /* IPRAS */
 509         { 0xFFD20000, 0, 16, 4, { __IGNORE0(CTI), MVI3, _2DDMAC, ICB } },
 510         /* IPRBS */
 511         { 0xFFD20004, 0, 16, 4, { JPU, LCDC0, 0, __IGNORE0(LCRC) } },
 512         /* IPRCS */
 513         __IGNORE({ 0xFFD20008, 0, 16, 4, { BBIF2, 0, 0, 0 } })
 514         /* IPRES */
 515         { 0xFFD20010, 0, 16, 4, { RTDMAC1_1, CEU, __IGNORE0(MFI), VPU } },
 516         /* IPRFS */
 517         { 0xFFD20014, 0, 16, 4,
 518           { __IGNORE0(KEYSC), RTDMAC1_2, __IGNORE0(CMT2), CMT0 } },
 519         /* IPRGS */
 520         { 0xFFD20018, 0, 16, 4, { TMU_TUNI0, TMU_TUNI1, TMU_TUNI2, TSIF1 } },
 521         /* IPRHS */
 522         { 0xFFD2001C, 0, 16, 4, { __IGNORE0(TTI20), 0, VEU, BEU } },
 523         /* IPRIS */
 524         { 0xFFD20020, 0, 16, 4, { 0, __IGNORE0(MSIOF), TSIF0, IIC0 } },
 525         /* IPRJS */
 526         __IGNORE({ 0xFFD20024, 0, 16, 4, { 0, SGX540, MSUG, MSU } })
 527         /* IPRKS */
 528         { 0xFFD20028, 0, 16, 4, { __IGNORE0(_2DG), ASA, LMB, PEP } },
 529         /* IPRLS */
 530         { 0xFFD2002C, 0, 16, 4, { IPMMU, 0, 0, HQE } },
 531         /* IPRMS */
 532         { 0xFFD20030, 0, 16, 4,
 533           { IIC2, 0, __IGNORE0(RWDT1), __IGNORE0(RWDT0) } },
 534         /* IPRAS3 */
 535         { 0xFFD50000, 0, 16, 4, { RTDMAC2_1, 0, 0, 0 } },
 536         /* IPRBS3 */
 537         { 0xFFD50004, 0, 16, 4, { RTDMAC2_2, 0, 0, 0 } },
 538         /* IPRIS3 */
 539         { 0xFFD50020, 0, 16, 4, { FRC, 0, 0, 0 } },
 540         /* IPRJS3 */
 541         { 0xFFD50024, 0, 16, 4, { LCDC1, CSIRX, DSITX, 0 } },
 542         /* IPRKS3 */
 543         __IGNORE({ 0xFFD50028, 0, 16, 4, { SPU2, 0, FSI, FMSI } })
 544         /* IPRLS3 */
 545         __IGNORE({ 0xFFD5002C, 0, 16, 4, { SCUV, 0, 0, 0 } })
 546         /* IPRMS3 */
 547         { 0xFFD50030, 0, 16, 4, { TMU1, 0, 0, TSIF2 } },
 548         /* IPRNS3 */
 549         { 0xFFD50034, 0, 16, 4, { CMT4, 0, 0, 0 } },
 550         /* IPROS3 */
 551         { 0xFFD50038, 0, 16, 4, { __IGNORE0(MFIS2), CPORTS2R, 0, 0 } },
 552 };
 553
 554 static struct resource intcs_resources[] __initdata = {
 555         [0] = {
 556                 .start  = 0xffd20000,
 557                 .end    = 0xffd500ff,
 558                 .flags  = IORESOURCE_MEM,
 559         }
 560 };
 561
 562 static struct intc_desc intcs_desc __initdata = {
 563         .name = "sh7377-intcs",
 564         .resource = intcs_resources,
 565         .num_resources = ARRAY_SIZE(intcs_resources),
 566         .hw = INTC_HW_DESC(intcs_vectors, intcs_groups,
 567                            intcs_mask_registers, intcs_prio_registers,
 568                            NULL, NULL),
 569 };
 570
 571 static void intcs_demux(unsigned int irq, struct irq_desc *desc)
 572 {
 573         void __iomem *reg = (void *)irq_get_handler_data(irq);
 574         unsigned int evtcodeas = ioread32(reg);
 575
 576         generic_handle_irq(intcs_evt2irq(evtcodeas));
 577 }
 578
 579 #define INTEVTSA 0xFFD20100
 580 void __init sh7377_init_irq(void)
 581 {
 582         void __iomem *intevtsa = ioremap_nocache(INTEVTSA, PAGE_SIZE);
 583
 584         register_intc_controller(&intca_desc);
 585         register_intc_controller(&intca_irq_pins_desc);
 586         register_intc_controller(&intcs_desc);
 587
 588         /* demux using INTEVTSA */
 589         irq_set_handler_data(evt2irq(INTCS_INTVECT), (void *)intevtsa);
 590         irq_set_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux);
 591 }