arch/arm/mach-shmobile/intc-sh73a0.c

   1 /*
   2  * sh73a0 processor support - INTC hardware block
   3  *
   4  * Copyright (C) 2010  Magnus Damm
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  18  */
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/module.h>
  23 #include <linux/irq.h>
  24 #include <linux/io.h>
  25 #include <linux/sh_intc.h>
  26 #include <mach/intc.h>
  27 #include <mach/sh73a0.h>
  28 #include <asm/hardware/gic.h>
  29 #include <asm/mach-types.h>
  30 #include <asm/mach/arch.h>
  31
  32 enum {
  33         UNUSED = 0,
  34
  35         /* interrupt sources INTCS */
  36         PINTCS_PINT1, PINTCS_PINT2,
  37         RTDMAC_0_DEI0, RTDMAC_0_DEI1, RTDMAC_0_DEI2, RTDMAC_0_DEI3,
  38         CEU, MFI, BBIF2, VPU, TSIF1, _3DG_SGX543, _2DDMAC_2DDM0,
  39         RTDMAC_1_DEI4, RTDMAC_1_DEI5, RTDMAC_1_DADERR,
  40         KEYSC_KEY, VINT, MSIOF,
  41         TMU0_TUNI00, TMU0_TUNI01, TMU0_TUNI02,
  42         CMT0, TSIF0, CMT2, LMB, MSUG, MSU_MSU, MSU_MSU2,
  43         CTI, RWDT0, ICB, PEP, ASA, JPU_JPEG, LCDC, LCRC,
  44         RTDMAC_2_DEI6, RTDMAC_2_DEI7, RTDMAC_2_DEI8, RTDMAC_2_DEI9,
  45         RTDMAC_3_DEI10, RTDMAC_3_DEI11,
  46         FRC, GCU, LCDC1, CSIRX,
  47         DSITX0_DSITX00, DSITX0_DSITX01,
  48         SPU2_SPU0, SPU2_SPU1, FSI,
  49         TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12,
  50         TSIF2, CMT4, MFIS2, CPORTS2R, TSG, DMASCH1, SCUW,
  51         VIO60, VIO61, CEU21, CSI21, DSITX1_DSITX10, DSITX1_DSITX11,
  52         DISP, DSRV, EMUX2_EMUX20I, EMUX2_EMUX21I,
  53         MSTIF0_MST00I, MSTIF0_MST01I, MSTIF1_MST10I, MSTIF1_MST11I,
  54         SPUV,
  55
  56         /* interrupt groups INTCS */
  57         RTDMAC_0, RTDMAC_1, RTDMAC_2, RTDMAC_3,
  58         DSITX0, SPU2, TMU1, MSU,
  59 };
  60
  61 static struct intc_vect intcs_vectors[] = {
  62         INTCS_VECT(PINTCS_PINT1, 0x0600), INTCS_VECT(PINTCS_PINT2, 0x0620),
  63         INTCS_VECT(RTDMAC_0_DEI0, 0x0800), INTCS_VECT(RTDMAC_0_DEI1, 0x0820),
  64         INTCS_VECT(RTDMAC_0_DEI2, 0x0840), INTCS_VECT(RTDMAC_0_DEI3, 0x0860),
  65         INTCS_VECT(CEU, 0x0880), INTCS_VECT(MFI, 0x0900),
  66         INTCS_VECT(BBIF2, 0x0960), INTCS_VECT(VPU, 0x0980),
  67         INTCS_VECT(TSIF1, 0x09a0), INTCS_VECT(_3DG_SGX543, 0x09e0),
  68         INTCS_VECT(_2DDMAC_2DDM0, 0x0a00),
  69         INTCS_VECT(RTDMAC_1_DEI4, 0x0b80), INTCS_VECT(RTDMAC_1_DEI5, 0x0ba0),
  70         INTCS_VECT(RTDMAC_1_DADERR, 0x0bc0),
  71         INTCS_VECT(KEYSC_KEY, 0x0be0), INTCS_VECT(VINT, 0x0c80),
  72         INTCS_VECT(MSIOF, 0x0d20),
  73         INTCS_VECT(TMU0_TUNI00, 0x0e80), INTCS_VECT(TMU0_TUNI01, 0x0ea0),
  74         INTCS_VECT(TMU0_TUNI02, 0x0ec0),
  75         INTCS_VECT(CMT0, 0x0f00), INTCS_VECT(TSIF0, 0x0f20),
  76         INTCS_VECT(CMT2, 0x0f40), INTCS_VECT(LMB, 0x0f60),
  77         INTCS_VECT(MSUG, 0x0f80),
  78         INTCS_VECT(MSU_MSU, 0x0fa0), INTCS_VECT(MSU_MSU2, 0x0fc0),
  79         INTCS_VECT(CTI, 0x0400), INTCS_VECT(RWDT0, 0x0440),
  80         INTCS_VECT(ICB, 0x0480), INTCS_VECT(PEP, 0x04a0),
  81         INTCS_VECT(ASA, 0x04c0), INTCS_VECT(JPU_JPEG, 0x0560),
  82         INTCS_VECT(LCDC, 0x0580), INTCS_VECT(LCRC, 0x05a0),
  83         INTCS_VECT(RTDMAC_2_DEI6, 0x1300), INTCS_VECT(RTDMAC_2_DEI7, 0x1320),
  84         INTCS_VECT(RTDMAC_2_DEI8, 0x1340), INTCS_VECT(RTDMAC_2_DEI9, 0x1360),
  85         INTCS_VECT(RTDMAC_3_DEI10, 0x1380), INTCS_VECT(RTDMAC_3_DEI11, 0x13a0),
  86         INTCS_VECT(FRC, 0x1700), INTCS_VECT(GCU, 0x1760),
  87         INTCS_VECT(LCDC1, 0x1780), INTCS_VECT(CSIRX, 0x17a0),
  88         INTCS_VECT(DSITX0_DSITX00, 0x17c0), INTCS_VECT(DSITX0_DSITX01, 0x17e0),
  89         INTCS_VECT(SPU2_SPU0, 0x1800), INTCS_VECT(SPU2_SPU1, 0x1820),
  90         INTCS_VECT(FSI, 0x1840),
  91         INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920),
  92         INTCS_VECT(TMU1_TUNI12, 0x1940),
  93         INTCS_VECT(TSIF2, 0x1960), INTCS_VECT(CMT4, 0x1980),
  94         INTCS_VECT(MFIS2, 0x1a00), INTCS_VECT(CPORTS2R, 0x1a20),
  95         INTCS_VECT(TSG, 0x1ae0), INTCS_VECT(DMASCH1, 0x1b00),
  96         INTCS_VECT(SCUW, 0x1b40),
  97         INTCS_VECT(VIO60, 0x1b60), INTCS_VECT(VIO61, 0x1b80),
  98         INTCS_VECT(CEU21, 0x1ba0), INTCS_VECT(CSI21, 0x1be0),
  99         INTCS_VECT(DSITX1_DSITX10, 0x1c00), INTCS_VECT(DSITX1_DSITX11, 0x1c20),
 100         INTCS_VECT(DISP, 0x1c40), INTCS_VECT(DSRV, 0x1c60),
 101         INTCS_VECT(EMUX2_EMUX20I, 0x1c80), INTCS_VECT(EMUX2_EMUX21I, 0x1ca0),
 102         INTCS_VECT(MSTIF0_MST00I, 0x1cc0), INTCS_VECT(MSTIF0_MST01I, 0x1ce0),
 103         INTCS_VECT(MSTIF1_MST10I, 0x1d00), INTCS_VECT(MSTIF1_MST11I, 0x1d20),
 104         INTCS_VECT(SPUV, 0x2300),
 105 };
 106
 107 static struct intc_group intcs_groups[] __initdata = {
 108         INTC_GROUP(RTDMAC_0, RTDMAC_0_DEI0, RTDMAC_0_DEI1,
 109                    RTDMAC_0_DEI2, RTDMAC_0_DEI3),
 110         INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI4, RTDMAC_1_DEI5, RTDMAC_1_DADERR),
 111         INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI6, RTDMAC_2_DEI7,
 112                    RTDMAC_2_DEI8, RTDMAC_2_DEI9),
 113         INTC_GROUP(RTDMAC_3, RTDMAC_3_DEI10, RTDMAC_3_DEI11),
 114         INTC_GROUP(TMU1, TMU1_TUNI12, TMU1_TUNI11, TMU1_TUNI10),
 115         INTC_GROUP(DSITX0, DSITX0_DSITX00, DSITX0_DSITX01),
 116         INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1),
 117         INTC_GROUP(MSU, MSU_MSU, MSU_MSU2),
 118 };
 119
 120 static struct intc_mask_reg intcs_mask_registers[] = {
 121         { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
 122           { 0, 0, 0, CEU,
 123             0, 0, 0, 0 } },
 124         { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
 125           { 0, 0, 0, VPU,
 126             BBIF2, 0, 0, MFI } },
 127         { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
 128           { 0, 0, 0, _2DDMAC_2DDM0,
 129             0, ASA, PEP, ICB } },
 130         { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
 131           { 0, 0, 0, CTI,
 132             JPU_JPEG, 0, LCRC, LCDC } },
 133         { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
 134           { KEYSC_KEY, RTDMAC_1_DADERR, RTDMAC_1_DEI5, RTDMAC_1_DEI4,
 135             RTDMAC_0_DEI3, RTDMAC_0_DEI2, RTDMAC_0_DEI1, RTDMAC_0_DEI0 } },
 136         { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
 137           { 0, 0, MSIOF, 0,
 138             _3DG_SGX543, 0, 0, 0 } },
 139         { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
 140           { 0, TMU0_TUNI02, TMU0_TUNI01, TMU0_TUNI00,
 141             0, 0, 0, 0 } },
 142         { 0xffd201a0, 0xffd201e0, 8, /* IMR8SA / IMCR8SA */
 143           { 0, 0, 0, 0,
 144             0, MSU_MSU, MSU_MSU2, MSUG } },
 145         { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
 146           { 0, RWDT0, CMT2, CMT0,
 147             0, 0, 0, 0 } },
 148         { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
 149           { 0, 0, 0, 0,
 150             0, TSIF1, LMB, TSIF0 } },
 151         { 0xffd201b0, 0xffd201f0, 8, /* IMR12SA / IMCR12SA */
 152           { 0, 0, 0, 0,
 153             0, 0, PINTCS_PINT2, PINTCS_PINT1 } },
 154         { 0xffd50180, 0xffd501c0, 8, /* IMR0SA3 / IMCR0SA3 */
 155           { RTDMAC_2_DEI6, RTDMAC_2_DEI7, RTDMAC_2_DEI8, RTDMAC_2_DEI9,
 156             RTDMAC_3_DEI10, RTDMAC_3_DEI11, 0, 0 } },
 157         { 0xffd50190, 0xffd501d0, 8, /* IMR4SA3 / IMCR4SA3 */
 158           { FRC, 0, 0, GCU,
 159             LCDC1, CSIRX, DSITX0_DSITX00, DSITX0_DSITX01 } },
 160         { 0xffd50194, 0xffd501d4, 8, /* IMR5SA3 / IMCR5SA3 */
 161           { SPU2_SPU0, SPU2_SPU1, FSI, 0,
 162             0, 0, 0, 0 } },
 163         { 0xffd50198, 0xffd501d8, 8, /* IMR6SA3 / IMCR6SA3 */
 164           { TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, 0,
 165             TSIF2, CMT4, 0, 0 } },
 166         { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */
 167           { MFIS2, CPORTS2R, 0, 0,
 168             0, 0, 0, TSG } },
 169         { 0xffd501a0, 0xffd501e0, 8, /* IMR8SA3 / IMCR8SA3 */
 170           { DMASCH1, 0, SCUW, VIO60,
 171             VIO61, CEU21, 0, CSI21 } },
 172         { 0xffd501a4, 0xffd501e4, 8, /* IMR9SA3 / IMCR9SA3 */
 173           { DSITX1_DSITX10, DSITX1_DSITX11, DISP, DSRV,
 174             EMUX2_EMUX20I, EMUX2_EMUX21I, MSTIF0_MST00I, MSTIF0_MST01I } },
 175         { 0xffd501a8, 0xffd501e8, 8, /* IMR10SA3 / IMCR10SA3 */
 176           { MSTIF0_MST00I, MSTIF0_MST01I, 0, 0,
 177             0, 0, 0, 0  } },
 178         { 0xffd60180, 0xffd601c0, 8, /* IMR0SA4 / IMCR0SA4 */
 179           { SPUV, 0, 0, 0,
 180             0, 0, 0, 0  } },
 181 };
 182
 183 /* Priority is needed for INTCA to receive the INTCS interrupt */
 184 static struct intc_prio_reg intcs_prio_registers[] = {
 185         { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC_2DDM0, ICB } },
 186         { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } },
 187         { 0xffd20008, 0, 16, 4, /* IPRCS */ { BBIF2, 0, 0, 0 } },
 188         { 0xffd2000c, 0, 16, 4, /* IPRDS */ { PINTCS_PINT1, PINTCS_PINT2,
 189                                               0, 0 } },
 190         { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_0, CEU, MFI, VPU } },
 191         { 0xffd20014, 0, 16, 4, /* IPRFS */ { KEYSC_KEY, RTDMAC_1,
 192                                               CMT2, CMT0 } },
 193         { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_TUNI00, TMU0_TUNI01,
 194                                               TMU0_TUNI02, TSIF1 } },
 195         { 0xffd2001c, 0, 16, 4, /* IPRHS */ { VINT, 0, 0, 0 } },
 196         { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, 0 } },
 197         { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, _3DG_SGX543, MSUG, MSU } },
 198         { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, ASA, LMB, PEP } },
 199         { 0xffd20030, 0, 16, 4, /* IPRMS */ { 0, 0, 0, RWDT0 } },
 200         { 0xffd50000, 0, 16, 4, /* IPRAS3 */ { RTDMAC_2, 0, 0, 0 } },
 201         { 0xffd50004, 0, 16, 4, /* IPRBS3 */ { RTDMAC_3, 0, 0, 0 } },
 202         { 0xffd50020, 0, 16, 4, /* IPRIS3 */ { FRC, 0, 0, 0 } },
 203         { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, CSIRX, DSITX0, 0 } },
 204         { 0xffd50028, 0, 16, 4, /* IPRKS3 */ { SPU2, 0, FSI, 0 } },
 205         { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, TSIF2 } },
 206         { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, 0, 0, 0 } },
 207         { 0xffd50038, 0, 16, 4, /* IPROS3 */ { MFIS2, CPORTS2R, 0, 0 } },
 208         { 0xffd50040, 0, 16, 4, /* IPRQS3 */ { DMASCH1, 0, SCUW, VIO60 } },
 209         { 0xffd50044, 0, 16, 4, /* IPRRS3 */ { VIO61, CEU21, 0, CSI21 } },
 210         { 0xffd50048, 0, 16, 4, /* IPRSS3 */ { DSITX1_DSITX10, DSITX1_DSITX11,
 211                                                DISP, DSRV } },
 212         { 0xffd5004c, 0, 16, 4, /* IPRTS3 */ { EMUX2_EMUX20I, EMUX2_EMUX21I,
 213                                                MSTIF0_MST00I, MSTIF0_MST01I } },
 214         { 0xffd50050, 0, 16, 4, /* IPRUS3 */ { MSTIF1_MST10I, MSTIF1_MST11I,
 215                                                0, 0 } },
 216         { 0xffd60000, 0, 16, 4, /* IPRAS4 */ { SPUV, 0, 0, 0 } },
 217 };
 218
 219 static struct resource intcs_resources[] __initdata = {
 220         [0] = {
 221                 .start  = 0xffd20000,
 222                 .end    = 0xffd201ff,
 223                 .flags  = IORESOURCE_MEM,
 224         },
 225         [1] = {
 226                 .start  = 0xffd50000,
 227                 .end    = 0xffd501ff,
 228                 .flags  = IORESOURCE_MEM,
 229         },
 230         [2] = {
 231                 .start  = 0xffd60000,
 232                 .end    = 0xffd601ff,
 233                 .flags  = IORESOURCE_MEM,
 234         }
 235 };
 236
 237 static struct intc_desc intcs_desc __initdata = {
 238         .name = "sh73a0-intcs",
 239         .resource = intcs_resources,
 240         .num_resources = ARRAY_SIZE(intcs_resources),
 241         .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
 242                            intcs_prio_registers, NULL, NULL),
 243 };
 244
 245 static struct irqaction sh73a0_intcs_cascade;
 246
 247 static irqreturn_t sh73a0_intcs_demux(int irq, void *dev_id)
 248 {
 249         unsigned int evtcodeas = ioread32((void __iomem *)dev_id);
 250
 251         generic_handle_irq(intcs_evt2irq(evtcodeas));
 252
 253         return IRQ_HANDLED;
 254 }
 255
 256 static int sh73a0_set_wake(struct irq_data *data, unsigned int on)
 257 {
 258         return 0; /* always allow wakeup */
 259 }
 260
 261 #define RELOC_BASE 0x1000
 262
 263 /* INTCA IRQ pins at INTCS + 0x1000 to make space for GIC+INTC handling */
 264 #define INTCS_VECT_RELOC(n, vect) INTCS_VECT((n), (vect) + RELOC_BASE)
 265
 266 INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
 267                  INTCS_VECT_RELOC, "sh73a0-intca-irq-pins");
 268
 269 static int to_gic_irq(struct irq_data *data)
 270 {
 271         unsigned int vect = irq2evt(data->irq) - INTCS_VECT_BASE;
 272
 273         if (vect >= 0x3200)
 274                 vect -= 0x3000;
 275         else
 276                 vect -= 0x0200;
 277
 278         return gic_spi((vect >> 5) + 1);
 279 }
 280
 281 static int to_intca_reloc_irq(struct irq_data *data)
 282 {
 283         return data->irq + (RELOC_BASE >> 5);
 284 }
 285
 286 #define irq_cb(cb, irq) irq_get_chip(irq)->cb(irq_get_irq_data(irq))
 287 #define irq_cbp(cb, irq, p...) irq_get_chip(irq)->cb(irq_get_irq_data(irq), p)
 288
 289 static void intca_gic_enable(struct irq_data *data)
 290 {
 291         irq_cb(irq_unmask, to_intca_reloc_irq(data));
 292         irq_cb(irq_unmask, to_gic_irq(data));
 293 }
 294
 295 static void intca_gic_disable(struct irq_data *data)
 296 {
 297         irq_cb(irq_mask, to_gic_irq(data));
 298         irq_cb(irq_mask, to_intca_reloc_irq(data));
 299 }
 300
 301 static void intca_gic_mask_ack(struct irq_data *data)
 302 {
 303         irq_cb(irq_mask, to_gic_irq(data));
 304         irq_cb(irq_mask_ack, to_intca_reloc_irq(data));
 305 }
 306
 307 static void intca_gic_eoi(struct irq_data *data)
 308 {
 309         irq_cb(irq_eoi, to_gic_irq(data));
 310 }
 311
 312 static int intca_gic_set_type(struct irq_data *data, unsigned int type)
 313 {
 314         return irq_cbp(irq_set_type, to_intca_reloc_irq(data), type);
 315 }
 316
 317 static int intca_gic_set_wake(struct irq_data *data, unsigned int on)
 318 {
 319         return irq_cbp(irq_set_wake, to_intca_reloc_irq(data), on);
 320 }
 321
 322 #ifdef CONFIG_SMP
 323 static int intca_gic_set_affinity(struct irq_data *data,
 324                                   const struct cpumask *cpumask,
 325                                   bool force)
 326 {
 327         return irq_cbp(irq_set_affinity, to_gic_irq(data), cpumask, force);
 328 }
 329 #endif
 330
 331 struct irq_chip intca_gic_irq_chip = {
 332         .name                   = "INTCA-GIC",
 333         .irq_mask               = intca_gic_disable,
 334         .irq_unmask             = intca_gic_enable,
 335         .irq_mask_ack           = intca_gic_mask_ack,
 336         .irq_eoi                = intca_gic_eoi,
 337         .irq_enable             = intca_gic_enable,
 338         .irq_disable            = intca_gic_disable,
 339         .irq_shutdown           = intca_gic_disable,
 340         .irq_set_type           = intca_gic_set_type,
 341         .irq_set_wake           = intca_gic_set_wake,
 342 #ifdef CONFIG_SMP
 343         .irq_set_affinity       = intca_gic_set_affinity,
 344 #endif
 345 };
 346
 347 static int to_intc_vect(int irq)
 348 {
 349         unsigned int irq_pin = irq - gic_spi(1);
 350         unsigned int offs;
 351
 352         if (irq_pin < 16)
 353                 offs = 0x0200;
 354         else
 355                 offs = 0x3000;
 356
 357         return offs + (irq_pin << 5);
 358 }
 359
 360 static irqreturn_t sh73a0_irq_pin_demux(int irq, void *dev_id)
 361 {
 362         generic_handle_irq(intcs_evt2irq(to_intc_vect(irq)));
 363         return IRQ_HANDLED;
 364 }
 365
 366 static struct irqaction sh73a0_irq_pin_cascade[32];
 367
 368 #define PINTER0 0xe69000a0
 369 #define PINTER1 0xe69000a4
 370 #define PINTRR0 0xe69000d0
 371 #define PINTRR1 0xe69000d4
 372
 373 #define PINT0A_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq))
 374 #define PINT0B_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 8))
 375 #define PINT0C_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 16))
 376 #define PINT0D_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 24))
 377 #define PINT1E_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT1_IRQ(irq))
 378
 379 INTC_PINT(intc_pint0, PINTER0, 0xe69000b0, "sh73a0-pint0",              \
 380   INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D),       \
 381   INTC_PINT_V(A, PINT0A_IRQ), INTC_PINT_V(B, PINT0B_IRQ),               \
 382   INTC_PINT_V(C, PINT0C_IRQ), INTC_PINT_V(D, PINT0D_IRQ),               \
 383   INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D),       \
 384   INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D));
 385
 386 INTC_PINT(intc_pint1, PINTER1, 0xe69000c0, "sh73a0-pint1",              \
 387   INTC_PINT_E(E), INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, \
 388   INTC_PINT_V(E, PINT1E_IRQ), INTC_PINT_V_NONE,                         \
 389   INTC_PINT_V_NONE, INTC_PINT_V_NONE,                                   \
 390   INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E(E), \
 391   INTC_PINT_E(E), INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E_NONE);
 392
 393 static struct irqaction sh73a0_pint0_cascade;
 394 static struct irqaction sh73a0_pint1_cascade;
 395
 396 static void pint_demux(unsigned long rr, unsigned long er, int base_irq)
 397 {
 398         unsigned long value =  ioread32(rr) & ioread32(er);
 399         int k;
 400
 401         for (k = 0; k < 32; k++) {
 402                 if (value & (1 << (31 - k))) {
 403                         generic_handle_irq(base_irq + k);
 404                         iowrite32(~(1 << (31 - k)), rr);
 405                 }
 406         }
 407 }
 408
 409 static irqreturn_t sh73a0_pint0_demux(int irq, void *dev_id)
 410 {
 411         pint_demux(PINTRR0, PINTER0, SH73A0_PINT0_IRQ(0));
 412         return IRQ_HANDLED;
 413 }
 414
 415 static irqreturn_t sh73a0_pint1_demux(int irq, void *dev_id)
 416 {
 417         pint_demux(PINTRR1, PINTER1, SH73A0_PINT1_IRQ(0));
 418         return IRQ_HANDLED;
 419 }
 420
 421 void __init sh73a0_init_irq(void)
 422 {
 423         void __iomem *gic_dist_base = __io(0xf0001000);
 424         void __iomem *gic_cpu_base = __io(0xf0000100);
 425         void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
 426         int k, n;
 427
 428         gic_init(0, 29, gic_dist_base, gic_cpu_base);
 429         gic_arch_extn.irq_set_wake = sh73a0_set_wake;
 430
 431         register_intc_controller(&intcs_desc);
 432         register_intc_controller(&intca_irq_pins_desc);
 433         register_intc_controller(&intc_pint0_desc);
 434         register_intc_controller(&intc_pint1_desc);
 435
 436         /* demux using INTEVTSA */
 437         sh73a0_intcs_cascade.name = "INTCS cascade";
 438         sh73a0_intcs_cascade.handler = sh73a0_intcs_demux;
 439         sh73a0_intcs_cascade.dev_id = intevtsa;
 440         setup_irq(gic_spi(50), &sh73a0_intcs_cascade);
 441
 442         /* IRQ pins require special handling through INTCA and GIC */
 443         for (k = 0; k < 32; k++) {
 444                 sh73a0_irq_pin_cascade[k].name = "INTCA-GIC cascade";
 445                 sh73a0_irq_pin_cascade[k].handler = sh73a0_irq_pin_demux;
 446                 setup_irq(gic_spi(1 + k), &sh73a0_irq_pin_cascade[k]);
 447
 448                 n = intcs_evt2irq(to_intc_vect(gic_spi(1 + k)));
 449                 WARN_ON(irq_alloc_desc_at(n, numa_node_id()) != n);
 450                 irq_set_chip_and_handler_name(n, &intca_gic_irq_chip,
 451                                               handle_level_irq, "level");
 452                 set_irq_flags(n, IRQF_VALID); /* yuck */
 453         }
 454
 455         /* PINT pins are sanely tied to the GIC as SPI */
 456         sh73a0_pint0_cascade.name = "PINT0 cascade";
 457         sh73a0_pint0_cascade.handler = sh73a0_pint0_demux;
 458         setup_irq(gic_spi(33), &sh73a0_pint0_cascade);
 459
 460         sh73a0_pint1_cascade.name = "PINT1 cascade";
 461         sh73a0_pint1_cascade.handler = sh73a0_pint1_demux;
 462         setup_irq(gic_spi(34), &sh73a0_pint1_cascade);
 463 }