arch/arm/mach-tegra/platsmp.c

   1 /*
   2  *  linux/arch/arm/mach-tegra/platsmp.c
   3  *
   4  *  Copyright (C) 2002 ARM Ltd.
   5  *  All Rights Reserved
   6  *
   7  *  Copyright (C) 2009 Palm
   8  *  All Rights Reserved
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/errno.h>
  16 #include <linux/delay.h>
  17 #include <linux/device.h>
  18 #include <linux/jiffies.h>
  19 #include <linux/smp.h>
  20 #include <linux/io.h>
  21
  22 #include <asm/cacheflush.h>
  23 #include <asm/hardware/gic.h>
  24 #include <asm/mach-types.h>
  25 #include <asm/smp_scu.h>
  26
  27 #include <mach/iomap.h>
  28
  29 extern void tegra_secondary_startup(void);
  30
  31 static DEFINE_SPINLOCK(boot_lock);
  32 static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
  33
  34 #define EVP_CPU_RESET_VECTOR \
  35         (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
  36 #define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \
  37         (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c)
  38 #define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \
  39         (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344)
  40
  41 void __cpuinit platform_secondary_init(unsigned int cpu)
  42 {
  43         /*
  44          * if any interrupts are already enabled for the primary
  45          * core (e.g. timer irq), then they will not have been enabled
  46          * for us: do so
  47          */
  48         gic_secondary_init(0);
  49
  50         /*
  51          * Synchronise with the boot thread.
  52          */
  53         spin_lock(&boot_lock);
  54         spin_unlock(&boot_lock);
  55 }
  56
  57 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
  58 {
  59         unsigned long old_boot_vector;
  60         unsigned long boot_vector;
  61         unsigned long timeout;
  62         u32 reg;
  63
  64         /*
  65          * set synchronisation state between this boot processor
  66          * and the secondary one
  67          */
  68         spin_lock(&boot_lock);
  69
  70
  71         /* set the reset vector to point to the secondary_startup routine */
  72
  73         boot_vector = virt_to_phys(tegra_secondary_startup);
  74         old_boot_vector = readl(EVP_CPU_RESET_VECTOR);
  75         writel(boot_vector, EVP_CPU_RESET_VECTOR);
  76
  77         /* enable cpu clock on cpu1 */
  78         reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
  79         writel(reg & ~(1<<9), CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
  80
  81         reg = (1<<13) | (1<<9) | (1<<5) | (1<<1);
  82         writel(reg, CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
  83
  84         smp_wmb();
  85         flush_cache_all();
  86
  87         /* unhalt the cpu */
  88         writel(0, IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x14);
  89
  90         timeout = jiffies + (1 * HZ);
  91         while (time_before(jiffies, timeout)) {
  92                 if (readl(EVP_CPU_RESET_VECTOR) != boot_vector)
  93                         break;
  94                 udelay(10);
  95         }
  96
  97         /* put the old boot vector back */
  98         writel(old_boot_vector, EVP_CPU_RESET_VECTOR);
  99
 100         /*
 101          * now the secondary core is starting up let it run its
 102          * calibrations, then wait for it to finish
 103          */
 104         spin_unlock(&boot_lock);
 105
 106         return 0;
 107 }
 108
 109 /*
 110  * Initialise the CPU possible map early - this describes the CPUs
 111  * which may be present or become present in the system.
 112  */
 113 void __init smp_init_cpus(void)
 114 {
 115         unsigned int i, ncores = scu_get_core_count(scu_base);
 116
 117         if (ncores > nr_cpu_ids) {
 118                 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
 119                         ncores, nr_cpu_ids);
 120                 ncores = nr_cpu_ids;
 121         }
 122
 123         for (i = 0; i < ncores; i++)
 124                 set_cpu_possible(i, true);
 125
 126         set_smp_cross_call(gic_raise_softirq);
 127 }
 128
 129 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 130 {
 131
 132         scu_enable(scu_base);
 133 }