| blob | c2e2b66f72b5cd08648085c28ffc5d8c2ee8359a |
1 /*
2 * linux/arch/arm/mm/proc-v7.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This is the "shell" of the ARMv7 processor support.
11 */
12 #include <linux/init.h>
13 #include <linux/linkage.h>
14 #include <asm/assembler.h>
15 #include <asm/asm-offsets.h>
16 #include <asm/hwcap.h>
17 #include <asm/pgtable-hwdef.h>
18 #include <asm/pgtable.h>
20 #include "proc-macros.S"
22 #ifdef CONFIG_ARM_LPAE
23 #include "proc-v7-3level.S"
24 #else
25 #include "proc-v7-2level.S"
26 #endif
28 ENTRY(cpu_v7_proc_init)
29 mov pc, lr
30 ENDPROC(cpu_v7_proc_init)
32 ENTRY(cpu_v7_proc_fin)
33 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
34 bic r0, r0, #0x1000 @ ...i............
35 bic r0, r0, #0x0006 @ .............ca.
36 mcr p15, 0, r0, c1, c0, 0 @ disable caches
37 mov pc, lr
38 ENDPROC(cpu_v7_proc_fin)
40 /*
41 * cpu_v7_reset(loc)
42 *
43 * Perform a soft reset of the system. Put the CPU into the
44 * same state as it would be if it had been reset, and branch
45 * to what would be the reset vector.
46 *
47 * - loc - location to jump to for soft reset
48 *
49 * This code must be executed using a flat identity mapping with
50 * caches disabled.
51 */
52 .align 5
53 .pushsection .idmap.text, "ax"
54 ENTRY(cpu_v7_reset)
55 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
56 bic r1, r1, #0x1 @ ...............m
57 THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
58 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
59 isb
60 mov pc, r0
61 ENDPROC(cpu_v7_reset)
62 .popsection
64 /*
65 * cpu_v7_do_idle()
66 *
67 * Idle the processor (eg, wait for interrupt).
68 *
69 * IRQs are already disabled.
70 */
71 ENTRY(cpu_v7_do_idle)
72 dsb @ WFI may enter a low-power mode
73 wfi
74 mov pc, lr
75 ENDPROC(cpu_v7_do_idle)
77 ENTRY(cpu_v7_dcache_clean_area)
78 #ifndef TLB_CAN_READ_FROM_L1_CACHE
79 dcache_line_size r2, r3
80 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
81 add r0, r0, r2
82 subs r1, r1, r2
83 bhi 1b
84 dsb
85 #endif
86 mov pc, lr
87 ENDPROC(cpu_v7_dcache_clean_area)
89 string cpu_v7_name, "ARMv7 Processor"
90 .align
92 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
93 .globl cpu_v7_suspend_size
94 .equ cpu_v7_suspend_size, 4 * 8
95 #ifdef CONFIG_ARM_CPU_SUSPEND
96 ENTRY(cpu_v7_do_suspend)
97 stmfd sp!, {r4 - r10, lr}
98 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
99 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
100 stmia r0!, {r4 - r5}
101 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
102 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
103 mrc p15, 0, r11, c2, c0, 2 @ TTB control register
104 mrc p15, 0, r8, c1, c0, 0 @ Control register
105 mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
106 mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
107 stmia r0, {r6 - r11}
108 ldmfd sp!, {r4 - r10, pc}
109 ENDPROC(cpu_v7_do_suspend)
111 ENTRY(cpu_v7_do_resume)
112 mov ip, #0
113 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
114 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
115 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
116 ldmia r0!, {r4 - r5}
117 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
118 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
119 ldmia r0, {r6 - r11}
120 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
121 #ifndef CONFIG_ARM_LPAE
122 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
123 ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
124 #endif
125 mcr p15, 0, r1, c2, c0, 0 @ TTB 0
126 mcr p15, 0, r7, c2, c0, 1 @ TTB 1
127 mcr p15, 0, r11, c2, c0, 2 @ TTB control register
128 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
129 teq r4, r9 @ Is it already set?
130 mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
131 mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
132 ldr r4, =PRRR @ PRRR
133 ldr r5, =NMRR @ NMRR
134 mcr p15, 0, r4, c10, c2, 0 @ write PRRR
135 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
136 isb
137 dsb
138 mov r0, r8 @ control register
139 b cpu_resume_mmu
140 ENDPROC(cpu_v7_do_resume)
141 #endif
143 __CPUINIT
145 /*
146 * __v7_setup
147 *
148 * Initialise TLB, Caches, and MMU state ready to switch the MMU
149 * on. Return in r0 the new CP15 C1 control register setting.
150 *
151 * This should be able to cover all ARMv7 cores.
152 *
153 * It is assumed that:
154 * - cache type register is implemented
155 */
156 __v7_ca5mp_setup:
157 __v7_ca9mp_setup:
158 mov r10, #(1 << 0) @ TLB ops broadcasting
159 b 1f
160 __v7_ca7mp_setup:
161 __v7_ca15mp_setup:
162 mov r10, #0
163 1:
164 #ifdef CONFIG_SMP
165 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
166 ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
167 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
168 orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
169 orreq r0, r0, r10 @ Enable CPU-specific SMP bits
170 mcreq p15, 0, r0, c1, c0, 1
171 #endif
172 __v7_setup:
173 adr r12, __v7_setup_stack @ the local stack
174 stmia r12, {r0-r5, r7, r9, r11, lr}
175 bl v7_flush_dcache_all
176 ldmia r12, {r0-r5, r7, r9, r11, lr}
178 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
179 and r10, r0, #0xff000000 @ ARM?
180 teq r10, #0x41000000
181 bne 3f
182 and r5, r0, #0x00f00000 @ variant
183 and r6, r0, #0x0000000f @ revision
184 orr r6, r6, r5, lsr #20-4 @ combine variant and revision
185 ubfx r0, r0, #4, #12 @ primary part number
187 /* Cortex-A8 Errata */
188 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
189 teq r0, r10
190 bne 2f
191 #ifdef CONFIG_ARM_ERRATA_430973
192 teq r5, #0x00100000 @ only present in r1p*
193 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
194 orreq r10, r10, #(1 << 6) @ set IBE to 1
195 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
196 #endif
197 #ifdef CONFIG_ARM_ERRATA_458693
198 teq r6, #0x20 @ only present in r2p0
199 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
200 orreq r10, r10, #(1 << 5) @ set L1NEON to 1
201 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
202 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
203 #endif
204 #ifdef CONFIG_ARM_ERRATA_460075
205 teq r6, #0x20 @ only present in r2p0
206 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
207 tsteq r10, #1 << 22
208 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
209 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
210 #endif
211 b 3f
213 /* Cortex-A9 Errata */
214 2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
215 teq r0, r10
216 bne 3f
217 #ifdef CONFIG_ARM_ERRATA_742230
218 cmp r6, #0x22 @ only present up to r2p2
219 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
220 orrle r10, r10, #1 << 4 @ set bit #4
221 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
222 #endif
223 #ifdef CONFIG_ARM_ERRATA_742231
224 teq r6, #0x20 @ present in r2p0
225 teqne r6, #0x21 @ present in r2p1
226 teqne r6, #0x22 @ present in r2p2
227 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
228 orreq r10, r10, #1 << 12 @ set bit #12
229 orreq r10, r10, #1 << 22 @ set bit #22
230 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
231 #endif
232 #ifdef CONFIG_ARM_ERRATA_743622
233 teq r5, #0x00200000 @ only present in r2p*
234 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
235 orreq r10, r10, #1 << 6 @ set bit #6
236 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
237 #endif
238 #if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
239 ALT_SMP(cmp r6, #0x30) @ present prior to r3p0
240 ALT_UP_B(1f)
241 mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
242 orrlt r10, r10, #1 << 11 @ set bit #11
243 mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
244 1:
245 #endif
247 3: mov r10, #0
248 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
249 dsb
250 #ifdef CONFIG_MMU
251 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
252 v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup
253 ldr r5, =PRRR @ PRRR
254 ldr r6, =NMRR @ NMRR
255 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
256 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
257 #endif
258 #ifndef CONFIG_ARM_THUMBEE
259 mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
260 and r0, r0, #(0xf << 12) @ ThumbEE enabled field
261 teq r0, #(1 << 12) @ check if ThumbEE is present
262 bne 1f
263 mov r5, #0
264 mcr p14, 6, r5, c1, c0, 0 @ Initialize TEEHBR to 0
265 mrc p14, 6, r0, c0, c0, 0 @ load TEECR
266 orr r0, r0, #1 @ set the 1st bit in order to
267 mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
268 1:
269 #endif
270 adr r5, v7_crval
271 ldmia r5, {r5, r6}
272 #ifdef CONFIG_CPU_ENDIAN_BE8
273 orr r6, r6, #1 << 25 @ big-endian page tables
274 #endif
275 #ifdef CONFIG_SWP_EMULATE
276 orr r5, r5, #(1 << 10) @ set SW bit in "clear"
277 bic r6, r6, #(1 << 10) @ clear it in "mmuset"
278 #endif
279 mrc p15, 0, r0, c1, c0, 0 @ read control register
280 bic r0, r0, r5 @ clear bits them
281 orr r0, r0, r6 @ set them
282 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
283 mov pc, lr @ return to head.S:__ret
284 ENDPROC(__v7_setup)
286 .align 2
287 __v7_setup_stack:
288 .space 4 * 11 @ 11 registers
290 __INITDATA
292 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
293 define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
295 .section ".rodata"
297 string cpu_arch_name, "armv7"
298 string cpu_elf_name, "v7"
299 .align
301 .section ".proc.info.init", #alloc, #execinstr
303 /*
304 * Standard v7 proc info content
305 */
306 .macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0
307 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
308 PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
309 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
310 PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
311 .long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
312 PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
313 W(b) \initfunc
314 .long cpu_arch_name
315 .long cpu_elf_name
316 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
317 HWCAP_EDSP | HWCAP_TLS | \hwcaps
318 .long cpu_v7_name
319 .long v7_processor_functions
320 .long v7wbi_tlb_fns
321 .long v6_user_fns
322 .long v7_cache_fns
323 .endm
325 #ifndef CONFIG_ARM_LPAE
326 /*
327 * ARM Ltd. Cortex A5 processor.
328 */
329 .type __v7_ca5mp_proc_info, #object
330 __v7_ca5mp_proc_info:
331 .long 0x410fc050
332 .long 0xff0ffff0
333 __v7_proc __v7_ca5mp_setup
334 .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
336 /*
337 * ARM Ltd. Cortex A9 processor.
338 */
339 .type __v7_ca9mp_proc_info, #object
340 __v7_ca9mp_proc_info:
341 .long 0x410fc090
342 .long 0xff0ffff0
343 __v7_proc __v7_ca9mp_setup
344 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
345 #endif /* CONFIG_ARM_LPAE */
347 /*
348 * ARM Ltd. Cortex A7 processor.
349 */
350 .type __v7_ca7mp_proc_info, #object
351 __v7_ca7mp_proc_info:
352 .long 0x410fc070
353 .long 0xff0ffff0
354 __v7_proc __v7_ca7mp_setup, hwcaps = HWCAP_IDIV
355 .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
357 /*
358 * ARM Ltd. Cortex A15 processor.
359 */
360 .type __v7_ca15mp_proc_info, #object
361 __v7_ca15mp_proc_info:
362 .long 0x410fc0f0
363 .long 0xff0ffff0
364 __v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV
365 .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
367 /*
368 * Match any ARMv7 processor core.
369 */
370 .type __v7_proc_info, #object
371 __v7_proc_info:
372 .long 0x000f0000 @ Required ID value
373 .long 0x000f0000 @ Mask for ID
374 __v7_proc __v7_setup
375 .size __v7_proc_info, . - __v7_proc_info