arch/arm/plat-mxc/avic.c

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  17  * MA  02110-1301, USA.
  18  */
  19
  20 #include <linux/module.h>
  21 #include <linux/irq.h>
  22 #include <linux/io.h>
  23 #include <mach/common.h>
  24 #include <asm/mach/irq.h>
  25 #include <asm/exception.h>
  26 #include <mach/hardware.h>
  27
  28 #include "irq-common.h"
  29
  30 #define AVIC_INTCNTL            0x00    /* int control reg */
  31 #define AVIC_NIMASK             0x04    /* int mask reg */
  32 #define AVIC_INTENNUM           0x08    /* int enable number reg */
  33 #define AVIC_INTDISNUM          0x0C    /* int disable number reg */
  34 #define AVIC_INTENABLEH         0x10    /* int enable reg high */
  35 #define AVIC_INTENABLEL         0x14    /* int enable reg low */
  36 #define AVIC_INTTYPEH           0x18    /* int type reg high */
  37 #define AVIC_INTTYPEL           0x1C    /* int type reg low */
  38 #define AVIC_NIPRIORITY(x)      (0x20 + 4 * (7 - (x))) /* int priority */
  39 #define AVIC_NIVECSR            0x40    /* norm int vector/status */
  40 #define AVIC_FIVECSR            0x44    /* fast int vector/status */
  41 #define AVIC_INTSRCH            0x48    /* int source reg high */
  42 #define AVIC_INTSRCL            0x4C    /* int source reg low */
  43 #define AVIC_INTFRCH            0x50    /* int force reg high */
  44 #define AVIC_INTFRCL            0x54    /* int force reg low */
  45 #define AVIC_NIPNDH             0x58    /* norm int pending high */
  46 #define AVIC_NIPNDL             0x5C    /* norm int pending low */
  47 #define AVIC_FIPNDH             0x60    /* fast int pending high */
  48 #define AVIC_FIPNDL             0x64    /* fast int pending low */
  49
  50 #define AVIC_NUM_IRQS 64
  51
  52 void __iomem *avic_base;
  53
  54 static u32 avic_saved_mask_reg[2];
  55
  56 #ifdef CONFIG_MXC_IRQ_PRIOR
  57 static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
  58 {
  59         unsigned int temp;
  60         unsigned int mask = 0x0F << irq % 8 * 4;
  61
  62         if (irq >= AVIC_NUM_IRQS)
  63                 return -EINVAL;;
  64
  65         temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8));
  66         temp &= ~mask;
  67         temp |= prio & mask;
  68
  69         __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8));
  70
  71         return 0;
  72 }
  73 #endif
  74
  75 #ifdef CONFIG_FIQ
  76 static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
  77 {
  78         unsigned int irqt;
  79
  80         if (irq >= AVIC_NUM_IRQS)
  81                 return -EINVAL;
  82
  83         if (irq < AVIC_NUM_IRQS / 2) {
  84                 irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq);
  85                 __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL);
  86         } else {
  87                 irq -= AVIC_NUM_IRQS / 2;
  88                 irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq);
  89                 __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH);
  90         }
  91
  92         return 0;
  93 }
  94 #endif /* CONFIG_FIQ */
  95
  96
  97 static struct mxc_extra_irq avic_extra_irq = {
  98 #ifdef CONFIG_MXC_IRQ_PRIOR
  99         .set_priority = avic_irq_set_priority,
 100 #endif
 101 #ifdef CONFIG_FIQ
 102         .set_irq_fiq = avic_set_irq_fiq,
 103 #endif
 104 };
 105
 106 #ifdef CONFIG_PM
 107 static void avic_irq_suspend(struct irq_data *d)
 108 {
 109         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 110         struct irq_chip_type *ct = gc->chip_types;
 111         int idx = gc->irq_base >> 5;
 112
 113         avic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask);
 114         __raw_writel(gc->wake_active, avic_base + ct->regs.mask);
 115 }
 116
 117 static void avic_irq_resume(struct irq_data *d)
 118 {
 119         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 120         struct irq_chip_type *ct = gc->chip_types;
 121         int idx = gc->irq_base >> 5;
 122
 123         __raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
 124 }
 125
 126 #else
 127 #define avic_irq_suspend NULL
 128 #define avic_irq_resume NULL
 129 #endif
 130
 131 static __init void avic_init_gc(unsigned int irq_start)
 132 {
 133         struct irq_chip_generic *gc;
 134         struct irq_chip_type *ct;
 135         int idx = irq_start >> 5;
 136
 137         gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base,
 138                                     handle_level_irq);
 139         gc->private = &avic_extra_irq;
 140         gc->wake_enabled = IRQ_MSK(32);
 141
 142         ct = gc->chip_types;
 143         ct->chip.irq_mask = irq_gc_mask_clr_bit;
 144         ct->chip.irq_unmask = irq_gc_mask_set_bit;
 145         ct->chip.irq_ack = irq_gc_mask_clr_bit;
 146         ct->chip.irq_set_wake = irq_gc_set_wake;
 147         ct->chip.irq_suspend = avic_irq_suspend;
 148         ct->chip.irq_resume = avic_irq_resume;
 149         ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH;
 150         ct->regs.ack = ct->regs.mask;
 151
 152         irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
 153 }
 154
 155 asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
 156 {
 157         u32 nivector;
 158
 159         do {
 160                 nivector = __raw_readl(avic_base + AVIC_NIVECSR) >> 16;
 161                 if (nivector == 0xffff)
 162                         break;
 163
 164                 handle_IRQ(nivector, regs);
 165         } while (1);
 166 }
 167
 168 /*
 169  * This function initializes the AVIC hardware and disables all the
 170  * interrupts. It registers the interrupt enable and disable functions
 171  * to the kernel for each interrupt source.
 172  */
 173 void __init mxc_init_irq(void __iomem *irqbase)
 174 {
 175         int i;
 176
 177         avic_base = irqbase;
 178
 179         /* put the AVIC into the reset value with
 180          * all interrupts disabled
 181          */
 182         __raw_writel(0, avic_base + AVIC_INTCNTL);
 183         __raw_writel(0x1f, avic_base + AVIC_NIMASK);
 184
 185         /* disable all interrupts */
 186         __raw_writel(0, avic_base + AVIC_INTENABLEH);
 187         __raw_writel(0, avic_base + AVIC_INTENABLEL);
 188
 189         /* all IRQ no FIQ */
 190         __raw_writel(0, avic_base + AVIC_INTTYPEH);
 191         __raw_writel(0, avic_base + AVIC_INTTYPEL);
 192
 193         for (i = 0; i < AVIC_NUM_IRQS; i += 32)
 194                 avic_init_gc(i);
 195
 196         /* Set default priority value (0) for all IRQ's */
 197         for (i = 0; i < 8; i++)
 198                 __raw_writel(0, avic_base + AVIC_NIPRIORITY(i));
 199
 200 #ifdef CONFIG_FIQ
 201         /* Initialize FIQ */
 202         init_FIQ();
 203 #endif
 204
 205         printk(KERN_INFO "MXC IRQ initialized\n");
 206 }