arch/arm/plat-pxa/include/plat/pxa3xx_nand.h

   1 #ifndef __ASM_ARCH_PXA3XX_NAND_H
   2 #define __ASM_ARCH_PXA3XX_NAND_H
   3
   4 #include <linux/mtd/mtd.h>
   5 #include <linux/mtd/partitions.h>
   6
   7 struct pxa3xx_nand_timing {
   8         unsigned int    tCH;  /* Enable signal hold time */
   9         unsigned int    tCS;  /* Enable signal setup time */
  10         unsigned int    tWH;  /* ND_nWE high duration */
  11         unsigned int    tWP;  /* ND_nWE pulse time */
  12         unsigned int    tRH;  /* ND_nRE high duration */
  13         unsigned int    tRP;  /* ND_nRE pulse width */
  14         unsigned int    tR;   /* ND_nWE high to ND_nRE low for read */
  15         unsigned int    tWHR; /* ND_nWE high to ND_nRE low for status read */
  16         unsigned int    tAR;  /* ND_ALE low to ND_nRE low delay */
  17 };
  18
  19 struct pxa3xx_nand_cmdset {
  20         uint16_t        read1;
  21         uint16_t        read2;
  22         uint16_t        program;
  23         uint16_t        read_status;
  24         uint16_t        read_id;
  25         uint16_t        erase;
  26         uint16_t        reset;
  27         uint16_t        lock;
  28         uint16_t        unlock;
  29         uint16_t        lock_status;
  30 };
  31
  32 struct pxa3xx_nand_flash {
  33         char            *name;
  34         uint32_t        chip_id;
  35         unsigned int    page_per_block; /* Pages per block (PG_PER_BLK) */
  36         unsigned int    page_size;      /* Page size in bytes (PAGE_SZ) */
  37         unsigned int    flash_width;    /* Width of Flash memory (DWIDTH_M) */
  38         unsigned int    dfc_width;      /* Width of flash controller(DWIDTH_C) */
  39         unsigned int    num_blocks;     /* Number of physical blocks in Flash */
  40
  41         struct pxa3xx_nand_timing *timing;      /* NAND Flash timing */
  42 };
  43
  44 /*
  45  * Current pxa3xx_nand controller has two chip select which
  46  * both be workable.
  47  *
  48  * Notice should be taken that:
  49  * When you want to use this feature, you should not enable the
  50  * keep configuration feature, for two chip select could be
  51  * attached with different nand chip. The different page size
  52  * and timing requirement make the keep configuration impossible.
  53  */
  54
  55 /* The max num of chip select current support */
  56 #define NUM_CHIP_SELECT         (2)
  57 struct pxa3xx_nand_platform_data {
  58
  59         /* the data flash bus is shared between the Static Memory
  60          * Controller and the Data Flash Controller,  the arbiter
  61          * controls the ownership of the bus
  62          */
  63         int     enable_arbiter;
  64
  65         /* allow platform code to keep OBM/bootloader defined NFC config */
  66         int     keep_config;
  67
  68         /* indicate how many chip selects will be used */
  69         int     num_cs;
  70
  71         const struct mtd_partition              *parts[NUM_CHIP_SELECT];
  72         unsigned int                            nr_parts[NUM_CHIP_SELECT];
  73
  74         const struct pxa3xx_nand_flash *        flash;
  75         size_t                                  num_flash;
  76 };
  77
  78 extern void pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info);
  79 #endif /* __ASM_ARCH_PXA3XX_NAND_H */