Merge tag 'v3.3.7' into 3.3/master
[zen-stable.git] / arch / arm / plat-samsung / include / plat / regs-srom.h
blob9b6729c81cda8731d5845f8a347aacd367527f5c
1 /* linux/arch/arm/plat-samsung/include/plat/regs-srom.h
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * S5P SROMC register definitions
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef __PLAT_SAMSUNG_REGS_SROM_H
14 #define __PLAT_SAMSUNG_REGS_SROM_H __FILE__
16 #include <mach/map.h>
18 #define S5P_SROMREG(x) (S5P_VA_SROMC + (x))
20 #define S5P_SROM_BW S5P_SROMREG(0x0)
21 #define S5P_SROM_BC0 S5P_SROMREG(0x4)
22 #define S5P_SROM_BC1 S5P_SROMREG(0x8)
23 #define S5P_SROM_BC2 S5P_SROMREG(0xc)
24 #define S5P_SROM_BC3 S5P_SROMREG(0x10)
25 #define S5P_SROM_BC4 S5P_SROMREG(0x14)
26 #define S5P_SROM_BC5 S5P_SROMREG(0x18)
28 /* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */
30 #define S5P_SROM_BW__DATAWIDTH__SHIFT 0
31 #define S5P_SROM_BW__ADDRMODE__SHIFT 1
32 #define S5P_SROM_BW__WAITENABLE__SHIFT 2
33 #define S5P_SROM_BW__BYTEENABLE__SHIFT 3
35 #define S5P_SROM_BW__CS_MASK 0xf
37 #define S5P_SROM_BW__NCS0__SHIFT 0
38 #define S5P_SROM_BW__NCS1__SHIFT 4
39 #define S5P_SROM_BW__NCS2__SHIFT 8
40 #define S5P_SROM_BW__NCS3__SHIFT 12
41 #define S5P_SROM_BW__NCS4__SHIFT 16
42 #define S5P_SROM_BW__NCS5__SHIFT 20
44 /* applies to same to BCS0 - BCS3 */
46 #define S5P_SROM_BCX__PMC__SHIFT 0
47 #define S5P_SROM_BCX__TACP__SHIFT 4
48 #define S5P_SROM_BCX__TCAH__SHIFT 8
49 #define S5P_SROM_BCX__TCOH__SHIFT 12
50 #define S5P_SROM_BCX__TACC__SHIFT 16
51 #define S5P_SROM_BCX__TCOS__SHIFT 24
52 #define S5P_SROM_BCX__TACS__SHIFT 28
54 #endif /* __PLAT_SAMSUNG_REGS_SROM_H */