arch/blackfin/mach-bf538/include/mach/anomaly.h

   1 /*
   2  * DO NOT EDIT THIS FILE
   3  * This file is under version control at
   4  *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
   5  * and can be replaced with that version at any time
   6  * DO NOT EDIT THIS FILE
   7  *
   8  * Copyright 2004-2011 Analog Devices Inc.
   9  * Licensed under the ADI BSD license.
  10  *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
  11  */
  12
  13 /* This file should be up to date with:
  14  *  - Revision J, 05/23/2011; ADSP-BF538/BF538F Blackfin Processor Anomaly List
  15  *  - Revision O, 05/23/2011; ADSP-BF539/BF539F Blackfin Processor Anomaly List
  16  */
  17
  18 #ifndef _MACH_ANOMALY_H_
  19 #define _MACH_ANOMALY_H_
  20
  21 /* We do not support old silicon - sorry */
  22 #if __SILICON_REVISION__ < 4
  23 # error will not work on BF538/BF539 silicon version 0.0, 0.1, 0.2, or 0.3
  24 #endif
  25
  26 #if defined(__ADSPBF538__)
  27 # define ANOMALY_BF538 1
  28 #else
  29 # define ANOMALY_BF538 0
  30 #endif
  31 #if defined(__ADSPBF539__)
  32 # define ANOMALY_BF539 1
  33 #else
  34 # define ANOMALY_BF539 0
  35 #endif
  36
  37 /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
  38 #define ANOMALY_05000074 (1)
  39 /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
  40 #define ANOMALY_05000119 (1)
  41 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
  42 #define ANOMALY_05000122 (1)
  43 /* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
  44 #define ANOMALY_05000166 (1)
  45 /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
  46 #define ANOMALY_05000179 (1)
  47 /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
  48 #define ANOMALY_05000180 (1)
  49 /* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
  50 #define ANOMALY_05000193 (1)
  51 /* Current DMA Address Shows Wrong Value During Carry Fix */
  52 #define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
  53 /* NMI Event at Boot Time Results in Unpredictable State */
  54 #define ANOMALY_05000219 (1)
  55 /* SPI Slave Boot Mode Modifies Registers from Reset Value */
  56 #define ANOMALY_05000229 (1)
  57 /* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
  58 #define ANOMALY_05000233 (1)
  59 /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
  60 #define ANOMALY_05000245 (1)
  61 /* Maximum External Clock Speed for Timers */
  62 #define ANOMALY_05000253 (1)
  63 /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
  64 #define ANOMALY_05000270 (__SILICON_REVISION__ < 4)
  65 /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
  66 #define ANOMALY_05000272 (ANOMALY_BF538)
  67 /* Writes to Synchronous SDRAM Memory May Be Lost */
  68 #define ANOMALY_05000273 (__SILICON_REVISION__ < 4)
  69 /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
  70 #define ANOMALY_05000277 (__SILICON_REVISION__ < 4)
  71 /* Disabling Peripherals with DMA Running May Cause DMA System Instability */
  72 #define ANOMALY_05000278 (__SILICON_REVISION__ < 4)
  73 /* False Hardware Error when ISR Context Is Not Restored */
  74 #define ANOMALY_05000281 (__SILICON_REVISION__ < 4)
  75 /* Memory DMA Corruption with 32-Bit Data and Traffic Control */
  76 #define ANOMALY_05000282 (__SILICON_REVISION__ < 4)
  77 /* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
  78 #define ANOMALY_05000283 (__SILICON_REVISION__ < 4)
  79 /* SPORTs May Receive Bad Data If FIFOs Fill Up */
  80 #define ANOMALY_05000288 (__SILICON_REVISION__ < 4)
  81 /* Reads from CAN Mailbox and Acceptance Mask Area Can Fail */
  82 #define ANOMALY_05000291 (__SILICON_REVISION__ < 4)
  83 /* Hibernate Leakage Current Is Higher Than Specified */
  84 #define ANOMALY_05000293 (__SILICON_REVISION__ < 4)
  85 /* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
  86 #define ANOMALY_05000294 (1)
  87 /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
  88 #define ANOMALY_05000301 (__SILICON_REVISION__ < 4)
  89 /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
  90 #define ANOMALY_05000304 (__SILICON_REVISION__ < 4)
  91 /* SCKELOW Bit Does Not Maintain State Through Hibernate */
  92 #define ANOMALY_05000307 (__SILICON_REVISION__ < 4)
  93 /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
  94 #define ANOMALY_05000310 (1)
  95 /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
  96 #define ANOMALY_05000312 (__SILICON_REVISION__ < 5)
  97 /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
  98 #define ANOMALY_05000313 (__SILICON_REVISION__ < 4)
  99 /* Killed System MMR Write Completes Erroneously on Next System MMR Access */
 100 #define ANOMALY_05000315 (__SILICON_REVISION__ < 4)
 101 /* PFx Glitch on Write to PORTFIO or PORTFIO_TOGGLE */
 102 #define ANOMALY_05000317 (__SILICON_REVISION__ < 4)     /* XXX: Same as 05000318 */
 103 /* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */
 104 #define ANOMALY_05000318 (__SILICON_REVISION__ < 4)     /* XXX: Same as 05000317 */
 105 /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
 106 #define ANOMALY_05000355 (__SILICON_REVISION__ < 5)
 107 /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
 108 #define ANOMALY_05000357 (__SILICON_REVISION__ < 5)
 109 /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
 110 #define ANOMALY_05000366 (1)
 111 /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
 112 #define ANOMALY_05000371 (__SILICON_REVISION__ < 5)
 113 /* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */
 114 #define ANOMALY_05000374 (__SILICON_REVISION__ == 4)
 115 /* GPIO Pins PC1 and PC4 Can Function as Normal Outputs */
 116 #define ANOMALY_05000375 (__SILICON_REVISION__ < 4)
 117 /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
 118 #define ANOMALY_05000402 (__SILICON_REVISION__ == 3)
 119 /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
 120 #define ANOMALY_05000403 (1)
 121 /* Speculative Fetches Can Cause Undesired External FIFO Operations */
 122 #define ANOMALY_05000416 (1)
 123 /* Multichannel SPORT Channel Misalignment Under Specific Configuration */
 124 #define ANOMALY_05000425 (1)
 125 /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
 126 #define ANOMALY_05000426 (1)
 127 /* Specific GPIO Pins May Change State when Entering Hibernate */
 128 #define ANOMALY_05000436 (__SILICON_REVISION__ > 3)
 129 /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
 130 #define ANOMALY_05000443 (1)
 131 /* False Hardware Error when RETI Points to Invalid Memory */
 132 #define ANOMALY_05000461 (1)
 133 /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
 134 #define ANOMALY_05000462 (1)
 135 /* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
 136 #define ANOMALY_05000473 (1)
 137 /* Possible Lockup Condition when Modifying PLL from External Memory */
 138 #define ANOMALY_05000475 (1)
 139 /* TESTSET Instruction Cannot Be Interrupted */
 140 #define ANOMALY_05000477 (1)
 141 /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
 142 #define ANOMALY_05000481 (1)
 143 /* PLL May Latch Incorrect Values Coming Out of Reset */
 144 #define ANOMALY_05000489 (1)
 145 /* Instruction Memory Stalls Can Cause IFLUSH to Fail */
 146 #define ANOMALY_05000491 (1)
 147 /* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
 148 #define ANOMALY_05000494 (1)
 149 /* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
 150 #define ANOMALY_05000501 (1)
 151
 152 /*
 153  * These anomalies have been "phased" out of analog.com anomaly sheets and are
 154  * here to show running on older silicon just isn't feasible.
 155  */
 156
 157 /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
 158 #define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
 159 /* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
 160 #define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
 161
 162 /* Anomalies that don't exist on this proc */
 163 #define ANOMALY_05000099 (0)
 164 #define ANOMALY_05000120 (0)
 165 #define ANOMALY_05000125 (0)
 166 #define ANOMALY_05000149 (0)
 167 #define ANOMALY_05000158 (0)
 168 #define ANOMALY_05000171 (0)
 169 #define ANOMALY_05000182 (0)
 170 #define ANOMALY_05000189 (0)
 171 #define ANOMALY_05000198 (0)
 172 #define ANOMALY_05000202 (0)
 173 #define ANOMALY_05000215 (0)
 174 #define ANOMALY_05000220 (0)
 175 #define ANOMALY_05000227 (0)
 176 #define ANOMALY_05000230 (0)
 177 #define ANOMALY_05000231 (0)
 178 #define ANOMALY_05000234 (0)
 179 #define ANOMALY_05000242 (0)
 180 #define ANOMALY_05000248 (0)
 181 #define ANOMALY_05000250 (0)
 182 #define ANOMALY_05000254 (0)
 183 #define ANOMALY_05000257 (0)
 184 #define ANOMALY_05000263 (0)
 185 #define ANOMALY_05000266 (0)
 186 #define ANOMALY_05000274 (0)
 187 #define ANOMALY_05000287 (0)
 188 #define ANOMALY_05000305 (0)
 189 #define ANOMALY_05000311 (0)
 190 #define ANOMALY_05000323 (0)
 191 #define ANOMALY_05000353 (1)
 192 #define ANOMALY_05000362 (1)
 193 #define ANOMALY_05000363 (0)
 194 #define ANOMALY_05000364 (0)
 195 #define ANOMALY_05000380 (0)
 196 #define ANOMALY_05000383 (0)
 197 #define ANOMALY_05000386 (1)
 198 #define ANOMALY_05000389 (0)
 199 #define ANOMALY_05000400 (0)
 200 #define ANOMALY_05000412 (0)
 201 #define ANOMALY_05000430 (0)
 202 #define ANOMALY_05000432 (0)
 203 #define ANOMALY_05000435 (0)
 204 #define ANOMALY_05000440 (0)
 205 #define ANOMALY_05000447 (0)
 206 #define ANOMALY_05000448 (0)
 207 #define ANOMALY_05000456 (0)
 208 #define ANOMALY_05000450 (0)
 209 #define ANOMALY_05000465 (0)
 210 #define ANOMALY_05000467 (0)
 211 #define ANOMALY_05000474 (0)
 212 #define ANOMALY_05000480 (0)
 213 #define ANOMALY_05000485 (0)
 214
 215 #endif