5 * This file is autogenerated from
6 * file: ../../mod/fakereg.rmap
7 * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp
8 * last modified: Wed Feb 11 20:53:25 2004
9 * file: ../../rtl/global.rmap
10 * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp
11 * last modified: Mon Aug 18 17:08:23 2003
12 * file: ../../mod/modreg.rmap
13 * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp
14 * last modified: Fri Feb 20 16:40:04 2004
16 * by /n/asic/design/tools/rdesc/src/rdes2c -map -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/io_proc/rtl/guinness/iop_top.r ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap
17 * id: $Id: reg_map.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
18 * Any changes here will be lost.
20 * -*- buffer-read-only: t -*-
23 regi_ata
= 0xb0032000,
24 regi_bif_core
= 0xb0014000,
25 regi_bif_dma
= 0xb0016000,
26 regi_bif_slave
= 0xb0018000,
27 regi_config
= 0xb003c000,
28 regi_dma0
= 0xb0000000,
29 regi_dma1
= 0xb0002000,
30 regi_dma2
= 0xb0004000,
31 regi_dma3
= 0xb0006000,
32 regi_dma4
= 0xb0008000,
33 regi_dma5
= 0xb000a000,
34 regi_dma6
= 0xb000c000,
35 regi_dma7
= 0xb000e000,
36 regi_dma8
= 0xb0010000,
37 regi_dma9
= 0xb0012000,
38 regi_eth0
= 0xb0034000,
39 regi_eth1
= 0xb0036000,
40 regi_gio
= 0xb001a000,
41 regi_iop
= 0xb0020000,
42 regi_iop_version
= 0xb0020000,
43 regi_iop_fifo_in0_extra
= 0xb0020040,
44 regi_iop_fifo_in1_extra
= 0xb0020080,
45 regi_iop_fifo_out0_extra
= 0xb00200c0,
46 regi_iop_fifo_out1_extra
= 0xb0020100,
47 regi_iop_trigger_grp0
= 0xb0020140,
48 regi_iop_trigger_grp1
= 0xb0020180,
49 regi_iop_trigger_grp2
= 0xb00201c0,
50 regi_iop_trigger_grp3
= 0xb0020200,
51 regi_iop_trigger_grp4
= 0xb0020240,
52 regi_iop_trigger_grp5
= 0xb0020280,
53 regi_iop_trigger_grp6
= 0xb00202c0,
54 regi_iop_trigger_grp7
= 0xb0020300,
55 regi_iop_crc_par0
= 0xb0020380,
56 regi_iop_crc_par1
= 0xb0020400,
57 regi_iop_dmc_in0
= 0xb0020480,
58 regi_iop_dmc_in1
= 0xb0020500,
59 regi_iop_dmc_out0
= 0xb0020580,
60 regi_iop_dmc_out1
= 0xb0020600,
61 regi_iop_fifo_in0
= 0xb0020680,
62 regi_iop_fifo_in1
= 0xb0020700,
63 regi_iop_fifo_out0
= 0xb0020780,
64 regi_iop_fifo_out1
= 0xb0020800,
65 regi_iop_scrc_in0
= 0xb0020880,
66 regi_iop_scrc_in1
= 0xb0020900,
67 regi_iop_scrc_out0
= 0xb0020980,
68 regi_iop_scrc_out1
= 0xb0020a00,
69 regi_iop_timer_grp0
= 0xb0020a80,
70 regi_iop_timer_grp1
= 0xb0020b00,
71 regi_iop_timer_grp2
= 0xb0020b80,
72 regi_iop_timer_grp3
= 0xb0020c00,
73 regi_iop_sap_in
= 0xb0020d00,
74 regi_iop_sap_out
= 0xb0020e00,
75 regi_iop_spu0
= 0xb0020f00,
76 regi_iop_spu1
= 0xb0021000,
77 regi_iop_sw_cfg
= 0xb0021100,
78 regi_iop_sw_cpu
= 0xb0021200,
79 regi_iop_sw_mpu
= 0xb0021300,
80 regi_iop_sw_spu0
= 0xb0021400,
81 regi_iop_sw_spu1
= 0xb0021500,
82 regi_iop_mpu
= 0xb0021600,
83 regi_irq
= 0xb001c000,
84 regi_irq2
= 0xb005c000,
85 regi_marb
= 0xb003e000,
86 regi_marb_bp0
= 0xb003e240,
87 regi_marb_bp1
= 0xb003e280,
88 regi_marb_bp2
= 0xb003e2c0,
89 regi_marb_bp3
= 0xb003e300,
90 regi_pinmux
= 0xb0038000,
91 regi_ser0
= 0xb0026000,
92 regi_ser1
= 0xb0028000,
93 regi_ser2
= 0xb002a000,
94 regi_ser3
= 0xb002c000,
95 regi_sser0
= 0xb0022000,
96 regi_sser1
= 0xb0024000,
97 regi_strcop
= 0xb0030000,
98 regi_strmux
= 0xb003a000,
99 regi_timer
= 0xb001e000,
100 regi_timer0
= 0xb001e000,
101 regi_timer2
= 0xb005e000,
102 regi_trace
= 0xb0040000,
103 } reg_scope_instances
;
104 #endif /* __reg_map_h */
