arch/cris/include/arch-v32/mach-fs/mach/hwregs/timer_defs.h

   1 #ifndef __timer_defs_h
   2 #define __timer_defs_h
   3
   4 /*
   5  * This file is autogenerated from
   6  *   file:           ../../inst/timer/rtl/timer_regs.r
   7  *     id:           timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp
   8  *     last modfied: Mon Apr 11 16:09:53 2005
   9  *
  10  *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile timer_defs.h ../../inst/timer/rtl/timer_regs.r
  11  *      id: $Id: timer_defs.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $
  12  * Any changes here will be lost.
  13  *
  14  * -*- buffer-read-only: t -*-
  15  */
  16 /* Main access macros */
  17 #ifndef REG_RD
  18 #define REG_RD( scope, inst, reg ) \
  19   REG_READ( reg_##scope##_##reg, \
  20             (inst) + REG_RD_ADDR_##scope##_##reg )
  21 #endif
  22
  23 #ifndef REG_WR
  24 #define REG_WR( scope, inst, reg, val ) \
  25   REG_WRITE( reg_##scope##_##reg, \
  26              (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  27 #endif
  28
  29 #ifndef REG_RD_VECT
  30 #define REG_RD_VECT( scope, inst, reg, index ) \
  31   REG_READ( reg_##scope##_##reg, \
  32             (inst) + REG_RD_ADDR_##scope##_##reg + \
  33             (index) * STRIDE_##scope##_##reg )
  34 #endif
  35
  36 #ifndef REG_WR_VECT
  37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
  38   REG_WRITE( reg_##scope##_##reg, \
  39              (inst) + REG_WR_ADDR_##scope##_##reg + \
  40              (index) * STRIDE_##scope##_##reg, (val) )
  41 #endif
  42
  43 #ifndef REG_RD_INT
  44 #define REG_RD_INT( scope, inst, reg ) \
  45   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
  46 #endif
  47
  48 #ifndef REG_WR_INT
  49 #define REG_WR_INT( scope, inst, reg, val ) \
  50   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  51 #endif
  52
  53 #ifndef REG_RD_INT_VECT
  54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
  55   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
  56             (index) * STRIDE_##scope##_##reg )
  57 #endif
  58
  59 #ifndef REG_WR_INT_VECT
  60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
  61   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
  62              (index) * STRIDE_##scope##_##reg, (val) )
  63 #endif
  64
  65 #ifndef REG_TYPE_CONV
  66 #define REG_TYPE_CONV( type, orgtype, val ) \
  67   ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
  68 #endif
  69
  70 #ifndef reg_page_size
  71 #define reg_page_size 8192
  72 #endif
  73
  74 #ifndef REG_ADDR
  75 #define REG_ADDR( scope, inst, reg ) \
  76   ( (inst) + REG_RD_ADDR_##scope##_##reg )
  77 #endif
  78
  79 #ifndef REG_ADDR_VECT
  80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
  81   ( (inst) + REG_RD_ADDR_##scope##_##reg + \
  82     (index) * STRIDE_##scope##_##reg )
  83 #endif
  84
  85 /* C-code for register scope timer */
  86
  87 /* Register rw_tmr0_div, scope timer, type rw */
  88 typedef unsigned int reg_timer_rw_tmr0_div;
  89 #define REG_RD_ADDR_timer_rw_tmr0_div 0
  90 #define REG_WR_ADDR_timer_rw_tmr0_div 0
  91
  92 /* Register r_tmr0_data, scope timer, type r */
  93 typedef unsigned int reg_timer_r_tmr0_data;
  94 #define REG_RD_ADDR_timer_r_tmr0_data 4
  95
  96 /* Register rw_tmr0_ctrl, scope timer, type rw */
  97 typedef struct {
  98   unsigned int op   : 2;
  99   unsigned int freq : 3;
 100   unsigned int dummy1 : 27;
 101 } reg_timer_rw_tmr0_ctrl;
 102 #define REG_RD_ADDR_timer_rw_tmr0_ctrl 8
 103 #define REG_WR_ADDR_timer_rw_tmr0_ctrl 8
 104
 105 /* Register rw_tmr1_div, scope timer, type rw */
 106 typedef unsigned int reg_timer_rw_tmr1_div;
 107 #define REG_RD_ADDR_timer_rw_tmr1_div 16
 108 #define REG_WR_ADDR_timer_rw_tmr1_div 16
 109
 110 /* Register r_tmr1_data, scope timer, type r */
 111 typedef unsigned int reg_timer_r_tmr1_data;
 112 #define REG_RD_ADDR_timer_r_tmr1_data 20
 113
 114 /* Register rw_tmr1_ctrl, scope timer, type rw */
 115 typedef struct {
 116   unsigned int op   : 2;
 117   unsigned int freq : 3;
 118   unsigned int dummy1 : 27;
 119 } reg_timer_rw_tmr1_ctrl;
 120 #define REG_RD_ADDR_timer_rw_tmr1_ctrl 24
 121 #define REG_WR_ADDR_timer_rw_tmr1_ctrl 24
 122
 123 /* Register rs_cnt_data, scope timer, type rs */
 124 typedef struct {
 125   unsigned int tmr : 24;
 126   unsigned int cnt : 8;
 127 } reg_timer_rs_cnt_data;
 128 #define REG_RD_ADDR_timer_rs_cnt_data 32
 129
 130 /* Register r_cnt_data, scope timer, type r */
 131 typedef struct {
 132   unsigned int tmr : 24;
 133   unsigned int cnt : 8;
 134 } reg_timer_r_cnt_data;
 135 #define REG_RD_ADDR_timer_r_cnt_data 36
 136
 137 /* Register rw_cnt_cfg, scope timer, type rw */
 138 typedef struct {
 139   unsigned int clk : 2;
 140   unsigned int dummy1 : 30;
 141 } reg_timer_rw_cnt_cfg;
 142 #define REG_RD_ADDR_timer_rw_cnt_cfg 40
 143 #define REG_WR_ADDR_timer_rw_cnt_cfg 40
 144
 145 /* Register rw_trig, scope timer, type rw */
 146 typedef unsigned int reg_timer_rw_trig;
 147 #define REG_RD_ADDR_timer_rw_trig 48
 148 #define REG_WR_ADDR_timer_rw_trig 48
 149
 150 /* Register rw_trig_cfg, scope timer, type rw */
 151 typedef struct {
 152   unsigned int tmr : 2;
 153   unsigned int dummy1 : 30;
 154 } reg_timer_rw_trig_cfg;
 155 #define REG_RD_ADDR_timer_rw_trig_cfg 52
 156 #define REG_WR_ADDR_timer_rw_trig_cfg 52
 157
 158 /* Register r_time, scope timer, type r */
 159 typedef unsigned int reg_timer_r_time;
 160 #define REG_RD_ADDR_timer_r_time 56
 161
 162 /* Register rw_out, scope timer, type rw */
 163 typedef struct {
 164   unsigned int tmr : 2;
 165   unsigned int dummy1 : 30;
 166 } reg_timer_rw_out;
 167 #define REG_RD_ADDR_timer_rw_out 60
 168 #define REG_WR_ADDR_timer_rw_out 60
 169
 170 /* Register rw_wd_ctrl, scope timer, type rw */
 171 typedef struct {
 172   unsigned int cnt : 8;
 173   unsigned int cmd : 1;
 174   unsigned int key : 7;
 175   unsigned int dummy1 : 16;
 176 } reg_timer_rw_wd_ctrl;
 177 #define REG_RD_ADDR_timer_rw_wd_ctrl 64
 178 #define REG_WR_ADDR_timer_rw_wd_ctrl 64
 179
 180 /* Register r_wd_stat, scope timer, type r */
 181 typedef struct {
 182   unsigned int cnt : 8;
 183   unsigned int cmd : 1;
 184   unsigned int dummy1 : 23;
 185 } reg_timer_r_wd_stat;
 186 #define REG_RD_ADDR_timer_r_wd_stat 68
 187
 188 /* Register rw_intr_mask, scope timer, type rw */
 189 typedef struct {
 190   unsigned int tmr0 : 1;
 191   unsigned int tmr1 : 1;
 192   unsigned int cnt  : 1;
 193   unsigned int trig : 1;
 194   unsigned int dummy1 : 28;
 195 } reg_timer_rw_intr_mask;
 196 #define REG_RD_ADDR_timer_rw_intr_mask 72
 197 #define REG_WR_ADDR_timer_rw_intr_mask 72
 198
 199 /* Register rw_ack_intr, scope timer, type rw */
 200 typedef struct {
 201   unsigned int tmr0 : 1;
 202   unsigned int tmr1 : 1;
 203   unsigned int cnt  : 1;
 204   unsigned int trig : 1;
 205   unsigned int dummy1 : 28;
 206 } reg_timer_rw_ack_intr;
 207 #define REG_RD_ADDR_timer_rw_ack_intr 76
 208 #define REG_WR_ADDR_timer_rw_ack_intr 76
 209
 210 /* Register r_intr, scope timer, type r */
 211 typedef struct {
 212   unsigned int tmr0 : 1;
 213   unsigned int tmr1 : 1;
 214   unsigned int cnt  : 1;
 215   unsigned int trig : 1;
 216   unsigned int dummy1 : 28;
 217 } reg_timer_r_intr;
 218 #define REG_RD_ADDR_timer_r_intr 80
 219
 220 /* Register r_masked_intr, scope timer, type r */
 221 typedef struct {
 222   unsigned int tmr0 : 1;
 223   unsigned int tmr1 : 1;
 224   unsigned int cnt  : 1;
 225   unsigned int trig : 1;
 226   unsigned int dummy1 : 28;
 227 } reg_timer_r_masked_intr;
 228 #define REG_RD_ADDR_timer_r_masked_intr 84
 229
 230 /* Register rw_test, scope timer, type rw */
 231 typedef struct {
 232   unsigned int dis : 1;
 233   unsigned int en  : 1;
 234   unsigned int dummy1 : 30;
 235 } reg_timer_rw_test;
 236 #define REG_RD_ADDR_timer_rw_test 88
 237 #define REG_WR_ADDR_timer_rw_test 88
 238
 239
 240 /* Constants */
 241 enum {
 242   regk_timer_ext                           = 0x00000001,
 243   regk_timer_f100                          = 0x00000007,
 244   regk_timer_f29_493                       = 0x00000004,
 245   regk_timer_f32                           = 0x00000005,
 246   regk_timer_f32_768                       = 0x00000006,
 247   regk_timer_hold                          = 0x00000001,
 248   regk_timer_ld                            = 0x00000000,
 249   regk_timer_no                            = 0x00000000,
 250   regk_timer_off                           = 0x00000000,
 251   regk_timer_run                           = 0x00000002,
 252   regk_timer_rw_cnt_cfg_default            = 0x00000000,
 253   regk_timer_rw_intr_mask_default          = 0x00000000,
 254   regk_timer_rw_out_default                = 0x00000000,
 255   regk_timer_rw_test_default               = 0x00000000,
 256   regk_timer_rw_tmr0_ctrl_default          = 0x00000000,
 257   regk_timer_rw_tmr1_ctrl_default          = 0x00000000,
 258   regk_timer_rw_trig_cfg_default           = 0x00000000,
 259   regk_timer_start                         = 0x00000001,
 260   regk_timer_stop                          = 0x00000000,
 261   regk_timer_time                          = 0x00000001,
 262   regk_timer_tmr0                          = 0x00000002,
 263   regk_timer_tmr1                          = 0x00000003,
 264   regk_timer_yes                           = 0x00000001
 265 };
 266 #endif /* __timer_defs_h */