arch/mips/bcm63xx/cpu.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   7  * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
   8  */
   9
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/cpu.h>
  13 #include <asm/cpu.h>
  14 #include <asm/cpu-info.h>
  15 #include <asm/mipsregs.h>
  16 #include <bcm63xx_cpu.h>
  17 #include <bcm63xx_regs.h>
  18 #include <bcm63xx_io.h>
  19 #include <bcm63xx_irq.h>
  20
  21 const unsigned long *bcm63xx_regs_base;
  22 EXPORT_SYMBOL(bcm63xx_regs_base);
  23
  24 const int *bcm63xx_irqs;
  25 EXPORT_SYMBOL(bcm63xx_irqs);
  26
  27 static u16 bcm63xx_cpu_id;
  28 static u16 bcm63xx_cpu_rev;
  29 static unsigned int bcm63xx_cpu_freq;
  30 static unsigned int bcm63xx_memory_size;
  31
  32 static const unsigned long bcm6338_regs_base[] = {
  33         __GEN_CPU_REGS_TABLE(6338)
  34 };
  35
  36 static const int bcm6338_irqs[] = {
  37         __GEN_CPU_IRQ_TABLE(6338)
  38 };
  39
  40 static const unsigned long bcm6345_regs_base[] = {
  41         __GEN_CPU_REGS_TABLE(6345)
  42 };
  43
  44 static const int bcm6345_irqs[] = {
  45         __GEN_CPU_IRQ_TABLE(6345)
  46 };
  47
  48 static const unsigned long bcm6348_regs_base[] = {
  49         __GEN_CPU_REGS_TABLE(6348)
  50 };
  51
  52 static const int bcm6348_irqs[] = {
  53         __GEN_CPU_IRQ_TABLE(6348)
  54
  55 };
  56
  57 static const unsigned long bcm6358_regs_base[] = {
  58         __GEN_CPU_REGS_TABLE(6358)
  59 };
  60
  61 static const int bcm6358_irqs[] = {
  62         __GEN_CPU_IRQ_TABLE(6358)
  63
  64 };
  65
  66 static const unsigned long bcm6368_regs_base[] = {
  67         __GEN_CPU_REGS_TABLE(6368)
  68 };
  69
  70 static const int bcm6368_irqs[] = {
  71         __GEN_CPU_IRQ_TABLE(6368)
  72
  73 };
  74
  75 u16 __bcm63xx_get_cpu_id(void)
  76 {
  77         return bcm63xx_cpu_id;
  78 }
  79
  80 EXPORT_SYMBOL(__bcm63xx_get_cpu_id);
  81
  82 u16 bcm63xx_get_cpu_rev(void)
  83 {
  84         return bcm63xx_cpu_rev;
  85 }
  86
  87 EXPORT_SYMBOL(bcm63xx_get_cpu_rev);
  88
  89 unsigned int bcm63xx_get_cpu_freq(void)
  90 {
  91         return bcm63xx_cpu_freq;
  92 }
  93
  94 unsigned int bcm63xx_get_memory_size(void)
  95 {
  96         return bcm63xx_memory_size;
  97 }
  98
  99 static unsigned int detect_cpu_clock(void)
 100 {
 101         switch (bcm63xx_get_cpu_id()) {
 102         case BCM6338_CPU_ID:
 103                 /* BCM6338 has a fixed 240 Mhz frequency */
 104                 return 240000000;
 105
 106         case BCM6345_CPU_ID:
 107                 /* BCM6345 has a fixed 140Mhz frequency */
 108                 return 140000000;
 109
 110         case BCM6348_CPU_ID:
 111         {
 112                 unsigned int tmp, n1, n2, m1;
 113
 114                 /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
 115                 tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
 116                 n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
 117                 n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT;
 118                 m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT;
 119                 n1 += 1;
 120                 n2 += 2;
 121                 m1 += 1;
 122                 return (16 * 1000000 * n1 * n2) / m1;
 123         }
 124
 125         case BCM6358_CPU_ID:
 126         {
 127                 unsigned int tmp, n1, n2, m1;
 128
 129                 /* 16MHz * N1 * N2 / M1_CPU */
 130                 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
 131                 n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
 132                 n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
 133                 m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
 134                 return (16 * 1000000 * n1 * n2) / m1;
 135         }
 136
 137         case BCM6368_CPU_ID:
 138         {
 139                 unsigned int tmp, p1, p2, ndiv, m1;
 140
 141                 /* (64MHz / P1) * P2 * NDIV / M1_CPU */
 142                 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_6368_REG);
 143
 144                 p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >>
 145                         DMIPSPLLCFG_6368_P1_SHIFT;
 146
 147                 p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >>
 148                         DMIPSPLLCFG_6368_P2_SHIFT;
 149
 150                 ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >>
 151                         DMIPSPLLCFG_6368_NDIV_SHIFT;
 152
 153                 tmp = bcm_ddr_readl(DDR_DMIPSPLLDIV_6368_REG);
 154                 m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >>
 155                         DMIPSPLLDIV_6368_MDIV_SHIFT;
 156
 157                 return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
 158         }
 159
 160         default:
 161                 BUG();
 162         }
 163 }
 164
 165 /*
 166  * attempt to detect the amount of memory installed
 167  */
 168 static unsigned int detect_memory_size(void)
 169 {
 170         unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
 171         u32 val;
 172
 173         if (BCMCPU_IS_6345()) {
 174                 val = bcm_sdram_readl(SDRAM_MBASE_REG);
 175                 return (val * 8 * 1024 * 1024);
 176         }
 177
 178         if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
 179                 val = bcm_sdram_readl(SDRAM_CFG_REG);
 180                 rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
 181                 cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
 182                 is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
 183                 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
 184         }
 185
 186         if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
 187                 val = bcm_memc_readl(MEMC_CFG_REG);
 188                 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
 189                 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
 190                 is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
 191                 banks = 2;
 192         }
 193
 194         /* 0 => 11 address bits ... 2 => 13 address bits */
 195         rows += 11;
 196
 197         /* 0 => 8 address bits ... 2 => 10 address bits */
 198         cols += 8;
 199
 200         return 1 << (cols + rows + (is_32bits + 1) + banks);
 201 }
 202
 203 void __init bcm63xx_cpu_init(void)
 204 {
 205         unsigned int tmp, expected_cpu_id;
 206         struct cpuinfo_mips *c = &current_cpu_data;
 207         unsigned int cpu = smp_processor_id();
 208
 209         /* soc registers location depends on cpu type */
 210         expected_cpu_id = 0;
 211
 212         switch (c->cputype) {
 213         case CPU_BMIPS3300:
 214                 if ((read_c0_prid() & 0xff00) == PRID_IMP_BMIPS3300_ALT) {
 215                         expected_cpu_id = BCM6348_CPU_ID;
 216                         bcm63xx_regs_base = bcm6348_regs_base;
 217                         bcm63xx_irqs = bcm6348_irqs;
 218                 } else {
 219                         __cpu_name[cpu] = "Broadcom BCM6338";
 220                         expected_cpu_id = BCM6338_CPU_ID;
 221                         bcm63xx_regs_base = bcm6338_regs_base;
 222                         bcm63xx_irqs = bcm6338_irqs;
 223                 }
 224                 break;
 225         case CPU_BMIPS32:
 226                 expected_cpu_id = BCM6345_CPU_ID;
 227                 bcm63xx_regs_base = bcm6345_regs_base;
 228                 bcm63xx_irqs = bcm6345_irqs;
 229                 break;
 230         case CPU_BMIPS4350:
 231                 switch (read_c0_prid() & 0xf0) {
 232                 case 0x10:
 233                         expected_cpu_id = BCM6358_CPU_ID;
 234                         bcm63xx_regs_base = bcm6358_regs_base;
 235                         bcm63xx_irqs = bcm6358_irqs;
 236                         break;
 237                 case 0x30:
 238                         expected_cpu_id = BCM6368_CPU_ID;
 239                         bcm63xx_regs_base = bcm6368_regs_base;
 240                         bcm63xx_irqs = bcm6368_irqs;
 241                         break;
 242                 }
 243                 break;
 244         }
 245
 246         /*
 247          * really early to panic, but delaying panic would not help since we
 248          * will never get any working console
 249          */
 250         if (!expected_cpu_id)
 251                 panic("unsupported Broadcom CPU");
 252
 253         /*
 254          * bcm63xx_regs_base is set, we can access soc registers
 255          */
 256
 257         /* double check CPU type */
 258         tmp = bcm_perf_readl(PERF_REV_REG);
 259         bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
 260         bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
 261
 262         if (bcm63xx_cpu_id != expected_cpu_id)
 263                 panic("bcm63xx CPU id mismatch");
 264
 265         bcm63xx_cpu_freq = detect_cpu_clock();
 266         bcm63xx_memory_size = detect_memory_size();
 267
 268         printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n",
 269                bcm63xx_cpu_id, bcm63xx_cpu_rev);
 270         printk(KERN_INFO "CPU frequency is %u MHz\n",
 271                bcm63xx_cpu_freq / 1000000);
 272         printk(KERN_INFO "%uMB of RAM installed\n",
 273                bcm63xx_memory_size >> 20);
 274 }