arch/mips/cavium-octeon/csrc-octeon.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2007 by Ralf Baechle
   7  * Copyright (C) 2009, 2010 Cavium Networks, Inc.
   8  */
   9 #include <linux/clocksource.h>
  10 #include <linux/export.h>
  11 #include <linux/init.h>
  12 #include <linux/smp.h>
  13
  14 #include <asm/cpu-info.h>
  15 #include <asm/time.h>
  16
  17 #include <asm/octeon/octeon.h>
  18 #include <asm/octeon/cvmx-ipd-defs.h>
  19 #include <asm/octeon/cvmx-mio-defs.h>
  20
  21 /*
  22  * Set the current core's cvmcount counter to the value of the
  23  * IPD_CLK_COUNT.  We do this on all cores as they are brought
  24  * on-line.  This allows for a read from a local cpu register to
  25  * access a synchronized counter.
  26  *
  27  * On CPU_CAVIUM_OCTEON2 the IPD_CLK_COUNT is scaled by rdiv/sdiv.
  28  */
  29 void octeon_init_cvmcount(void)
  30 {
  31         unsigned long flags;
  32         unsigned loops = 2;
  33         u64 f = 0;
  34         u64 rdiv = 0;
  35         u64 sdiv = 0;
  36         if (current_cpu_type() == CPU_CAVIUM_OCTEON2) {
  37                 union cvmx_mio_rst_boot rst_boot;
  38                 rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
  39                 rdiv = rst_boot.s.c_mul;        /* CPU clock */
  40                 sdiv = rst_boot.s.pnr_mul;      /* I/O clock */
  41                 f = (0x8000000000000000ull / sdiv) * 2;
  42         }
  43
  44
  45         /* Clobber loops so GCC will not unroll the following while loop. */
  46         asm("" : "+r" (loops));
  47
  48         local_irq_save(flags);
  49         /*
  50          * Loop several times so we are executing from the cache,
  51          * which should give more deterministic timing.
  52          */
  53         while (loops--) {
  54                 u64 ipd_clk_count = cvmx_read_csr(CVMX_IPD_CLK_COUNT);
  55                 if (rdiv != 0) {
  56                         ipd_clk_count *= rdiv;
  57                         if (f != 0) {
  58                                 asm("dmultu\t%[cnt],%[f]\n\t"
  59                                     "mfhi\t%[cnt]"
  60                                     : [cnt] "+r" (ipd_clk_count),
  61                                       [f] "=r" (f)
  62                                     : : "hi", "lo");
  63                         }
  64                 }
  65                 write_c0_cvmcount(ipd_clk_count);
  66         }
  67         local_irq_restore(flags);
  68 }
  69
  70 static cycle_t octeon_cvmcount_read(struct clocksource *cs)
  71 {
  72         return read_c0_cvmcount();
  73 }
  74
  75 static struct clocksource clocksource_mips = {
  76         .name           = "OCTEON_CVMCOUNT",
  77         .read           = octeon_cvmcount_read,
  78         .mask           = CLOCKSOURCE_MASK(64),
  79         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  80 };
  81
  82 unsigned long long notrace sched_clock(void)
  83 {
  84         /* 64-bit arithmatic can overflow, so use 128-bit.  */
  85         u64 t1, t2, t3;
  86         unsigned long long rv;
  87         u64 mult = clocksource_mips.mult;
  88         u64 shift = clocksource_mips.shift;
  89         u64 cnt = read_c0_cvmcount();
  90
  91         asm (
  92                 "dmultu\t%[cnt],%[mult]\n\t"
  93                 "nor\t%[t1],$0,%[shift]\n\t"
  94                 "mfhi\t%[t2]\n\t"
  95                 "mflo\t%[t3]\n\t"
  96                 "dsll\t%[t2],%[t2],1\n\t"
  97                 "dsrlv\t%[rv],%[t3],%[shift]\n\t"
  98                 "dsllv\t%[t1],%[t2],%[t1]\n\t"
  99                 "or\t%[rv],%[t1],%[rv]\n\t"
 100                 : [rv] "=&r" (rv), [t1] "=&r" (t1), [t2] "=&r" (t2), [t3] "=&r" (t3)
 101                 : [cnt] "r" (cnt), [mult] "r" (mult), [shift] "r" (shift)
 102                 : "hi", "lo");
 103         return rv;
 104 }
 105
 106 void __init plat_time_init(void)
 107 {
 108         clocksource_mips.rating = 300;
 109         clocksource_register_hz(&clocksource_mips, octeon_get_clock_rate());
 110 }
 111
 112 static u64 octeon_udelay_factor;
 113 static u64 octeon_ndelay_factor;
 114
 115 void __init octeon_setup_delays(void)
 116 {
 117         octeon_udelay_factor = octeon_get_clock_rate() / 1000000;
 118         /*
 119          * For __ndelay we divide by 2^16, so the factor is multiplied
 120          * by the same amount.
 121          */
 122         octeon_ndelay_factor = (octeon_udelay_factor * 0x10000ull) / 1000ull;
 123
 124         preset_lpj = octeon_get_clock_rate() / HZ;
 125 }
 126
 127 void __udelay(unsigned long us)
 128 {
 129         u64 cur, end, inc;
 130
 131         cur = read_c0_cvmcount();
 132
 133         inc = us * octeon_udelay_factor;
 134         end = cur + inc;
 135
 136         while (end > cur)
 137                 cur = read_c0_cvmcount();
 138 }
 139 EXPORT_SYMBOL(__udelay);
 140
 141 void __ndelay(unsigned long ns)
 142 {
 143         u64 cur, end, inc;
 144
 145         cur = read_c0_cvmcount();
 146
 147         inc = ((ns * octeon_ndelay_factor) >> 16);
 148         end = cur + inc;
 149
 150         while (end > cur)
 151                 cur = read_c0_cvmcount();
 152 }
 153 EXPORT_SYMBOL(__ndelay);
 154
 155 void __delay(unsigned long loops)
 156 {
 157         u64 cur, end;
 158
 159         cur = read_c0_cvmcount();
 160         end = cur + loops;
 161
 162         while (end > cur)
 163                 cur = read_c0_cvmcount();
 164 }
 165 EXPORT_SYMBOL(__delay);