| blob | 914074b91a8561ecf89fce5fa3316d17c0f9cf47 |
1 /*
2 * P5020/5010 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
35 &lbc {
36 compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
37 interrupts = <25 2 0 0>;
38 #address-cells = <2>;
39 #size-cells = <1>;
40 };
42 /* controller at 0x200000 */
43 &pci0 {
44 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0x0 0xff>;
49 clock-frequency = <33333333>;
50 interrupts = <16 2 1 15>;
51 pcie@0 {
52 reg = <0 0 0 0 0>;
53 #interrupt-cells = <1>;
54 #size-cells = <2>;
55 #address-cells = <3>;
56 device_type = "pci";
57 interrupts = <16 2 1 15>;
58 interrupt-map-mask = <0xf800 0 0 7>;
59 interrupt-map = <
60 /* IDSEL 0x0 */
61 0000 0 0 1 &mpic 40 1 0 0
62 0000 0 0 2 &mpic 1 1 0 0
63 0000 0 0 3 &mpic 2 1 0 0
64 0000 0 0 4 &mpic 3 1 0 0
65 >;
66 };
67 };
69 /* controller at 0x201000 */
70 &pci1 {
71 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
72 device_type = "pci";
73 #size-cells = <2>;
74 #address-cells = <3>;
75 bus-range = <0 0xff>;
76 clock-frequency = <33333333>;
77 interrupts = <16 2 1 14>;
78 pcie@0 {
79 reg = <0 0 0 0 0>;
80 #interrupt-cells = <1>;
81 #size-cells = <2>;
82 #address-cells = <3>;
83 device_type = "pci";
84 interrupts = <16 2 1 14>;
85 interrupt-map-mask = <0xf800 0 0 7>;
86 interrupt-map = <
87 /* IDSEL 0x0 */
88 0000 0 0 1 &mpic 41 1 0 0
89 0000 0 0 2 &mpic 5 1 0 0
90 0000 0 0 3 &mpic 6 1 0 0
91 0000 0 0 4 &mpic 7 1 0 0
92 >;
93 };
94 };
96 /* controller at 0x202000 */
97 &pci2 {
98 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
99 device_type = "pci";
100 #size-cells = <2>;
101 #address-cells = <3>;
102 bus-range = <0x0 0xff>;
103 clock-frequency = <33333333>;
104 interrupts = <16 2 1 13>;
105 pcie@0 {
106 reg = <0 0 0 0 0>;
107 #interrupt-cells = <1>;
108 #size-cells = <2>;
109 #address-cells = <3>;
110 device_type = "pci";
111 interrupts = <16 2 1 13>;
112 interrupt-map-mask = <0xf800 0 0 7>;
113 interrupt-map = <
114 /* IDSEL 0x0 */
115 0000 0 0 1 &mpic 42 1 0 0
116 0000 0 0 2 &mpic 9 1 0 0
117 0000 0 0 3 &mpic 10 1 0 0
118 0000 0 0 4 &mpic 11 1 0 0
119 >;
120 };
121 };
123 /* controller at 0x203000 */
124 &pci3 {
125 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
126 device_type = "pci";
127 #size-cells = <2>;
128 #address-cells = <3>;
129 bus-range = <0x0 0xff>;
130 clock-frequency = <33333333>;
131 interrupts = <16 2 1 12>;
132 pcie@0 {
133 reg = <0 0 0 0 0>;
134 #interrupt-cells = <1>;
135 #size-cells = <2>;
136 #address-cells = <3>;
137 device_type = "pci";
138 interrupts = <16 2 1 12>;
139 interrupt-map-mask = <0xf800 0 0 7>;
140 interrupt-map = <
141 /* IDSEL 0x0 */
142 0000 0 0 1 &mpic 43 1 0 0
143 0000 0 0 2 &mpic 0 1 0 0
144 0000 0 0 3 &mpic 4 1 0 0
145 0000 0 0 4 &mpic 8 1 0 0
146 >;
147 };
148 };
150 &rio {
151 compatible = "fsl,srio";
152 interrupts = <16 2 1 11>;
153 #address-cells = <2>;
154 #size-cells = <2>;
155 ranges;
157 port1 {
158 #address-cells = <2>;
159 #size-cells = <2>;
160 cell-index = <1>;
161 };
163 port2 {
164 #address-cells = <2>;
165 #size-cells = <2>;
166 cell-index = <2>;
167 };
168 };
170 &dcsr {
171 #address-cells = <1>;
172 #size-cells = <1>;
173 compatible = "fsl,dcsr", "simple-bus";
175 dcsr-epu@0 {
176 compatible = "fsl,dcsr-epu";
177 interrupts = <52 2 0 0
178 84 2 0 0
179 85 2 0 0>;
180 reg = <0x0 0x1000>;
181 };
182 dcsr-npc {
183 compatible = "fsl,dcsr-npc";
184 reg = <0x1000 0x1000 0x1000000 0x8000>;
185 };
186 dcsr-nxc@2000 {
187 compatible = "fsl,dcsr-nxc";
188 reg = <0x2000 0x1000>;
189 };
190 dcsr-corenet {
191 compatible = "fsl,dcsr-corenet";
192 reg = <0x8000 0x1000 0xB0000 0x1000>;
193 };
194 dcsr-dpaa@9000 {
195 compatible = "fsl,p5020-dcsr-dpaa", "fsl,dcsr-dpaa";
196 reg = <0x9000 0x1000>;
197 };
198 dcsr-ocn@11000 {
199 compatible = "fsl,p5020-dcsr-ocn", "fsl,dcsr-ocn";
200 reg = <0x11000 0x1000>;
201 };
202 dcsr-ddr@12000 {
203 compatible = "fsl,dcsr-ddr";
204 dev-handle = <&ddr1>;
205 reg = <0x12000 0x1000>;
206 };
207 dcsr-ddr@13000 {
208 compatible = "fsl,dcsr-ddr";
209 dev-handle = <&ddr2>;
210 reg = <0x13000 0x1000>;
211 };
212 dcsr-nal@18000 {
213 compatible = "fsl,p5020-dcsr-nal", "fsl,dcsr-nal";
214 reg = <0x18000 0x1000>;
215 };
216 dcsr-rcpm@22000 {
217 compatible = "fsl,p5020-dcsr-rcpm", "fsl,dcsr-rcpm";
218 reg = <0x22000 0x1000>;
219 };
220 dcsr-cpu-sb-proxy@40000 {
221 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
222 cpu-handle = <&cpu0>;
223 reg = <0x40000 0x1000>;
224 };
225 dcsr-cpu-sb-proxy@41000 {
226 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
227 cpu-handle = <&cpu1>;
228 reg = <0x41000 0x1000>;
229 };
230 };
232 &soc {
233 #address-cells = <1>;
234 #size-cells = <1>;
235 device_type = "soc";
236 compatible = "simple-bus";
238 soc-sram-error {
239 compatible = "fsl,soc-sram-error";
240 interrupts = <16 2 1 29>;
241 };
243 corenet-law@0 {
244 compatible = "fsl,corenet-law";
245 reg = <0x0 0x1000>;
246 fsl,num-laws = <32>;
247 };
249 ddr1: memory-controller@8000 {
250 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
251 reg = <0x8000 0x1000>;
252 interrupts = <16 2 1 23>;
253 };
255 ddr2: memory-controller@9000 {
256 compatible = "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller";
257 reg = <0x9000 0x1000>;
258 interrupts = <16 2 1 22>;
259 };
261 cpc: l3-cache-controller@10000 {
262 compatible = "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
263 reg = <0x10000 0x1000
264 0x11000 0x1000>;
265 interrupts = <16 2 1 27
266 16 2 1 26>;
267 };
269 corenet-cf@18000 {
270 compatible = "fsl,corenet-cf";
271 reg = <0x18000 0x1000>;
272 interrupts = <16 2 1 31>;
273 fsl,ccf-num-csdids = <32>;
274 fsl,ccf-num-snoopids = <32>;
275 };
277 iommu@20000 {
278 compatible = "fsl,pamu-v1.0", "fsl,pamu";
279 reg = <0x20000 0x4000>;
280 interrupts = <
281 24 2 0 0
282 16 2 1 30>;
283 };
285 /include/ "qoriq-mpic.dtsi"
287 guts: global-utilities@e0000 {
288 compatible = "fsl,qoriq-device-config-1.0";
289 reg = <0xe0000 0xe00>;
290 fsl,has-rstcr;
291 #sleep-cells = <1>;
292 fsl,liodn-bits = <12>;
293 };
295 pins: global-utilities@e0e00 {
296 compatible = "fsl,qoriq-pin-control-1.0";
297 reg = <0xe0e00 0x200>;
298 #sleep-cells = <2>;
299 };
301 clockgen: global-utilities@e1000 {
302 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
303 reg = <0xe1000 0x1000>;
304 clock-frequency = <0>;
305 };
307 rcpm: global-utilities@e2000 {
308 compatible = "fsl,qoriq-rcpm-1.0";
309 reg = <0xe2000 0x1000>;
310 #sleep-cells = <1>;
311 };
313 sfp: sfp@e8000 {
314 compatible = "fsl,p5020-sfp", "fsl,qoriq-sfp-1.0";
315 reg = <0xe8000 0x1000>;
316 };
318 serdes: serdes@ea000 {
319 compatible = "fsl,p5020-serdes";
320 reg = <0xea000 0x1000>;
321 };
323 /include/ "qoriq-dma-0.dtsi"
324 /include/ "qoriq-dma-1.dtsi"
325 /include/ "qoriq-espi-0.dtsi"
326 spi@110000 {
327 fsl,espi-num-chipselects = <4>;
328 };
330 /include/ "qoriq-esdhc-0.dtsi"
331 sdhc@114000 {
332 sdhci,auto-cmd12;
333 };
335 /include/ "qoriq-i2c-0.dtsi"
336 /include/ "qoriq-i2c-1.dtsi"
337 /include/ "qoriq-duart-0.dtsi"
338 /include/ "qoriq-duart-1.dtsi"
339 /include/ "qoriq-gpio-0.dtsi"
340 /include/ "qoriq-usb2-mph-0.dtsi"
341 usb0: usb@210000 {
342 phy_type = "utmi";
343 port0;
344 };
346 /include/ "qoriq-usb2-dr-0.dtsi"
347 usb1: usb@211000 {
348 dr_mode = "host";
349 phy_type = "utmi";
350 };
352 /include/ "qoriq-sata2-0.dtsi"
353 /include/ "qoriq-sata2-1.dtsi"
354 /include/ "qoriq-sec4.2-0.dtsi"
355 };