| blob | 5ab8932d09b7370aa9824131c5e74290874e823e |
1 /*
2 * GE SBC310 Device Tree Source
3 *
4 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * Based on: SBS CM6 Device Tree Source
12 * Copyright 2007 SBS Technologies GmbH & Co. KG
13 * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
14 * Copyright 2006 Freescale Semiconductor Inc.
15 */
17 /*
18 * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
19 */
21 /dts-v1/;
23 / {
24 model = "GEF_SBC310";
25 compatible = "gef,sbc310";
26 #address-cells = <1>;
27 #size-cells = <1>;
29 aliases {
30 ethernet0 = &enet0;
31 ethernet1 = &enet1;
32 serial0 = &serial0;
33 serial1 = &serial1;
34 pci0 = &pci0;
35 pci1 = &pci1;
36 };
38 cpus {
39 #address-cells = <1>;
40 #size-cells = <0>;
42 PowerPC,8641@0 {
43 device_type = "cpu";
44 reg = <0>;
45 d-cache-line-size = <32>; // 32 bytes
46 i-cache-line-size = <32>; // 32 bytes
47 d-cache-size = <32768>; // L1, 32K
48 i-cache-size = <32768>; // L1, 32K
49 timebase-frequency = <0>; // From uboot
50 bus-frequency = <0>; // From uboot
51 clock-frequency = <0>; // From uboot
52 };
53 PowerPC,8641@1 {
54 device_type = "cpu";
55 reg = <1>;
56 d-cache-line-size = <32>; // 32 bytes
57 i-cache-line-size = <32>; // 32 bytes
58 d-cache-size = <32768>; // L1, 32K
59 i-cache-size = <32768>; // L1, 32K
60 timebase-frequency = <0>; // From uboot
61 bus-frequency = <0>; // From uboot
62 clock-frequency = <0>; // From uboot
63 };
64 };
66 memory {
67 device_type = "memory";
68 reg = <0x0 0x40000000>; // set by uboot
69 };
71 localbus@fef05000 {
72 #address-cells = <2>;
73 #size-cells = <1>;
74 compatible = "fsl,mpc8641-localbus", "simple-bus";
75 reg = <0xfef05000 0x1000>;
76 interrupts = <19 2>;
77 interrupt-parent = <&mpic>;
79 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
80 1 0 0xe0000000 0x08000000 // Paged Flash 0
81 2 0 0xe8000000 0x08000000 // Paged Flash 1
82 3 0 0xfc100000 0x00020000 // NVRAM
83 4 0 0xfc000000 0x00010000>; // FPGA
85 /* flash@0,0 is a mirror of part of the memory in flash@1,0
86 flash@0,0 {
87 compatible = "gef,sbc310-firmware-mirror", "cfi-flash";
88 reg = <0x0 0x0 0x01000000>;
89 bank-width = <2>;
90 device-width = <2>;
91 #address-cells = <1>;
92 #size-cells = <1>;
93 partition@0 {
94 label = "firmware";
95 reg = <0x0 0x01000000>;
96 read-only;
97 };
98 };
99 */
101 flash@1,0 {
102 compatible = "gef,sbc310-paged-flash", "cfi-flash";
103 reg = <0x1 0x0 0x8000000>;
104 bank-width = <2>;
105 device-width = <2>;
106 #address-cells = <1>;
107 #size-cells = <1>;
108 partition@0 {
109 label = "user";
110 reg = <0x0 0x7800000>;
111 };
112 partition@7800000 {
113 label = "firmware";
114 reg = <0x7800000 0x800000>;
115 read-only;
116 };
117 };
119 nvram@3,0 {
120 device_type = "nvram";
121 compatible = "simtek,stk14ca8";
122 reg = <0x3 0x0 0x20000>;
123 };
125 fpga@4,0 {
126 compatible = "gef,fpga-regs";
127 reg = <0x4 0x0 0x40>;
128 };
130 wdt@4,2000 {
131 compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
132 "gef,fpga-wdt";
133 reg = <0x4 0x2000 0x8>;
134 interrupts = <0x1a 0x4>;
135 interrupt-parent = <&gef_pic>;
136 };
137 /*
138 wdt@4,2010 {
139 compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
140 "gef,fpga-wdt";
141 reg = <0x4 0x2010 0x8>;
142 interrupts = <0x1b 0x4>;
143 interrupt-parent = <&gef_pic>;
144 };
145 */
146 gef_pic: pic@4,4000 {
147 #interrupt-cells = <1>;
148 interrupt-controller;
149 compatible = "gef,sbc310-fpga-pic", "gef,fpga-pic";
150 reg = <0x4 0x4000 0x20>;
151 interrupts = <0x8
152 0x9>;
153 interrupt-parent = <&mpic>;
155 };
156 gef_gpio: gpio@4,8000 {
157 #gpio-cells = <2>;
158 compatible = "gef,sbc310-gpio";
159 reg = <0x4 0x8000 0x24>;
160 gpio-controller;
161 };
162 };
164 soc@fef00000 {
165 #address-cells = <1>;
166 #size-cells = <1>;
167 #interrupt-cells = <2>;
168 device_type = "soc";
169 compatible = "fsl,mpc8641-soc", "simple-bus";
170 ranges = <0x0 0xfef00000 0x00100000>;
171 bus-frequency = <33333333>;
173 mcm-law@0 {
174 compatible = "fsl,mcm-law";
175 reg = <0x0 0x1000>;
176 fsl,num-laws = <10>;
177 };
179 mcm@1000 {
180 compatible = "fsl,mpc8641-mcm", "fsl,mcm";
181 reg = <0x1000 0x1000>;
182 interrupts = <17 2>;
183 interrupt-parent = <&mpic>;
184 };
186 i2c1: i2c@3000 {
187 #address-cells = <1>;
188 #size-cells = <0>;
189 compatible = "fsl-i2c";
190 reg = <0x3000 0x100>;
191 interrupts = <0x2b 0x2>;
192 interrupt-parent = <&mpic>;
193 dfsrr;
195 rtc@51 {
196 compatible = "epson,rx8581";
197 reg = <0x00000051>;
198 };
199 };
201 i2c2: i2c@3100 {
202 #address-cells = <1>;
203 #size-cells = <0>;
204 compatible = "fsl-i2c";
205 reg = <0x3100 0x100>;
206 interrupts = <0x2b 0x2>;
207 interrupt-parent = <&mpic>;
208 dfsrr;
210 hwmon@48 {
211 compatible = "national,lm92";
212 reg = <0x48>;
213 };
215 hwmon@4c {
216 compatible = "adi,adt7461";
217 reg = <0x4c>;
218 };
220 eti@6b {
221 compatible = "dallas,ds1682";
222 reg = <0x6b>;
223 };
224 };
226 dma@21300 {
227 #address-cells = <1>;
228 #size-cells = <1>;
229 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
230 reg = <0x21300 0x4>;
231 ranges = <0x0 0x21100 0x200>;
232 cell-index = <0>;
233 dma-channel@0 {
234 compatible = "fsl,mpc8641-dma-channel",
235 "fsl,eloplus-dma-channel";
236 reg = <0x0 0x80>;
237 cell-index = <0>;
238 interrupt-parent = <&mpic>;
239 interrupts = <20 2>;
240 };
241 dma-channel@80 {
242 compatible = "fsl,mpc8641-dma-channel",
243 "fsl,eloplus-dma-channel";
244 reg = <0x80 0x80>;
245 cell-index = <1>;
246 interrupt-parent = <&mpic>;
247 interrupts = <21 2>;
248 };
249 dma-channel@100 {
250 compatible = "fsl,mpc8641-dma-channel",
251 "fsl,eloplus-dma-channel";
252 reg = <0x100 0x80>;
253 cell-index = <2>;
254 interrupt-parent = <&mpic>;
255 interrupts = <22 2>;
256 };
257 dma-channel@180 {
258 compatible = "fsl,mpc8641-dma-channel",
259 "fsl,eloplus-dma-channel";
260 reg = <0x180 0x80>;
261 cell-index = <3>;
262 interrupt-parent = <&mpic>;
263 interrupts = <23 2>;
264 };
265 };
267 enet0: ethernet@24000 {
268 #address-cells = <1>;
269 #size-cells = <1>;
270 cell-index = <0>;
271 device_type = "network";
272 model = "TSEC";
273 compatible = "gianfar";
274 reg = <0x24000 0x1000>;
275 ranges = <0x0 0x24000 0x1000>;
276 local-mac-address = [ 00 00 00 00 00 00 ];
277 interrupts = <29 2 30 2 34 2>;
278 interrupt-parent = <&mpic>;
279 tbi-handle = <&tbi0>;
280 phy-handle = <&phy0>;
281 phy-connection-type = "gmii";
283 mdio@520 {
284 #address-cells = <1>;
285 #size-cells = <0>;
286 compatible = "fsl,gianfar-mdio";
287 reg = <0x520 0x20>;
289 phy0: ethernet-phy@0 {
290 interrupt-parent = <&gef_pic>;
291 interrupts = <0x9 0x4>;
292 reg = <1>;
293 device_type = "ethernet-phy";
294 };
295 phy2: ethernet-phy@2 {
296 interrupt-parent = <&gef_pic>;
297 interrupts = <0x8 0x4>;
298 reg = <3>;
299 device_type = "ethernet-phy";
300 };
301 tbi0: tbi-phy@11 {
302 reg = <0x11>;
303 device_type = "tbi-phy";
304 };
305 };
306 };
308 enet1: ethernet@26000 {
309 #address-cells = <1>;
310 #size-cells = <1>;
311 cell-index = <2>;
312 device_type = "network";
313 model = "TSEC";
314 compatible = "gianfar";
315 reg = <0x26000 0x1000>;
316 ranges = <0x0 0x26000 0x1000>;
317 local-mac-address = [ 00 00 00 00 00 00 ];
318 interrupts = <31 2 32 2 33 2>;
319 interrupt-parent = <&mpic>;
320 tbi-handle = <&tbi2>;
321 phy-handle = <&phy2>;
322 phy-connection-type = "gmii";
324 mdio@520 {
325 #address-cells = <1>;
326 #size-cells = <0>;
327 compatible = "fsl,gianfar-tbi";
328 reg = <0x520 0x20>;
330 tbi2: tbi-phy@11 {
331 reg = <0x11>;
332 device_type = "tbi-phy";
333 };
334 };
335 };
337 serial0: serial@4500 {
338 cell-index = <0>;
339 device_type = "serial";
340 compatible = "fsl,ns16550", "ns16550";
341 reg = <0x4500 0x100>;
342 clock-frequency = <0>;
343 interrupts = <0x2a 0x2>;
344 interrupt-parent = <&mpic>;
345 };
347 serial1: serial@4600 {
348 cell-index = <1>;
349 device_type = "serial";
350 compatible = "fsl,ns16550", "ns16550";
351 reg = <0x4600 0x100>;
352 clock-frequency = <0>;
353 interrupts = <0x1c 0x2>;
354 interrupt-parent = <&mpic>;
355 };
357 mpic: pic@40000 {
358 clock-frequency = <0>;
359 interrupt-controller;
360 #address-cells = <0>;
361 #interrupt-cells = <2>;
362 reg = <0x40000 0x40000>;
363 compatible = "chrp,open-pic";
364 device_type = "open-pic";
365 };
367 msi@41600 {
368 compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
369 reg = <0x41600 0x80>;
370 msi-available-ranges = <0 0x100>;
371 interrupts = <
372 0xe0 0
373 0xe1 0
374 0xe2 0
375 0xe3 0
376 0xe4 0
377 0xe5 0
378 0xe6 0
379 0xe7 0>;
380 interrupt-parent = <&mpic>;
381 };
383 global-utilities@e0000 {
384 compatible = "fsl,mpc8641-guts";
385 reg = <0xe0000 0x1000>;
386 fsl,has-rstcr;
387 };
388 };
390 pci0: pcie@fef08000 {
391 compatible = "fsl,mpc8641-pcie";
392 device_type = "pci";
393 #interrupt-cells = <1>;
394 #size-cells = <2>;
395 #address-cells = <3>;
396 reg = <0xfef08000 0x1000>;
397 bus-range = <0x0 0xff>;
398 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
399 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
400 clock-frequency = <33333333>;
401 interrupt-parent = <&mpic>;
402 interrupts = <0x18 0x2>;
403 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
404 interrupt-map = <
405 0x0000 0x0 0x0 0x1 &mpic 0x0 0x2
406 0x0000 0x0 0x0 0x2 &mpic 0x1 0x2
407 0x0000 0x0 0x0 0x3 &mpic 0x2 0x2
408 0x0000 0x0 0x0 0x4 &mpic 0x3 0x2
409 >;
411 pcie@0 {
412 reg = <0 0 0 0 0>;
413 #size-cells = <2>;
414 #address-cells = <3>;
415 device_type = "pci";
416 ranges = <0x02000000 0x0 0x80000000
417 0x02000000 0x0 0x80000000
418 0x0 0x40000000
420 0x01000000 0x0 0x00000000
421 0x01000000 0x0 0x00000000
422 0x0 0x00400000>;
423 };
424 };
426 pci1: pcie@fef09000 {
427 compatible = "fsl,mpc8641-pcie";
428 device_type = "pci";
429 #interrupt-cells = <1>;
430 #size-cells = <2>;
431 #address-cells = <3>;
432 reg = <0xfef09000 0x1000>;
433 bus-range = <0x0 0xff>;
434 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
435 0x01000000 0x0 0x00000000 0xfe400000 0x0 0x00400000>;
436 clock-frequency = <33333333>;
437 interrupt-parent = <&mpic>;
438 interrupts = <0x19 0x2>;
439 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
440 interrupt-map = <
441 0x0000 0x0 0x0 0x1 &mpic 0x4 0x2
442 0x0000 0x0 0x0 0x2 &mpic 0x5 0x2
443 0x0000 0x0 0x0 0x3 &mpic 0x6 0x2
444 0x0000 0x0 0x0 0x4 &mpic 0x7 0x2
445 >;
447 pcie@0 {
448 reg = <0 0 0 0 0>;
449 #size-cells = <2>;
450 #address-cells = <3>;
451 device_type = "pci";
452 ranges = <0x02000000 0x0 0xc0000000
453 0x02000000 0x0 0xc0000000
454 0x0 0x20000000
456 0x01000000 0x0 0x00000000
457 0x01000000 0x0 0x00000000
458 0x0 0x00400000>;
459 };
460 };
461 };