arch/powerpc/boot/dts/mpc8572ds.dtsi

   1 /*
   2  * MPC8572DS Device Tree Source stub (no addresses or top-level ranges)
   3  *
   4  * Copyright 2011 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 &board_lbc {
  36         nor@0,0 {
  37                 #address-cells = <1>;
  38                 #size-cells = <1>;
  39                 compatible = "cfi-flash";
  40                 reg = <0x0 0x0 0x8000000>;
  41                 bank-width = <2>;
  42                 device-width = <1>;
  43
  44                 ramdisk@0 {
  45                         reg = <0x0 0x03000000>;
  46                         read-only;
  47                 };
  48
  49                 diagnostic@3000000 {
  50                         reg = <0x03000000 0x00e00000>;
  51                         read-only;
  52                 };
  53
  54                 dink@3e00000 {
  55                         reg = <0x03e00000 0x00200000>;
  56                         read-only;
  57                 };
  58
  59                 kernel@4000000 {
  60                         reg = <0x04000000 0x00400000>;
  61                         read-only;
  62                 };
  63
  64                 jffs2@4400000 {
  65                         reg = <0x04400000 0x03b00000>;
  66                 };
  67
  68                 dtb@7f00000 {
  69                         reg = <0x07f00000 0x00080000>;
  70                         read-only;
  71                 };
  72
  73                 u-boot@7f80000 {
  74                         reg = <0x07f80000 0x00080000>;
  75                         read-only;
  76                 };
  77         };
  78
  79         nand@2,0 {
  80                 #address-cells = <1>;
  81                 #size-cells = <1>;
  82                 compatible = "fsl,mpc8572-fcm-nand",
  83                              "fsl,elbc-fcm-nand";
  84                 reg = <0x2 0x0 0x40000>;
  85
  86                 u-boot@0 {
  87                         reg = <0x0 0x02000000>;
  88                         read-only;
  89                 };
  90
  91                 jffs2@2000000 {
  92                         reg = <0x02000000 0x10000000>;
  93                 };
  94
  95                 ramdisk@12000000 {
  96                         reg = <0x12000000 0x08000000>;
  97                         read-only;
  98                 };
  99
 100                 kernel@1a000000 {
 101                         reg = <0x1a000000 0x04000000>;
 102                 };
 103
 104                 dtb@1e000000 {
 105                         reg = <0x1e000000 0x01000000>;
 106                         read-only;
 107                 };
 108
 109                 empty@1f000000 {
 110                         reg = <0x1f000000 0x21000000>;
 111                 };
 112         };
 113
 114         nand@4,0 {
 115                 compatible = "fsl,mpc8572-fcm-nand",
 116                              "fsl,elbc-fcm-nand";
 117                 reg = <0x4 0x0 0x40000>;
 118         };
 119
 120         nand@5,0 {
 121                 compatible = "fsl,mpc8572-fcm-nand",
 122                              "fsl,elbc-fcm-nand";
 123                 reg = <0x5 0x0 0x40000>;
 124         };
 125
 126         nand@6,0 {
 127                 compatible = "fsl,mpc8572-fcm-nand",
 128                              "fsl,elbc-fcm-nand";
 129                 reg = <0x6 0x0 0x40000>;
 130         };
 131 };
 132
 133 &board_soc {
 134         enet0: ethernet@24000 {
 135                 tbi-handle = <&tbi0>;
 136                 phy-handle = <&phy0>;
 137                 phy-connection-type = "rgmii-id";
 138         };
 139
 140         mdio@24520 {
 141                 phy0: ethernet-phy@0 {
 142                         interrupts = <10 1 0 0>;
 143                         reg = <0x0>;
 144                 };
 145                 phy1: ethernet-phy@1 {
 146                         interrupts = <10 1 0 0>;
 147                         reg = <0x1>;
 148                 };
 149                 phy2: ethernet-phy@2 {
 150                         interrupts = <10 1 0 0>;
 151                         reg = <0x2>;
 152                 };
 153                 phy3: ethernet-phy@3 {
 154                         interrupts = <10 1 0 0>;
 155                         reg = <0x3>;
 156                 };
 157
 158                 tbi0: tbi-phy@11 {
 159                         reg = <0x11>;
 160                         device_type = "tbi-phy";
 161                 };
 162         };
 163
 164         ptp_clock@24e00 {
 165                 fsl,tclk-period = <5>;
 166                 fsl,tmr-prsc = <200>;
 167                 fsl,tmr-add = <0xAAAAAAAB>;
 168                 fsl,tmr-fiper1 = <0x3B9AC9FB>;
 169                 fsl,tmr-fiper2 = <0x3B9AC9FB>;
 170                 fsl,max-adj = <499999999>;
 171         };
 172
 173         enet1: ethernet@25000 {
 174                 tbi-handle = <&tbi1>;
 175                 phy-handle = <&phy1>;
 176                 phy-connection-type = "rgmii-id";
 177
 178         };
 179
 180         mdio@25520 {
 181                 tbi1: tbi-phy@11 {
 182                         reg = <0x11>;
 183                         device_type = "tbi-phy";
 184                 };
 185         };
 186
 187         enet2: ethernet@26000 {
 188                 tbi-handle = <&tbi2>;
 189                 phy-handle = <&phy2>;
 190                 phy-connection-type = "rgmii-id";
 191
 192         };
 193         mdio@26520 {
 194                 tbi2: tbi-phy@11 {
 195                         reg = <0x11>;
 196                         device_type = "tbi-phy";
 197                 };
 198         };
 199
 200         enet3: ethernet@27000 {
 201                 tbi-handle = <&tbi3>;
 202                 phy-handle = <&phy3>;
 203                 phy-connection-type = "rgmii-id";
 204         };
 205
 206         mdio@27520 {
 207                 tbi3: tbi-phy@11 {
 208                         reg = <0x11>;
 209                         device_type = "tbi-phy";
 210                 };
 211         };
 212 };
 213
 214 &board_pci0 {
 215         pcie@0 {
 216                 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
 217                 interrupt-map = <
 218                         /* IDSEL 0x11 func 0 - PCI slot 1 */
 219                         0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
 220                         0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
 221                         0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
 222                         0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
 223
 224                         /* IDSEL 0x11 func 1 - PCI slot 1 */
 225                         0x8900 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
 226                         0x8900 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
 227                         0x8900 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
 228                         0x8900 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
 229
 230                         /* IDSEL 0x11 func 2 - PCI slot 1 */
 231                         0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
 232                         0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
 233                         0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
 234                         0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
 235
 236                         /* IDSEL 0x11 func 3 - PCI slot 1 */
 237                         0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
 238                         0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
 239                         0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
 240                         0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
 241
 242                         /* IDSEL 0x11 func 4 - PCI slot 1 */
 243                         0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
 244                         0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
 245                         0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
 246                         0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
 247
 248                         /* IDSEL 0x11 func 5 - PCI slot 1 */
 249                         0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
 250                         0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
 251                         0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
 252                         0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
 253
 254                         /* IDSEL 0x11 func 6 - PCI slot 1 */
 255                         0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
 256                         0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
 257                         0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
 258                         0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
 259
 260                         /* IDSEL 0x11 func 7 - PCI slot 1 */
 261                         0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
 262                         0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
 263                         0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
 264                         0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
 265
 266                         /* IDSEL 0x12 func 0 - PCI slot 2 */
 267                         0x9000 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
 268                         0x9000 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
 269                         0x9000 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
 270                         0x9000 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
 271
 272                         /* IDSEL 0x12 func 1 - PCI slot 2 */
 273                         0x9100 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
 274                         0x9100 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
 275                         0x9100 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
 276                         0x9100 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
 277
 278                         /* IDSEL 0x12 func 2 - PCI slot 2 */
 279                         0x9200 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
 280                         0x9200 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
 281                         0x9200 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
 282                         0x9200 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
 283
 284                         /* IDSEL 0x12 func 3 - PCI slot 2 */
 285                         0x9300 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
 286                         0x9300 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
 287                         0x9300 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
 288                         0x9300 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
 289
 290                         /* IDSEL 0x12 func 4 - PCI slot 2 */
 291                         0x9400 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
 292                         0x9400 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
 293                         0x9400 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
 294                         0x9400 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
 295
 296                         /* IDSEL 0x12 func 5 - PCI slot 2 */
 297                         0x9500 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
 298                         0x9500 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
 299                         0x9500 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
 300                         0x9500 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
 301
 302                         /* IDSEL 0x12 func 6 - PCI slot 2 */
 303                         0x9600 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
 304                         0x9600 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
 305                         0x9600 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
 306                         0x9600 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
 307
 308                         /* IDSEL 0x12 func 7 - PCI slot 2 */
 309                         0x9700 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
 310                         0x9700 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
 311                         0x9700 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
 312                         0x9700 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
 313
 314                         // IDSEL 0x1c  USB
 315                         0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
 316                         0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
 317                         0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
 318                         0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
 319
 320                         // IDSEL 0x1d  Audio
 321                         0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
 322
 323                         // IDSEL 0x1e Legacy
 324                         0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
 325                         0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
 326
 327                         // IDSEL 0x1f IDE/SATA
 328                         0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
 329                         0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
 330                         >;
 331
 332
 333                 uli1575@0 {
 334                         reg = <0x0 0x0 0x0 0x0 0x0>;
 335                         #size-cells = <2>;
 336                         #address-cells = <3>;
 337                         ranges = <0x2000000 0x0 0x80000000
 338                                   0x2000000 0x0 0x80000000
 339                                   0x0 0x20000000
 340
 341                                   0x1000000 0x0 0x0
 342                                   0x1000000 0x0 0x0
 343                                   0x0 0x10000>;
 344                         isa@1e {
 345                                 device_type = "isa";
 346                                 #interrupt-cells = <2>;
 347                                 #size-cells = <1>;
 348                                 #address-cells = <2>;
 349                                 reg = <0xf000 0x0 0x0 0x0 0x0>;
 350                                 ranges = <0x1 0x0 0x1000000 0x0 0x0
 351                                           0x1000>;
 352                                 interrupt-parent = <&i8259>;
 353
 354                                 i8259: interrupt-controller@20 {
 355                                         reg = <0x1 0x20 0x2
 356                                                0x1 0xa0 0x2
 357                                                0x1 0x4d0 0x2>;
 358                                         interrupt-controller;
 359                                         device_type = "interrupt-controller";
 360                                         #address-cells = <0>;
 361                                         #interrupt-cells = <2>;
 362                                         compatible = "chrp,iic";
 363                                         interrupts = <9 2 0 0>;
 364                                         interrupt-parent = <&mpic>;
 365                                 };
 366
 367                                 i8042@60 {
 368                                         #size-cells = <0>;
 369                                         #address-cells = <1>;
 370                                         reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
 371                                         interrupts = <1 3 12 3>;
 372                                         interrupt-parent =
 373                                                 <&i8259>;
 374
 375                                         keyboard@0 {
 376                                                 reg = <0x0>;
 377                                                 compatible = "pnpPNP,303";
 378                                         };
 379
 380                                         mouse@1 {
 381                                                 reg = <0x1>;
 382                                                 compatible = "pnpPNP,f03";
 383                                         };
 384                                 };
 385
 386                                 rtc@70 {
 387                                         compatible = "pnpPNP,b00";
 388                                         reg = <0x1 0x70 0x2>;
 389                                 };
 390
 391                                 gpio@400 {
 392                                         reg = <0x1 0x400 0x80>;
 393                                 };
 394                         };
 395                 };
 396         };
 397 };