arch/powerpc/boot/dts/p2041rdb.dts

   1 /*
   2  * P2041RDB Device Tree Source
   3  *
   4  * Copyright 2011 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 /include/ "fsl/p2041si-pre.dtsi"
  36
  37 / {
  38         model = "fsl,P2041RDB";
  39         compatible = "fsl,P2041RDB";
  40         #address-cells = <2>;
  41         #size-cells = <2>;
  42         interrupt-parent = <&mpic>;
  43
  44         memory {
  45                 device_type = "memory";
  46         };
  47
  48         dcsr: dcsr@f00000000 {
  49                 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
  50         };
  51
  52         soc: soc@ffe000000 {
  53                 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  54                 reg = <0xf 0xfe000000 0 0x00001000>;
  55                 spi@110000 {
  56                         flash@0 {
  57                                 #address-cells = <1>;
  58                                 #size-cells = <1>;
  59                                 compatible = "spansion,s25sl12801";
  60                                 reg = <0>;
  61                                 spi-max-frequency = <40000000>; /* input clock */
  62                                 partition@u-boot {
  63                                         label = "u-boot";
  64                                         reg = <0x00000000 0x00100000>;
  65                                         read-only;
  66                                 };
  67                                 partition@kernel {
  68                                         label = "kernel";
  69                                         reg = <0x00100000 0x00500000>;
  70                                         read-only;
  71                                 };
  72                                 partition@dtb {
  73                                         label = "dtb";
  74                                         reg = <0x00600000 0x00100000>;
  75                                         read-only;
  76                                 };
  77                                 partition@fs {
  78                                         label = "file system";
  79                                         reg = <0x00700000 0x00900000>;
  80                                 };
  81                         };
  82                 };
  83
  84                 i2c@118000 {
  85                         lm75b@48 {
  86                                 compatible = "nxp,lm75a";
  87                                 reg = <0x48>;
  88                         };
  89                         eeprom@50 {
  90                                 compatible = "at24,24c256";
  91                                 reg = <0x50>;
  92                         };
  93                         rtc@68 {
  94                                 compatible = "pericom,pt7c4338";
  95                                 reg = <0x68>;
  96                         };
  97                 };
  98
  99                 i2c@118100 {
 100                         eeprom@50 {
 101                                 compatible = "at24,24c256";
 102                                 reg = <0x50>;
 103                         };
 104                 };
 105
 106                 usb1: usb@211000 {
 107                         dr_mode = "host";
 108                 };
 109         };
 110
 111         rio: rapidio@ffe0c0000 {
 112                 reg = <0xf 0xfe0c0000 0 0x11000>;
 113
 114                 port1 {
 115                         ranges = <0 0 0xc 0x20000000 0 0x10000000>;
 116                 };
 117                 port2 {
 118                         ranges = <0 0 0xc 0x30000000 0 0x10000000>;
 119                 };
 120         };
 121
 122         lbc: localbus@ffe124000 {
 123                 reg = <0xf 0xfe124000 0 0x1000>;
 124                 ranges = <0 0 0xf 0xe8000000 0x08000000>;
 125
 126                 flash@0,0 {
 127                         compatible = "cfi-flash";
 128                         reg = <0 0 0x08000000>;
 129                         bank-width = <2>;
 130                         device-width = <2>;
 131                 };
 132         };
 133
 134         pci0: pcie@ffe200000 {
 135                 reg = <0xf 0xfe200000 0 0x1000>;
 136                 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
 137                           0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
 138                 fsl,msi = <&msi0>;
 139                 pcie@0 {
 140                         ranges = <0x02000000 0 0xe0000000
 141                                   0x02000000 0 0xe0000000
 142                                   0 0x20000000
 143
 144                                   0x01000000 0 0x00000000
 145                                   0x01000000 0 0x00000000
 146                                   0 0x00010000>;
 147                 };
 148         };
 149
 150         pci1: pcie@ffe201000 {
 151                 reg = <0xf 0xfe201000 0 0x1000>;
 152                 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
 153                           0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
 154                 fsl,msi = <&msi1>;
 155                 pcie@0 {
 156                         ranges = <0x02000000 0 0xe0000000
 157                                   0x02000000 0 0xe0000000
 158                                   0 0x20000000
 159
 160                                   0x01000000 0 0x00000000
 161                                   0x01000000 0 0x00000000
 162                                   0 0x00010000>;
 163                 };
 164         };
 165
 166         pci2: pcie@ffe202000 {
 167                 reg = <0xf 0xfe202000 0 0x1000>;
 168                 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
 169                           0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
 170                 fsl,msi = <&msi2>;
 171                 pcie@0 {
 172                         ranges = <0x02000000 0 0xe0000000
 173                                   0x02000000 0 0xe0000000
 174                                   0 0x20000000
 175
 176                                   0x01000000 0 0x00000000
 177                                   0x01000000 0 0x00000000
 178                                   0 0x00010000>;
 179                 };
 180         };
 181 };
 182
 183 /include/ "fsl/p2041si-post.dtsi"