arch/powerpc/boot/dts/stxssa8555.dts

   1 /*
   2  * MPC8555-based STx GP3 Device Tree Source
   3  *
   4  * Copyright 2006, 2008 Freescale Semiconductor Inc.
   5  *
   6  * Copyright 2010 Silicon Turnkey Express LLC.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13
  14 /dts-v1/;
  15
  16 / {
  17         model = "stx,gp3";
  18         compatible = "stx,gp3-8560", "stx,gp3";
  19         #address-cells = <1>;
  20         #size-cells = <1>;
  21
  22         aliases {
  23                 ethernet0 = &enet0;
  24                 ethernet1 = &enet1;
  25                 serial0 = &serial0;
  26                 serial1 = &serial1;
  27                 pci0 = &pci0;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 PowerPC,8555@0 {
  35                         device_type = "cpu";
  36                         reg = <0x0>;
  37                         d-cache-line-size = <32>;       // 32 bytes
  38                         i-cache-line-size = <32>;       // 32 bytes
  39                         d-cache-size = <0x8000>;                // L1, 32K
  40                         i-cache-size = <0x8000>;                // L1, 32K
  41                         timebase-frequency = <0>;       //  33 MHz, from uboot
  42                         bus-frequency = <0>;    // 166 MHz
  43                         clock-frequency = <0>;  // 825 MHz, from uboot
  44                         next-level-cache = <&L2>;
  45                 };
  46         };
  47
  48         memory {
  49                 device_type = "memory";
  50                 reg = <0x00000000 0x10000000>;
  51         };
  52
  53         soc8555@e0000000 {
  54                 #address-cells = <1>;
  55                 #size-cells = <1>;
  56                 device_type = "soc";
  57                 compatible = "simple-bus";
  58                 ranges = <0x0 0xe0000000 0x100000>;
  59                 bus-frequency = <0>;
  60
  61                 ecm-law@0 {
  62                         compatible = "fsl,ecm-law";
  63                         reg = <0x0 0x1000>;
  64                         fsl,num-laws = <8>;
  65                 };
  66
  67                 ecm@1000 {
  68                         compatible = "fsl,mpc8555-ecm", "fsl,ecm";
  69                         reg = <0x1000 0x1000>;
  70                         interrupts = <17 2>;
  71                         interrupt-parent = <&mpic>;
  72                 };
  73
  74                 memory-controller@2000 {
  75                         compatible = "fsl,mpc8555-memory-controller";
  76                         reg = <0x2000 0x1000>;
  77                         interrupt-parent = <&mpic>;
  78                         interrupts = <18 2>;
  79                 };
  80
  81                 L2: l2-cache-controller@20000 {
  82                         compatible = "fsl,mpc8555-l2-cache-controller";
  83                         reg = <0x20000 0x1000>;
  84                         cache-line-size = <32>; // 32 bytes
  85                         cache-size = <0x40000>; // L2, 256K
  86                         interrupt-parent = <&mpic>;
  87                         interrupts = <16 2>;
  88                 };
  89
  90                 i2c@3000 {
  91                         #address-cells = <1>;
  92                         #size-cells = <0>;
  93                         cell-index = <0>;
  94                         compatible = "fsl-i2c";
  95                         reg = <0x3000 0x100>;
  96                         interrupts = <43 2>;
  97                         interrupt-parent = <&mpic>;
  98                         dfsrr;
  99                 };
 100
 101                 dma@21300 {
 102                         #address-cells = <1>;
 103                         #size-cells = <1>;
 104                         compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
 105                         reg = <0x21300 0x4>;
 106                         ranges = <0x0 0x21100 0x200>;
 107                         cell-index = <0>;
 108                         dma-channel@0 {
 109                                 compatible = "fsl,mpc8555-dma-channel",
 110                                                 "fsl,eloplus-dma-channel";
 111                                 reg = <0x0 0x80>;
 112                                 cell-index = <0>;
 113                                 interrupt-parent = <&mpic>;
 114                                 interrupts = <20 2>;
 115                         };
 116                         dma-channel@80 {
 117                                 compatible = "fsl,mpc8555-dma-channel",
 118                                                 "fsl,eloplus-dma-channel";
 119                                 reg = <0x80 0x80>;
 120                                 cell-index = <1>;
 121                                 interrupt-parent = <&mpic>;
 122                                 interrupts = <21 2>;
 123                         };
 124                         dma-channel@100 {
 125                                 compatible = "fsl,mpc8555-dma-channel",
 126                                                 "fsl,eloplus-dma-channel";
 127                                 reg = <0x100 0x80>;
 128                                 cell-index = <2>;
 129                                 interrupt-parent = <&mpic>;
 130                                 interrupts = <22 2>;
 131                         };
 132                         dma-channel@180 {
 133                                 compatible = "fsl,mpc8555-dma-channel",
 134                                                 "fsl,eloplus-dma-channel";
 135                                 reg = <0x180 0x80>;
 136                                 cell-index = <3>;
 137                                 interrupt-parent = <&mpic>;
 138                                 interrupts = <23 2>;
 139                         };
 140                 };
 141
 142                 enet0: ethernet@24000 {
 143                         #address-cells = <1>;
 144                         #size-cells = <1>;
 145                         cell-index = <0>;
 146                         device_type = "network";
 147                         model = "TSEC";
 148                         compatible = "gianfar";
 149                         reg = <0x24000 0x1000>;
 150                         ranges = <0x0 0x24000 0x1000>;
 151                         local-mac-address = [ 00 00 00 00 00 00 ];
 152                         interrupts = <29 2 30 2 34 2>;
 153                         interrupt-parent = <&mpic>;
 154                         tbi-handle = <&tbi0>;
 155                         phy-handle = <&phy0>;
 156
 157                         mdio@520 {
 158                                 #address-cells = <1>;
 159                                 #size-cells = <0>;
 160                                 compatible = "fsl,gianfar-mdio";
 161                                 reg = <0x520 0x20>;
 162
 163                                 phy0: ethernet-phy@2 {
 164                                         interrupt-parent = <&mpic>;
 165                                         interrupts = <5 1>;
 166                                         reg = <0x2>;
 167                                         device_type = "ethernet-phy";
 168                                 };
 169                                 phy1: ethernet-phy@4 {
 170                                         interrupt-parent = <&mpic>;
 171                                         interrupts = <5 1>;
 172                                         reg = <0x4>;
 173                                         device_type = "ethernet-phy";
 174                                 };
 175                                 tbi0: tbi-phy@11 {
 176                                         reg = <0x11>;
 177                                         device_type = "tbi-phy";
 178                                 };
 179                         };
 180                 };
 181
 182                 enet1: ethernet@25000 {
 183                         #address-cells = <1>;
 184                         #size-cells = <1>;
 185                         cell-index = <1>;
 186                         device_type = "network";
 187                         model = "TSEC";
 188                         compatible = "gianfar";
 189                         reg = <0x25000 0x1000>;
 190                         ranges = <0x0 0x25000 0x1000>;
 191                         local-mac-address = [ 00 00 00 00 00 00 ];
 192                         interrupts = <35 2 36 2 40 2>;
 193                         interrupt-parent = <&mpic>;
 194                         tbi-handle = <&tbi1>;
 195                         phy-handle = <&phy1>;
 196
 197                         mdio@520 {
 198                                 #address-cells = <1>;
 199                                 #size-cells = <0>;
 200                                 compatible = "fsl,gianfar-tbi";
 201                                 reg = <0x520 0x20>;
 202
 203                                 tbi1: tbi-phy@11 {
 204                                         reg = <0x11>;
 205                                         device_type = "tbi-phy";
 206                                 };
 207                         };
 208                 };
 209
 210                 serial0: serial@4500 {
 211                         cell-index = <0>;
 212                         device_type = "serial";
 213                         compatible = "fsl,ns16550", "ns16550";
 214                         reg = <0x4500 0x100>;   // reg base, size
 215                         clock-frequency = <0>;  // should we fill in in uboot?
 216                         interrupts = <42 2>;
 217                         interrupt-parent = <&mpic>;
 218                 };
 219
 220                 serial1: serial@4600 {
 221                         cell-index = <1>;
 222                         device_type = "serial";
 223                         compatible = "fsl,ns16550", "ns16550";
 224                         reg = <0x4600 0x100>;   // reg base, size
 225                         clock-frequency = <0>;  // should we fill in in uboot?
 226                         interrupts = <42 2>;
 227                         interrupt-parent = <&mpic>;
 228                 };
 229
 230                 crypto@30000 {
 231                         compatible = "fsl,sec2.0";
 232                         reg = <0x30000 0x10000>;
 233                         interrupts = <45 2>;
 234                         interrupt-parent = <&mpic>;
 235                         fsl,num-channels = <4>;
 236                         fsl,channel-fifo-len = <24>;
 237                         fsl,exec-units-mask = <0x7e>;
 238                         fsl,descriptor-types-mask = <0x01010ebf>;
 239                 };
 240
 241                 mpic: pic@40000 {
 242                         interrupt-controller;
 243                         #address-cells = <0>;
 244                         #interrupt-cells = <2>;
 245                         reg = <0x40000 0x40000>;
 246                         compatible = "chrp,open-pic";
 247                         device_type = "open-pic";
 248                 };
 249
 250                 cpm@919c0 {
 251                         #address-cells = <1>;
 252                         #size-cells = <1>;
 253                         compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
 254                         reg = <0x919c0 0x30>;
 255                         ranges;
 256
 257                         muram@80000 {
 258                                 #address-cells = <1>;
 259                                 #size-cells = <1>;
 260                                 ranges = <0x0 0x80000 0x10000>;
 261
 262                                 data@0 {
 263                                         compatible = "fsl,cpm-muram-data";
 264                                         reg = <0x0 0x2000 0x9000 0x1000>;
 265                                 };
 266                         };
 267
 268                         brg@919f0 {
 269                                 compatible = "fsl,mpc8555-brg",
 270                                              "fsl,cpm2-brg",
 271                                              "fsl,cpm-brg";
 272                                 reg = <0x919f0 0x10 0x915f0 0x10>;
 273                         };
 274
 275                         cpmpic: pic@90c00 {
 276                                 interrupt-controller;
 277                                 #address-cells = <0>;
 278                                 #interrupt-cells = <2>;
 279                                 interrupts = <46 2>;
 280                                 interrupt-parent = <&mpic>;
 281                                 reg = <0x90c00 0x80>;
 282                                 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
 283                         };
 284                 };
 285         };
 286
 287         pci0: pci@e0008000 {
 288                 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
 289                 interrupt-map = <
 290
 291                         /* IDSEL 0x10 */
 292                         0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
 293                         0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
 294                         0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
 295                         0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
 296
 297                         /* IDSEL 0x11 */
 298                         0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
 299                         0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
 300                         0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
 301                         0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
 302
 303                         /* IDSEL 0x12 (Slot 1) */
 304                         0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
 305                         0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
 306                         0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
 307                         0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
 308
 309                         /* IDSEL 0x13 (Slot 2) */
 310                         0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
 311                         0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
 312                         0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
 313                         0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
 314
 315                         /* IDSEL 0x14 (Slot 3) */
 316                         0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
 317                         0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
 318                         0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
 319                         0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
 320
 321                         /* IDSEL 0x15 (Slot 4) */
 322                         0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
 323                         0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
 324                         0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
 325                         0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
 326
 327                         /* Bus 1 (Tundra Bridge) */
 328                         /* IDSEL 0x12 (ISA bridge) */
 329                         0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
 330                         0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
 331                         0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
 332                         0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 333                 interrupt-parent = <&mpic>;
 334                 interrupts = <24 2>;
 335                 bus-range = <0 0>;
 336                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
 337                           0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
 338                 clock-frequency = <66666666>;
 339                 #interrupt-cells = <1>;
 340                 #size-cells = <2>;
 341                 #address-cells = <3>;
 342                 reg = <0xe0008000 0x1000>;
 343                 compatible = "fsl,mpc8540-pci";
 344                 device_type = "pci";
 345
 346                 i8259@19000 {
 347                         interrupt-controller;
 348                         device_type = "interrupt-controller";
 349                         reg = <0x19000 0x0 0x0 0x0 0x1>;
 350                         #address-cells = <0>;
 351                         #interrupt-cells = <2>;
 352                         compatible = "chrp,iic";
 353                         interrupts = <1>;
 354                         interrupt-parent = <&pci0>;
 355                 };
 356         };
 357
 358         pci1: pci@e0009000 {
 359                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 360                 interrupt-map = <
 361
 362                         /* IDSEL 0x15 */
 363                         0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
 364                         0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
 365                         0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
 366                         0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
 367                 interrupt-parent = <&mpic>;
 368                 interrupts = <25 2>;
 369                 bus-range = <0 0>;
 370                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
 371                           0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
 372                 clock-frequency = <66666666>;
 373                 #interrupt-cells = <1>;
 374                 #size-cells = <2>;
 375                 #address-cells = <3>;
 376                 reg = <0xe0009000 0x1000>;
 377                 compatible = "fsl,mpc8540-pci";
 378                 device_type = "pci";
 379         };
 380 };