arch/powerpc/platforms/85xx/mpc85xx_cds.c

   1 /*
   2  * MPC85xx setup and early boot code plus other random bits.
   3  *
   4  * Maintained by Kumar Gala (see MAINTAINERS for contact information)
   5  *
   6  * Copyright 2005 Freescale Semiconductor Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13
  14 #include <linux/stddef.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/reboot.h>
  19 #include <linux/pci.h>
  20 #include <linux/kdev_t.h>
  21 #include <linux/major.h>
  22 #include <linux/console.h>
  23 #include <linux/delay.h>
  24 #include <linux/seq_file.h>
  25 #include <linux/initrd.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/fsl_devices.h>
  28 #include <linux/of_platform.h>
  29
  30 #include <asm/system.h>
  31 #include <asm/pgtable.h>
  32 #include <asm/page.h>
  33 #include <linux/atomic.h>
  34 #include <asm/time.h>
  35 #include <asm/io.h>
  36 #include <asm/machdep.h>
  37 #include <asm/ipic.h>
  38 #include <asm/pci-bridge.h>
  39 #include <asm/irq.h>
  40 #include <mm/mmu_decl.h>
  41 #include <asm/prom.h>
  42 #include <asm/udbg.h>
  43 #include <asm/mpic.h>
  44 #include <asm/i8259.h>
  45
  46 #include <sysdev/fsl_soc.h>
  47 #include <sysdev/fsl_pci.h>
  48
  49 #include "mpc85xx.h"
  50
  51 /* CADMUS info */
  52 /* xxx - galak, move into device tree */
  53 #define CADMUS_BASE (0xf8004000)
  54 #define CADMUS_SIZE (256)
  55 #define CM_VER  (0)
  56 #define CM_CSR  (1)
  57 #define CM_RST  (2)
  58
  59
  60 static int cds_pci_slot = 2;
  61 static volatile u8 *cadmus;
  62
  63 #ifdef CONFIG_PCI
  64
  65 #define ARCADIA_HOST_BRIDGE_IDSEL       17
  66 #define ARCADIA_2ND_BRIDGE_IDSEL        3
  67
  68 static int mpc85xx_exclude_device(struct pci_controller *hose,
  69                                   u_char bus, u_char devfn)
  70 {
  71         /* We explicitly do not go past the Tundra 320 Bridge */
  72         if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
  73                 return PCIBIOS_DEVICE_NOT_FOUND;
  74         if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
  75                 return PCIBIOS_DEVICE_NOT_FOUND;
  76         else
  77                 return PCIBIOS_SUCCESSFUL;
  78 }
  79
  80 static void mpc85xx_cds_restart(char *cmd)
  81 {
  82         struct pci_dev *dev;
  83         u_char tmp;
  84
  85         if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686,
  86                                         NULL))) {
  87
  88                 /* Use the VIA Super Southbridge to force a PCI reset */
  89                 pci_read_config_byte(dev, 0x47, &tmp);
  90                 pci_write_config_byte(dev, 0x47, tmp | 1);
  91
  92                 /* Flush the outbound PCI write queues */
  93                 pci_read_config_byte(dev, 0x47, &tmp);
  94
  95                 /*
  96                  *  At this point, the harware reset should have triggered.
  97                  *  However, if it doesn't work for some mysterious reason,
  98                  *  just fall through to the default reset below.
  99                  */
 100
 101                 pci_dev_put(dev);
 102         }
 103
 104         /*
 105          *  If we can't find the VIA chip (maybe the P2P bridge is disabled)
 106          *  or the VIA chip reset didn't work, just use the default reset.
 107          */
 108         fsl_rstcr_restart(NULL);
 109 }
 110
 111 static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
 112 {
 113         u_char c;
 114         if (dev->vendor == PCI_VENDOR_ID_VIA) {
 115                 switch (dev->device) {
 116                 case PCI_DEVICE_ID_VIA_82C586_1:
 117                         /*
 118                          * U-Boot does not set the enable bits
 119                          * for the IDE device. Force them on here.
 120                          */
 121                         pci_read_config_byte(dev, 0x40, &c);
 122                         c |= 0x03; /* IDE: Chip Enable Bits */
 123                         pci_write_config_byte(dev, 0x40, c);
 124
 125                         /*
 126                          * Since only primary interface works, force the
 127                          * IDE function to standard primary IDE interrupt
 128                          * w/ 8259 offset
 129                          */
 130                         dev->irq = 14;
 131                         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 132                         break;
 133                 /*
 134                  * Force legacy USB interrupt routing
 135                  */
 136                 case PCI_DEVICE_ID_VIA_82C586_2:
 137                 /* There are two USB controllers.
 138                  * Identify them by functon number
 139                  */
 140                         if (PCI_FUNC(dev->devfn) == 3)
 141                                 dev->irq = 11;
 142                         else
 143                                 dev->irq = 10;
 144                         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 145                 default:
 146                         break;
 147                 }
 148         }
 149 }
 150
 151 static void __devinit skip_fake_bridge(struct pci_dev *dev)
 152 {
 153         /* Make it an error to skip the fake bridge
 154          * in pci_setup_device() in probe.c */
 155         dev->hdr_type = 0x7f;
 156 }
 157 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x3fff, skip_fake_bridge);
 158 DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge);
 159 DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge);
 160
 161 #ifdef CONFIG_PPC_I8259
 162 static void mpc85xx_8259_cascade_handler(unsigned int irq,
 163                                          struct irq_desc *desc)
 164 {
 165         unsigned int cascade_irq = i8259_irq();
 166
 167         if (cascade_irq != NO_IRQ)
 168                 /* handle an interrupt from the 8259 */
 169                 generic_handle_irq(cascade_irq);
 170
 171         /* check for any interrupts from the shared IRQ line */
 172         handle_fasteoi_irq(irq, desc);
 173 }
 174
 175 static irqreturn_t mpc85xx_8259_cascade_action(int irq, void *dev_id)
 176 {
 177         return IRQ_HANDLED;
 178 }
 179
 180 static struct irqaction mpc85xxcds_8259_irqaction = {
 181         .handler = mpc85xx_8259_cascade_action,
 182         .flags = IRQF_SHARED | IRQF_NO_THREAD,
 183         .name = "8259 cascade",
 184 };
 185 #endif /* PPC_I8259 */
 186 #endif /* CONFIG_PCI */
 187
 188 static void __init mpc85xx_cds_pic_init(void)
 189 {
 190         struct mpic *mpic;
 191         mpic = mpic_alloc(NULL, 0,
 192                         MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
 193                         0, 256, " OpenPIC  ");
 194         BUG_ON(mpic == NULL);
 195         mpic_init(mpic);
 196 }
 197
 198 #if defined(CONFIG_PPC_I8259) && defined(CONFIG_PCI)
 199 static int mpc85xx_cds_8259_attach(void)
 200 {
 201         int ret;
 202         struct device_node *np = NULL;
 203         struct device_node *cascade_node = NULL;
 204         int cascade_irq;
 205
 206         /* Initialize the i8259 controller */
 207         for_each_node_by_type(np, "interrupt-controller")
 208                 if (of_device_is_compatible(np, "chrp,iic")) {
 209                         cascade_node = np;
 210                         break;
 211                 }
 212
 213         if (cascade_node == NULL) {
 214                 printk(KERN_DEBUG "Could not find i8259 PIC\n");
 215                 return -ENODEV;
 216         }
 217
 218         cascade_irq = irq_of_parse_and_map(cascade_node, 0);
 219         if (cascade_irq == NO_IRQ) {
 220                 printk(KERN_ERR "Failed to map cascade interrupt\n");
 221                 return -ENXIO;
 222         }
 223
 224         i8259_init(cascade_node, 0);
 225         of_node_put(cascade_node);
 226
 227         /*
 228          *  Hook the interrupt to make sure desc->action is never NULL.
 229          *  This is required to ensure that the interrupt does not get
 230          *  disabled when the last user of the shared IRQ line frees their
 231          *  interrupt.
 232          */
 233         if ((ret = setup_irq(cascade_irq, &mpc85xxcds_8259_irqaction))) {
 234                 printk(KERN_ERR "Failed to setup cascade interrupt\n");
 235                 return ret;
 236         }
 237
 238         /* Success. Connect our low-level cascade handler. */
 239         irq_set_handler(cascade_irq, mpc85xx_8259_cascade_handler);
 240
 241         return 0;
 242 }
 243 machine_device_initcall(mpc85xx_cds, mpc85xx_cds_8259_attach);
 244
 245 #endif /* CONFIG_PPC_I8259 */
 246
 247 /*
 248  * Setup the architecture
 249  */
 250 static void __init mpc85xx_cds_setup_arch(void)
 251 {
 252 #ifdef CONFIG_PCI
 253         struct device_node *np;
 254 #endif
 255
 256         if (ppc_md.progress)
 257                 ppc_md.progress("mpc85xx_cds_setup_arch()", 0);
 258
 259         cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
 260         cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
 261
 262         if (ppc_md.progress) {
 263                 char buf[40];
 264                 snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n",
 265                                 cadmus[CM_VER], cds_pci_slot);
 266                 ppc_md.progress(buf, 0);
 267         }
 268
 269 #ifdef CONFIG_PCI
 270         for_each_node_by_type(np, "pci") {
 271                 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
 272                     of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
 273                         struct resource rsrc;
 274                         of_address_to_resource(np, 0, &rsrc);
 275                         if ((rsrc.start & 0xfffff) == 0x8000)
 276                                 fsl_add_bridge(np, 1);
 277                         else
 278                                 fsl_add_bridge(np, 0);
 279                 }
 280         }
 281
 282         ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup;
 283         ppc_md.pci_exclude_device = mpc85xx_exclude_device;
 284 #endif
 285 }
 286
 287 static void mpc85xx_cds_show_cpuinfo(struct seq_file *m)
 288 {
 289         uint pvid, svid, phid1;
 290
 291         pvid = mfspr(SPRN_PVR);
 292         svid = mfspr(SPRN_SVR);
 293
 294         seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
 295         seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n", cadmus[CM_VER]);
 296         seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
 297         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 298
 299         /* Display cpu Pll setting */
 300         phid1 = mfspr(SPRN_HID1);
 301         seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 302 }
 303
 304
 305 /*
 306  * Called very early, device-tree isn't unflattened
 307  */
 308 static int __init mpc85xx_cds_probe(void)
 309 {
 310         unsigned long root = of_get_flat_dt_root();
 311
 312         return of_flat_dt_is_compatible(root, "MPC85xxCDS");
 313 }
 314
 315 machine_device_initcall(mpc85xx_cds, mpc85xx_common_publish_devices);
 316
 317 define_machine(mpc85xx_cds) {
 318         .name           = "MPC85xx CDS",
 319         .probe          = mpc85xx_cds_probe,
 320         .setup_arch     = mpc85xx_cds_setup_arch,
 321         .init_IRQ       = mpc85xx_cds_pic_init,
 322         .show_cpuinfo   = mpc85xx_cds_show_cpuinfo,
 323         .get_irq        = mpic_get_irq,
 324 #ifdef CONFIG_PCI
 325         .restart        = mpc85xx_cds_restart,
 326         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 327 #else
 328         .restart        = fsl_rstcr_restart,
 329 #endif
 330         .calibrate_decr = generic_calibrate_decr,
 331         .progress       = udbg_progress,
 332 };