arch/sh/kernel/cpu/sh4a/setup-sh7366.c

   1 /*
   2  * SH7366 Setup
   3  *
   4  *  Copyright (C) 2008 Renesas Solutions
   5  *
   6  * Based on linux/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12 #include <linux/platform_device.h>
  13 #include <linux/init.h>
  14 #include <linux/serial.h>
  15 #include <linux/serial_sci.h>
  16 #include <linux/uio_driver.h>
  17 #include <linux/sh_timer.h>
  18 #include <linux/usb/r8a66597.h>
  19 #include <asm/clock.h>
  20
  21 static struct plat_sci_port scif0_platform_data = {
  22         .mapbase        = 0xffe00000,
  23         .port_reg       = 0xa405013e,
  24         .flags          = UPF_BOOT_AUTOCONF,
  25         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  26         .scbrr_algo_id  = SCBRR_ALGO_2,
  27         .type           = PORT_SCIF,
  28         .irqs           = { 80, 80, 80, 80 },
  29 };
  30
  31 static struct platform_device scif0_device = {
  32         .name           = "sh-sci",
  33         .id             = 0,
  34         .dev            = {
  35                 .platform_data  = &scif0_platform_data,
  36         },
  37 };
  38
  39 static struct resource iic_resources[] = {
  40         [0] = {
  41                 .name   = "IIC",
  42                 .start  = 0x04470000,
  43                 .end    = 0x04470017,
  44                 .flags  = IORESOURCE_MEM,
  45         },
  46         [1] = {
  47                 .start  = 96,
  48                 .end    = 99,
  49                 .flags  = IORESOURCE_IRQ,
  50        },
  51 };
  52
  53 static struct platform_device iic_device = {
  54         .name           = "i2c-sh_mobile",
  55         .id             = 0, /* "i2c0" clock */
  56         .num_resources  = ARRAY_SIZE(iic_resources),
  57         .resource       = iic_resources,
  58 };
  59
  60 static struct r8a66597_platdata r8a66597_data = {
  61         .on_chip = 1,
  62 };
  63
  64 static struct resource usb_host_resources[] = {
  65         [0] = {
  66                 .start  = 0xa4d80000,
  67                 .end    = 0xa4d800ff,
  68                 .flags  = IORESOURCE_MEM,
  69         },
  70         [1] = {
  71                 .start  = 65,
  72                 .end    = 65,
  73                 .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
  74         },
  75 };
  76
  77 static struct platform_device usb_host_device = {
  78         .name   = "r8a66597_hcd",
  79         .id     = -1,
  80         .dev = {
  81                 .dma_mask               = NULL,
  82                 .coherent_dma_mask      = 0xffffffff,
  83                 .platform_data          = &r8a66597_data,
  84         },
  85         .num_resources  = ARRAY_SIZE(usb_host_resources),
  86         .resource       = usb_host_resources,
  87 };
  88
  89 static struct uio_info vpu_platform_data = {
  90         .name = "VPU5",
  91         .version = "0",
  92         .irq = 60,
  93 };
  94
  95 static struct resource vpu_resources[] = {
  96         [0] = {
  97                 .name   = "VPU",
  98                 .start  = 0xfe900000,
  99                 .end    = 0xfe902807,
 100                 .flags  = IORESOURCE_MEM,
 101         },
 102         [1] = {
 103                 /* place holder for contiguous memory */
 104         },
 105 };
 106
 107 static struct platform_device vpu_device = {
 108         .name           = "uio_pdrv_genirq",
 109         .id             = 0,
 110         .dev = {
 111                 .platform_data  = &vpu_platform_data,
 112         },
 113         .resource       = vpu_resources,
 114         .num_resources  = ARRAY_SIZE(vpu_resources),
 115 };
 116
 117 static struct uio_info veu0_platform_data = {
 118         .name = "VEU",
 119         .version = "0",
 120         .irq = 54,
 121 };
 122
 123 static struct resource veu0_resources[] = {
 124         [0] = {
 125                 .name   = "VEU(1)",
 126                 .start  = 0xfe920000,
 127                 .end    = 0xfe9200b7,
 128                 .flags  = IORESOURCE_MEM,
 129         },
 130         [1] = {
 131                 /* place holder for contiguous memory */
 132         },
 133 };
 134
 135 static struct platform_device veu0_device = {
 136         .name           = "uio_pdrv_genirq",
 137         .id             = 1,
 138         .dev = {
 139                 .platform_data  = &veu0_platform_data,
 140         },
 141         .resource       = veu0_resources,
 142         .num_resources  = ARRAY_SIZE(veu0_resources),
 143 };
 144
 145 static struct uio_info veu1_platform_data = {
 146         .name = "VEU",
 147         .version = "0",
 148         .irq = 27,
 149 };
 150
 151 static struct resource veu1_resources[] = {
 152         [0] = {
 153                 .name   = "VEU(2)",
 154                 .start  = 0xfe924000,
 155                 .end    = 0xfe9240b7,
 156                 .flags  = IORESOURCE_MEM,
 157         },
 158         [1] = {
 159                 /* place holder for contiguous memory */
 160         },
 161 };
 162
 163 static struct platform_device veu1_device = {
 164         .name           = "uio_pdrv_genirq",
 165         .id             = 2,
 166         .dev = {
 167                 .platform_data  = &veu1_platform_data,
 168         },
 169         .resource       = veu1_resources,
 170         .num_resources  = ARRAY_SIZE(veu1_resources),
 171 };
 172
 173 static struct sh_timer_config cmt_platform_data = {
 174         .channel_offset = 0x60,
 175         .timer_bit = 5,
 176         .clockevent_rating = 125,
 177         .clocksource_rating = 200,
 178 };
 179
 180 static struct resource cmt_resources[] = {
 181         [0] = {
 182                 .start  = 0x044a0060,
 183                 .end    = 0x044a006b,
 184                 .flags  = IORESOURCE_MEM,
 185         },
 186         [1] = {
 187                 .start  = 104,
 188                 .flags  = IORESOURCE_IRQ,
 189         },
 190 };
 191
 192 static struct platform_device cmt_device = {
 193         .name           = "sh_cmt",
 194         .id             = 0,
 195         .dev = {
 196                 .platform_data  = &cmt_platform_data,
 197         },
 198         .resource       = cmt_resources,
 199         .num_resources  = ARRAY_SIZE(cmt_resources),
 200 };
 201
 202 static struct sh_timer_config tmu0_platform_data = {
 203         .channel_offset = 0x04,
 204         .timer_bit = 0,
 205         .clockevent_rating = 200,
 206 };
 207
 208 static struct resource tmu0_resources[] = {
 209         [0] = {
 210                 .start  = 0xffd80008,
 211                 .end    = 0xffd80013,
 212                 .flags  = IORESOURCE_MEM,
 213         },
 214         [1] = {
 215                 .start  = 16,
 216                 .flags  = IORESOURCE_IRQ,
 217         },
 218 };
 219
 220 static struct platform_device tmu0_device = {
 221         .name           = "sh_tmu",
 222         .id             = 0,
 223         .dev = {
 224                 .platform_data  = &tmu0_platform_data,
 225         },
 226         .resource       = tmu0_resources,
 227         .num_resources  = ARRAY_SIZE(tmu0_resources),
 228 };
 229
 230 static struct sh_timer_config tmu1_platform_data = {
 231         .channel_offset = 0x10,
 232         .timer_bit = 1,
 233         .clocksource_rating = 200,
 234 };
 235
 236 static struct resource tmu1_resources[] = {
 237         [0] = {
 238                 .start  = 0xffd80014,
 239                 .end    = 0xffd8001f,
 240                 .flags  = IORESOURCE_MEM,
 241         },
 242         [1] = {
 243                 .start  = 17,
 244                 .flags  = IORESOURCE_IRQ,
 245         },
 246 };
 247
 248 static struct platform_device tmu1_device = {
 249         .name           = "sh_tmu",
 250         .id             = 1,
 251         .dev = {
 252                 .platform_data  = &tmu1_platform_data,
 253         },
 254         .resource       = tmu1_resources,
 255         .num_resources  = ARRAY_SIZE(tmu1_resources),
 256 };
 257
 258 static struct sh_timer_config tmu2_platform_data = {
 259         .channel_offset = 0x1c,
 260         .timer_bit = 2,
 261 };
 262
 263 static struct resource tmu2_resources[] = {
 264         [0] = {
 265                 .start  = 0xffd80020,
 266                 .end    = 0xffd8002b,
 267                 .flags  = IORESOURCE_MEM,
 268         },
 269         [1] = {
 270                 .start  = 18,
 271                 .flags  = IORESOURCE_IRQ,
 272         },
 273 };
 274
 275 static struct platform_device tmu2_device = {
 276         .name           = "sh_tmu",
 277         .id             = 2,
 278         .dev = {
 279                 .platform_data  = &tmu2_platform_data,
 280         },
 281         .resource       = tmu2_resources,
 282         .num_resources  = ARRAY_SIZE(tmu2_resources),
 283 };
 284
 285 static struct platform_device *sh7366_devices[] __initdata = {
 286         &scif0_device,
 287         &cmt_device,
 288         &tmu0_device,
 289         &tmu1_device,
 290         &tmu2_device,
 291         &iic_device,
 292         &usb_host_device,
 293         &vpu_device,
 294         &veu0_device,
 295         &veu1_device,
 296 };
 297
 298 static int __init sh7366_devices_setup(void)
 299 {
 300         platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
 301         platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
 302         platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
 303
 304         return platform_add_devices(sh7366_devices,
 305                                     ARRAY_SIZE(sh7366_devices));
 306 }
 307 arch_initcall(sh7366_devices_setup);
 308
 309 static struct platform_device *sh7366_early_devices[] __initdata = {
 310         &scif0_device,
 311         &cmt_device,
 312         &tmu0_device,
 313         &tmu1_device,
 314         &tmu2_device,
 315 };
 316
 317 void __init plat_early_device_setup(void)
 318 {
 319         early_platform_add_devices(sh7366_early_devices,
 320                                    ARRAY_SIZE(sh7366_early_devices));
 321 }
 322
 323 enum {
 324         UNUSED=0,
 325         ENABLED,
 326         DISABLED,
 327
 328         /* interrupt sources */
 329         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 330         ICB,
 331         DMAC0, DMAC1, DMAC2, DMAC3,
 332         VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
 333         MFI, VPU, USB,
 334         MMC_MMC1I, MMC_MMC2I, MMC_MMC3I,
 335         DMAC4, DMAC5, DMAC_DADERR,
 336         SCIF, SCIFA1, SCIFA2,
 337         DENC, MSIOF,
 338         FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
 339         I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
 340         SDHI, CMT, TSIF, SIU,
 341         TMU0, TMU1, TMU2,
 342         VEU2, LCDC,
 343
 344         /* interrupt groups */
 345
 346         DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C,
 347 };
 348
 349 static struct intc_vect vectors[] __initdata = {
 350         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
 351         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
 352         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
 353         INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
 354         INTC_VECT(ICB, 0x700),
 355         INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
 356         INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
 357         INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
 358         INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
 359         INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980), INTC_VECT(USB, 0xa20),
 360         INTC_VECT(MMC_MMC1I, 0xb00), INTC_VECT(MMC_MMC2I, 0xb20),
 361         INTC_VECT(MMC_MMC3I, 0xb40),
 362         INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
 363         INTC_VECT(DMAC_DADERR, 0xbc0),
 364         INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIFA1, 0xc20),
 365         INTC_VECT(SCIFA2, 0xc40),
 366         INTC_VECT(DENC, 0xc60), INTC_VECT(MSIOF, 0xc80),
 367         INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
 368         INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
 369         INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
 370         INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
 371         INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
 372         INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
 373         INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
 374         INTC_VECT(SIU, 0xf80),
 375         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 376         INTC_VECT(TMU2, 0x440),
 377         INTC_VECT(VEU2, 0x560), INTC_VECT(LCDC, 0x580),
 378 };
 379
 380 static struct intc_group groups[] __initdata = {
 381         INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
 382         INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
 383         INTC_GROUP(MMC, MMC_MMC1I, MMC_MMC2I, MMC_MMC3I),
 384         INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
 385         INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
 386                    FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
 387         INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
 388 };
 389
 390 static struct intc_mask_reg mask_registers[] __initdata = {
 391         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
 392           { } },
 393         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
 394           { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
 395         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
 396           { 0, 0, 0, VPU, 0, 0, 0, MFI } },
 397         { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
 398           { 0, 0, 0, ICB } },
 399         { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
 400           { 0, TMU2, TMU1, TMU0, VEU2, 0, 0, LCDC } },
 401         { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
 402           { 0, DMAC_DADERR, DMAC5, DMAC4, DENC, SCIFA2, SCIFA1, SCIF } },
 403         { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
 404           { 0, 0, 0, 0, 0, 0, 0, MSIOF } },
 405         { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
 406           { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
 407             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
 408         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
 409           { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, 0, SIU } },
 410         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
 411           { 0, 0, 0, CMT, 0, USB, } },
 412         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
 413           { 0, MMC_MMC3I, MMC_MMC2I, MMC_MMC1I } },
 414         { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
 415           { 0, 0, 0, 0, 0, 0, 0, TSIF } },
 416         { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
 417           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 418 };
 419
 420 static struct intc_prio_reg prio_registers[] __initdata = {
 421         { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
 422         { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2, LCDC, ICB } },
 423         { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
 424         { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
 425         { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } },
 426         { 0xa4080014, 0, 16, 4, /* IPRF */ { 0, DMAC45, USB, CMT } },
 427         { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIFA1, SCIFA2, DENC } },
 428         { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF, 0, FLCTL, I2C } },
 429         { 0xa4080020, 0, 16, 4, /* IPRI */ { 0, 0, TSIF, } },
 430         { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
 431         { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
 432         { 0xa408002c, 0, 16, 4, /* IPRL */ { } },
 433         { 0xa4140010, 0, 32, 4, /* INTPRI00 */
 434           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 435 };
 436
 437 static struct intc_sense_reg sense_registers[] __initdata = {
 438         { 0xa414001c, 16, 2, /* ICR1 */
 439           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 440 };
 441
 442 static struct intc_mask_reg ack_registers[] __initdata = {
 443         { 0xa4140024, 0, 8, /* INTREQ00 */
 444           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 445 };
 446
 447 static struct intc_desc intc_desc __initdata = {
 448         .name = "sh7366",
 449         .force_enable = ENABLED,
 450         .force_disable = DISABLED,
 451         .hw = INTC_HW_DESC(vectors, groups, mask_registers,
 452                            prio_registers, sense_registers, ack_registers),
 453 };
 454
 455 void __init plat_irq_setup(void)
 456 {
 457         register_intc_controller(&intc_desc);
 458 }
 459
 460 void __init plat_mem_setup(void)
 461 {
 462         /* TODO: Register Node 1 */
 463 }