Merge tag 'v3.3.7' into 3.3/master
[zen-stable.git] / arch / sparc / kernel / irq_32.c
blobb2668afd1c347a928e1ed682a44fcf7386317891
1 /*
2 * Interrupt request handling routines. On the
3 * Sparc the IRQs are basically 'cast in stone'
4 * and you are supposed to probe the prom's device
5 * node trees to find out who's got which IRQ.
7 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
8 * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
9 * Copyright (C) 1995,2002 Pete A. Zaitcev (zaitcev@yahoo.com)
10 * Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
11 * Copyright (C) 1998-2000 Anton Blanchard (anton@samba.org)
14 #include <linux/kernel_stat.h>
15 #include <linux/seq_file.h>
16 #include <linux/export.h>
18 #include <asm/cacheflush.h>
19 #include <asm/cpudata.h>
20 #include <asm/pcic.h>
21 #include <asm/leon.h>
23 #include "kernel.h"
24 #include "irq.h"
26 #ifdef CONFIG_SMP
27 #define SMP_NOP2 "nop; nop;\n\t"
28 #define SMP_NOP3 "nop; nop; nop;\n\t"
29 #else
30 #define SMP_NOP2
31 #define SMP_NOP3
32 #endif /* SMP */
34 /* platform specific irq setup */
35 struct sparc_irq_config sparc_irq_config;
37 unsigned long arch_local_irq_save(void)
39 unsigned long retval;
40 unsigned long tmp;
42 __asm__ __volatile__(
43 "rd %%psr, %0\n\t"
44 SMP_NOP3 /* Sun4m + Cypress + SMP bug */
45 "or %0, %2, %1\n\t"
46 "wr %1, 0, %%psr\n\t"
47 "nop; nop; nop\n"
48 : "=&r" (retval), "=r" (tmp)
49 : "i" (PSR_PIL)
50 : "memory");
52 return retval;
54 EXPORT_SYMBOL(arch_local_irq_save);
56 void arch_local_irq_enable(void)
58 unsigned long tmp;
60 __asm__ __volatile__(
61 "rd %%psr, %0\n\t"
62 SMP_NOP3 /* Sun4m + Cypress + SMP bug */
63 "andn %0, %1, %0\n\t"
64 "wr %0, 0, %%psr\n\t"
65 "nop; nop; nop\n"
66 : "=&r" (tmp)
67 : "i" (PSR_PIL)
68 : "memory");
70 EXPORT_SYMBOL(arch_local_irq_enable);
72 void arch_local_irq_restore(unsigned long old_psr)
74 unsigned long tmp;
76 __asm__ __volatile__(
77 "rd %%psr, %0\n\t"
78 "and %2, %1, %2\n\t"
79 SMP_NOP2 /* Sun4m + Cypress + SMP bug */
80 "andn %0, %1, %0\n\t"
81 "wr %0, %2, %%psr\n\t"
82 "nop; nop; nop\n"
83 : "=&r" (tmp)
84 : "i" (PSR_PIL), "r" (old_psr)
85 : "memory");
87 EXPORT_SYMBOL(arch_local_irq_restore);
90 * Dave Redman (djhr@tadpole.co.uk)
92 * IRQ numbers.. These are no longer restricted to 15..
94 * this is done to enable SBUS cards and onboard IO to be masked
95 * correctly. using the interrupt level isn't good enough.
97 * For example:
98 * A device interrupting at sbus level6 and the Floppy both come in
99 * at IRQ11, but enabling and disabling them requires writing to
100 * different bits in the SLAVIO/SEC.
102 * As a result of these changes sun4m machines could now support
103 * directed CPU interrupts using the existing enable/disable irq code
104 * with tweaks.
106 * Sun4d complicates things even further. IRQ numbers are arbitrary
107 * 32-bit values in that case. Since this is similar to sparc64,
108 * we adopt a virtual IRQ numbering scheme as is done there.
109 * Virutal interrupt numbers are allocated by build_irq(). So NR_IRQS
110 * just becomes a limit of how many interrupt sources we can handle in
111 * a single system. Even fully loaded SS2000 machines top off at
112 * about 32 interrupt sources or so, therefore a NR_IRQS value of 64
113 * is more than enough.
115 * We keep a map of per-PIL enable interrupts. These get wired
116 * up via the irq_chip->startup() method which gets invoked by
117 * the generic IRQ layer during request_irq().
121 /* Table of allocated irqs. Unused entries has irq == 0 */
122 static struct irq_bucket irq_table[NR_IRQS];
123 /* Protect access to irq_table */
124 static DEFINE_SPINLOCK(irq_table_lock);
126 /* Map between the irq identifier used in hw to the irq_bucket. */
127 struct irq_bucket *irq_map[SUN4D_MAX_IRQ];
128 /* Protect access to irq_map */
129 static DEFINE_SPINLOCK(irq_map_lock);
131 /* Allocate a new irq from the irq_table */
132 unsigned int irq_alloc(unsigned int real_irq, unsigned int pil)
134 unsigned long flags;
135 unsigned int i;
137 spin_lock_irqsave(&irq_table_lock, flags);
138 for (i = 1; i < NR_IRQS; i++) {
139 if (irq_table[i].real_irq == real_irq && irq_table[i].pil == pil)
140 goto found;
143 for (i = 1; i < NR_IRQS; i++) {
144 if (!irq_table[i].irq)
145 break;
148 if (i < NR_IRQS) {
149 irq_table[i].real_irq = real_irq;
150 irq_table[i].irq = i;
151 irq_table[i].pil = pil;
152 } else {
153 printk(KERN_ERR "IRQ: Out of virtual IRQs.\n");
154 i = 0;
156 found:
157 spin_unlock_irqrestore(&irq_table_lock, flags);
159 return i;
162 /* Based on a single pil handler_irq may need to call several
163 * interrupt handlers. Use irq_map as entry to irq_table,
164 * and let each entry in irq_table point to the next entry.
166 void irq_link(unsigned int irq)
168 struct irq_bucket *p;
169 unsigned long flags;
170 unsigned int pil;
172 BUG_ON(irq >= NR_IRQS);
174 spin_lock_irqsave(&irq_map_lock, flags);
176 p = &irq_table[irq];
177 pil = p->pil;
178 BUG_ON(pil > SUN4D_MAX_IRQ);
179 p->next = irq_map[pil];
180 irq_map[pil] = p;
182 spin_unlock_irqrestore(&irq_map_lock, flags);
185 void irq_unlink(unsigned int irq)
187 struct irq_bucket *p, **pnext;
188 unsigned long flags;
190 BUG_ON(irq >= NR_IRQS);
192 spin_lock_irqsave(&irq_map_lock, flags);
194 p = &irq_table[irq];
195 BUG_ON(p->pil > SUN4D_MAX_IRQ);
196 pnext = &irq_map[p->pil];
197 while (*pnext != p)
198 pnext = &(*pnext)->next;
199 *pnext = p->next;
201 spin_unlock_irqrestore(&irq_map_lock, flags);
205 /* /proc/interrupts printing */
206 int arch_show_interrupts(struct seq_file *p, int prec)
208 int j;
210 #ifdef CONFIG_SMP
211 seq_printf(p, "RES: ");
212 for_each_online_cpu(j)
213 seq_printf(p, "%10u ", cpu_data(j).irq_resched_count);
214 seq_printf(p, " IPI rescheduling interrupts\n");
215 seq_printf(p, "CAL: ");
216 for_each_online_cpu(j)
217 seq_printf(p, "%10u ", cpu_data(j).irq_call_count);
218 seq_printf(p, " IPI function call interrupts\n");
219 #endif
220 seq_printf(p, "NMI: ");
221 for_each_online_cpu(j)
222 seq_printf(p, "%10u ", cpu_data(j).counter);
223 seq_printf(p, " Non-maskable interrupts\n");
224 return 0;
227 void handler_irq(unsigned int pil, struct pt_regs *regs)
229 struct pt_regs *old_regs;
230 struct irq_bucket *p;
232 BUG_ON(pil > 15);
233 old_regs = set_irq_regs(regs);
234 irq_enter();
236 p = irq_map[pil];
237 while (p) {
238 struct irq_bucket *next = p->next;
240 generic_handle_irq(p->irq);
241 p = next;
243 irq_exit();
244 set_irq_regs(old_regs);
247 #if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE)
248 static unsigned int floppy_irq;
250 int sparc_floppy_request_irq(unsigned int irq, irq_handler_t irq_handler)
252 unsigned int cpu_irq;
253 int err;
255 #if defined CONFIG_SMP && !defined CONFIG_SPARC_LEON
256 struct tt_entry *trap_table;
257 #endif
259 err = request_irq(irq, irq_handler, 0, "floppy", NULL);
260 if (err)
261 return -1;
263 /* Save for later use in floppy interrupt handler */
264 floppy_irq = irq;
266 cpu_irq = (irq & (NR_IRQS - 1));
268 /* Dork with trap table if we get this far. */
269 #define INSTANTIATE(table) \
270 table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_one = SPARC_RD_PSR_L0; \
271 table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_two = \
272 SPARC_BRANCH((unsigned long) floppy_hardint, \
273 (unsigned long) &table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_two);\
274 table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_three = SPARC_RD_WIM_L3; \
275 table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_four = SPARC_NOP;
277 INSTANTIATE(sparc_ttable)
278 #if defined CONFIG_SMP && !defined CONFIG_SPARC_LEON
279 trap_table = &trapbase_cpu1;
280 INSTANTIATE(trap_table)
281 trap_table = &trapbase_cpu2;
282 INSTANTIATE(trap_table)
283 trap_table = &trapbase_cpu3;
284 INSTANTIATE(trap_table)
285 #endif
286 #undef INSTANTIATE
288 * XXX Correct thing whould be to flush only I- and D-cache lines
289 * which contain the handler in question. But as of time of the
290 * writing we have no CPU-neutral interface to fine-grained flushes.
292 flush_cache_all();
293 return 0;
295 EXPORT_SYMBOL(sparc_floppy_request_irq);
298 * These variables are used to access state from the assembler
299 * interrupt handler, floppy_hardint, so we cannot put these in
300 * the floppy driver image because that would not work in the
301 * modular case.
303 volatile unsigned char *fdc_status;
304 EXPORT_SYMBOL(fdc_status);
306 char *pdma_vaddr;
307 EXPORT_SYMBOL(pdma_vaddr);
309 unsigned long pdma_size;
310 EXPORT_SYMBOL(pdma_size);
312 volatile int doing_pdma;
313 EXPORT_SYMBOL(doing_pdma);
315 char *pdma_base;
316 EXPORT_SYMBOL(pdma_base);
318 unsigned long pdma_areasize;
319 EXPORT_SYMBOL(pdma_areasize);
321 /* Use the generic irq support to call floppy_interrupt
322 * which was setup using request_irq() in sparc_floppy_request_irq().
323 * We only have one floppy interrupt so we do not need to check
324 * for additional handlers being wired up by irq_link()
326 void sparc_floppy_irq(int irq, void *dev_id, struct pt_regs *regs)
328 struct pt_regs *old_regs;
330 old_regs = set_irq_regs(regs);
331 irq_enter();
332 generic_handle_irq(floppy_irq);
333 irq_exit();
334 set_irq_regs(old_regs);
336 #endif
338 /* djhr
339 * This could probably be made indirect too and assigned in the CPU
340 * bits of the code. That would be much nicer I think and would also
341 * fit in with the idea of being able to tune your kernel for your machine
342 * by removing unrequired machine and device support.
346 void __init init_IRQ(void)
348 switch (sparc_cpu_model) {
349 case sun4c:
350 case sun4:
351 sun4c_init_IRQ();
352 break;
354 case sun4m:
355 pcic_probe();
356 if (pcic_present())
357 sun4m_pci_init_IRQ();
358 else
359 sun4m_init_IRQ();
360 break;
362 case sun4d:
363 sun4d_init_IRQ();
364 break;
366 case sparc_leon:
367 leon_init_IRQ();
368 break;
370 default:
371 prom_printf("Cannot initialize IRQs on this Sun machine...");
372 break;
374 btfixup();