arch/sparc/kernel/pci_fire.c

   1 /* pci_fire.c: Sun4u platform PCI-E controller support.
   2  *
   3  * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
   4  */
   5 #include <linux/kernel.h>
   6 #include <linux/pci.h>
   7 #include <linux/slab.h>
   8 #include <linux/init.h>
   9 #include <linux/msi.h>
  10 #include <linux/export.h>
  11 #include <linux/irq.h>
  12 #include <linux/of_device.h>
  13
  14 #include <asm/prom.h>
  15 #include <asm/irq.h>
  16 #include <asm/upa.h>
  17
  18 #include "pci_impl.h"
  19
  20 #define DRIVER_NAME     "fire"
  21 #define PFX             DRIVER_NAME ": "
  22
  23 #define FIRE_IOMMU_CONTROL      0x40000UL
  24 #define FIRE_IOMMU_TSBBASE      0x40008UL
  25 #define FIRE_IOMMU_FLUSH        0x40100UL
  26 #define FIRE_IOMMU_FLUSHINV     0x40108UL
  27
  28 static int pci_fire_pbm_iommu_init(struct pci_pbm_info *pbm)
  29 {
  30         struct iommu *iommu = pbm->iommu;
  31         u32 vdma[2], dma_mask;
  32         u64 control;
  33         int tsbsize, err;
  34
  35         /* No virtual-dma property on these guys, use largest size.  */
  36         vdma[0] = 0xc0000000; /* base */
  37         vdma[1] = 0x40000000; /* size */
  38         dma_mask = 0xffffffff;
  39         tsbsize = 128;
  40
  41         /* Register addresses. */
  42         iommu->iommu_control  = pbm->pbm_regs + FIRE_IOMMU_CONTROL;
  43         iommu->iommu_tsbbase  = pbm->pbm_regs + FIRE_IOMMU_TSBBASE;
  44         iommu->iommu_flush    = pbm->pbm_regs + FIRE_IOMMU_FLUSH;
  45         iommu->iommu_flushinv = pbm->pbm_regs + FIRE_IOMMU_FLUSHINV;
  46
  47         /* We use the main control/status register of FIRE as the write
  48          * completion register.
  49          */
  50         iommu->write_complete_reg = pbm->controller_regs + 0x410000UL;
  51
  52         /*
  53          * Invalidate TLB Entries.
  54          */
  55         upa_writeq(~(u64)0, iommu->iommu_flushinv);
  56
  57         err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask,
  58                                pbm->numa_node);
  59         if (err)
  60                 return err;
  61
  62         upa_writeq(__pa(iommu->page_table) | 0x7UL, iommu->iommu_tsbbase);
  63
  64         control = upa_readq(iommu->iommu_control);
  65         control |= (0x00000400 /* TSB cache snoop enable */     |
  66                     0x00000300 /* Cache mode */                 |
  67                     0x00000002 /* Bypass enable */              |
  68                     0x00000001 /* Translation enable */);
  69         upa_writeq(control, iommu->iommu_control);
  70
  71         return 0;
  72 }
  73
  74 #ifdef CONFIG_PCI_MSI
  75 struct pci_msiq_entry {
  76         u64             word0;
  77 #define MSIQ_WORD0_RESV                 0x8000000000000000UL
  78 #define MSIQ_WORD0_FMT_TYPE             0x7f00000000000000UL
  79 #define MSIQ_WORD0_FMT_TYPE_SHIFT       56
  80 #define MSIQ_WORD0_LEN                  0x00ffc00000000000UL
  81 #define MSIQ_WORD0_LEN_SHIFT            46
  82 #define MSIQ_WORD0_ADDR0                0x00003fff00000000UL
  83 #define MSIQ_WORD0_ADDR0_SHIFT          32
  84 #define MSIQ_WORD0_RID                  0x00000000ffff0000UL
  85 #define MSIQ_WORD0_RID_SHIFT            16
  86 #define MSIQ_WORD0_DATA0                0x000000000000ffffUL
  87 #define MSIQ_WORD0_DATA0_SHIFT          0
  88
  89 #define MSIQ_TYPE_MSG                   0x6
  90 #define MSIQ_TYPE_MSI32                 0xb
  91 #define MSIQ_TYPE_MSI64                 0xf
  92
  93         u64             word1;
  94 #define MSIQ_WORD1_ADDR1                0xffffffffffff0000UL
  95 #define MSIQ_WORD1_ADDR1_SHIFT          16
  96 #define MSIQ_WORD1_DATA1                0x000000000000ffffUL
  97 #define MSIQ_WORD1_DATA1_SHIFT          0
  98
  99         u64             resv[6];
 100 };
 101
 102 /* All MSI registers are offset from pbm->pbm_regs */
 103 #define EVENT_QUEUE_BASE_ADDR_REG       0x010000UL
 104 #define  EVENT_QUEUE_BASE_ADDR_ALL_ONES 0xfffc000000000000UL
 105
 106 #define EVENT_QUEUE_CONTROL_SET(EQ)     (0x011000UL + (EQ) * 0x8UL)
 107 #define  EVENT_QUEUE_CONTROL_SET_OFLOW  0x0200000000000000UL
 108 #define  EVENT_QUEUE_CONTROL_SET_EN     0x0000100000000000UL
 109
 110 #define EVENT_QUEUE_CONTROL_CLEAR(EQ)   (0x011200UL + (EQ) * 0x8UL)
 111 #define  EVENT_QUEUE_CONTROL_CLEAR_OF   0x0200000000000000UL
 112 #define  EVENT_QUEUE_CONTROL_CLEAR_E2I  0x0000800000000000UL
 113 #define  EVENT_QUEUE_CONTROL_CLEAR_DIS  0x0000100000000000UL
 114
 115 #define EVENT_QUEUE_STATE(EQ)           (0x011400UL + (EQ) * 0x8UL)
 116 #define  EVENT_QUEUE_STATE_MASK         0x0000000000000007UL
 117 #define  EVENT_QUEUE_STATE_IDLE         0x0000000000000001UL
 118 #define  EVENT_QUEUE_STATE_ACTIVE       0x0000000000000002UL
 119 #define  EVENT_QUEUE_STATE_ERROR        0x0000000000000004UL
 120
 121 #define EVENT_QUEUE_TAIL(EQ)            (0x011600UL + (EQ) * 0x8UL)
 122 #define  EVENT_QUEUE_TAIL_OFLOW         0x0200000000000000UL
 123 #define  EVENT_QUEUE_TAIL_VAL           0x000000000000007fUL
 124
 125 #define EVENT_QUEUE_HEAD(EQ)            (0x011800UL + (EQ) * 0x8UL)
 126 #define  EVENT_QUEUE_HEAD_VAL           0x000000000000007fUL
 127
 128 #define MSI_MAP(MSI)                    (0x020000UL + (MSI) * 0x8UL)
 129 #define  MSI_MAP_VALID                  0x8000000000000000UL
 130 #define  MSI_MAP_EQWR_N                 0x4000000000000000UL
 131 #define  MSI_MAP_EQNUM                  0x000000000000003fUL
 132
 133 #define MSI_CLEAR(MSI)                  (0x028000UL + (MSI) * 0x8UL)
 134 #define  MSI_CLEAR_EQWR_N               0x4000000000000000UL
 135
 136 #define IMONDO_DATA0                    0x02C000UL
 137 #define  IMONDO_DATA0_DATA              0xffffffffffffffc0UL
 138
 139 #define IMONDO_DATA1                    0x02C008UL
 140 #define  IMONDO_DATA1_DATA              0xffffffffffffffffUL
 141
 142 #define MSI_32BIT_ADDR                  0x034000UL
 143 #define  MSI_32BIT_ADDR_VAL             0x00000000ffff0000UL
 144
 145 #define MSI_64BIT_ADDR                  0x034008UL
 146 #define  MSI_64BIT_ADDR_VAL             0xffffffffffff0000UL
 147
 148 static int pci_fire_get_head(struct pci_pbm_info *pbm, unsigned long msiqid,
 149                              unsigned long *head)
 150 {
 151         *head = upa_readq(pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid));
 152         return 0;
 153 }
 154
 155 static int pci_fire_dequeue_msi(struct pci_pbm_info *pbm, unsigned long msiqid,
 156                                 unsigned long *head, unsigned long *msi)
 157 {
 158         unsigned long type_fmt, type, msi_num;
 159         struct pci_msiq_entry *base, *ep;
 160
 161         base = (pbm->msi_queues + ((msiqid - pbm->msiq_first) * 8192));
 162         ep = &base[*head];
 163
 164         if ((ep->word0 & MSIQ_WORD0_FMT_TYPE) == 0)
 165                 return 0;
 166
 167         type_fmt = ((ep->word0 & MSIQ_WORD0_FMT_TYPE) >>
 168                     MSIQ_WORD0_FMT_TYPE_SHIFT);
 169         type = (type_fmt >> 3);
 170         if (unlikely(type != MSIQ_TYPE_MSI32 &&
 171                      type != MSIQ_TYPE_MSI64))
 172                 return -EINVAL;
 173
 174         *msi = msi_num = ((ep->word0 & MSIQ_WORD0_DATA0) >>
 175                           MSIQ_WORD0_DATA0_SHIFT);
 176
 177         upa_writeq(MSI_CLEAR_EQWR_N, pbm->pbm_regs + MSI_CLEAR(msi_num));
 178
 179         /* Clear the entry.  */
 180         ep->word0 &= ~MSIQ_WORD0_FMT_TYPE;
 181
 182         /* Go to next entry in ring.  */
 183         (*head)++;
 184         if (*head >= pbm->msiq_ent_count)
 185                 *head = 0;
 186
 187         return 1;
 188 }
 189
 190 static int pci_fire_set_head(struct pci_pbm_info *pbm, unsigned long msiqid,
 191                              unsigned long head)
 192 {
 193         upa_writeq(head, pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid));
 194         return 0;
 195 }
 196
 197 static int pci_fire_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid,
 198                               unsigned long msi, int is_msi64)
 199 {
 200         u64 val;
 201
 202         val = upa_readq(pbm->pbm_regs + MSI_MAP(msi));
 203         val &= ~(MSI_MAP_EQNUM);
 204         val |= msiqid;
 205         upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi));
 206
 207         upa_writeq(MSI_CLEAR_EQWR_N, pbm->pbm_regs + MSI_CLEAR(msi));
 208
 209         val = upa_readq(pbm->pbm_regs + MSI_MAP(msi));
 210         val |= MSI_MAP_VALID;
 211         upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi));
 212
 213         return 0;
 214 }
 215
 216 static int pci_fire_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi)
 217 {
 218         u64 val;
 219
 220         val = upa_readq(pbm->pbm_regs + MSI_MAP(msi));
 221
 222         val &= ~MSI_MAP_VALID;
 223
 224         upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi));
 225
 226         return 0;
 227 }
 228
 229 static int pci_fire_msiq_alloc(struct pci_pbm_info *pbm)
 230 {
 231         unsigned long pages, order, i;
 232
 233         order = get_order(512 * 1024);
 234         pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order);
 235         if (pages == 0UL) {
 236                 printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
 237                        order);
 238                 return -ENOMEM;
 239         }
 240         memset((char *)pages, 0, PAGE_SIZE << order);
 241         pbm->msi_queues = (void *) pages;
 242
 243         upa_writeq((EVENT_QUEUE_BASE_ADDR_ALL_ONES |
 244                     __pa(pbm->msi_queues)),
 245                    pbm->pbm_regs + EVENT_QUEUE_BASE_ADDR_REG);
 246
 247         upa_writeq(pbm->portid << 6, pbm->pbm_regs + IMONDO_DATA0);
 248         upa_writeq(0, pbm->pbm_regs + IMONDO_DATA1);
 249
 250         upa_writeq(pbm->msi32_start, pbm->pbm_regs + MSI_32BIT_ADDR);
 251         upa_writeq(pbm->msi64_start, pbm->pbm_regs + MSI_64BIT_ADDR);
 252
 253         for (i = 0; i < pbm->msiq_num; i++) {
 254                 upa_writeq(0, pbm->pbm_regs + EVENT_QUEUE_HEAD(i));
 255                 upa_writeq(0, pbm->pbm_regs + EVENT_QUEUE_TAIL(i));
 256         }
 257
 258         return 0;
 259 }
 260
 261 static void pci_fire_msiq_free(struct pci_pbm_info *pbm)
 262 {
 263         unsigned long pages, order;
 264
 265         order = get_order(512 * 1024);
 266         pages = (unsigned long) pbm->msi_queues;
 267
 268         free_pages(pages, order);
 269
 270         pbm->msi_queues = NULL;
 271 }
 272
 273 static int pci_fire_msiq_build_irq(struct pci_pbm_info *pbm,
 274                                    unsigned long msiqid,
 275                                    unsigned long devino)
 276 {
 277         unsigned long cregs = (unsigned long) pbm->pbm_regs;
 278         unsigned long imap_reg, iclr_reg, int_ctrlr;
 279         unsigned int irq;
 280         int fixup;
 281         u64 val;
 282
 283         imap_reg = cregs + (0x001000UL + (devino * 0x08UL));
 284         iclr_reg = cregs + (0x001400UL + (devino * 0x08UL));
 285
 286         /* XXX iterate amongst the 4 IRQ controllers XXX */
 287         int_ctrlr = (1UL << 6);
 288
 289         val = upa_readq(imap_reg);
 290         val |= (1UL << 63) | int_ctrlr;
 291         upa_writeq(val, imap_reg);
 292
 293         fixup = ((pbm->portid << 6) | devino) - int_ctrlr;
 294
 295         irq = build_irq(fixup, iclr_reg, imap_reg);
 296         if (!irq)
 297                 return -ENOMEM;
 298
 299         upa_writeq(EVENT_QUEUE_CONTROL_SET_EN,
 300                    pbm->pbm_regs + EVENT_QUEUE_CONTROL_SET(msiqid));
 301
 302         return irq;
 303 }
 304
 305 static const struct sparc64_msiq_ops pci_fire_msiq_ops = {
 306         .get_head       =       pci_fire_get_head,
 307         .dequeue_msi    =       pci_fire_dequeue_msi,
 308         .set_head       =       pci_fire_set_head,
 309         .msi_setup      =       pci_fire_msi_setup,
 310         .msi_teardown   =       pci_fire_msi_teardown,
 311         .msiq_alloc     =       pci_fire_msiq_alloc,
 312         .msiq_free      =       pci_fire_msiq_free,
 313         .msiq_build_irq =       pci_fire_msiq_build_irq,
 314 };
 315
 316 static void pci_fire_msi_init(struct pci_pbm_info *pbm)
 317 {
 318         sparc64_pbm_msi_init(pbm, &pci_fire_msiq_ops);
 319 }
 320 #else /* CONFIG_PCI_MSI */
 321 static void pci_fire_msi_init(struct pci_pbm_info *pbm)
 322 {
 323 }
 324 #endif /* !(CONFIG_PCI_MSI) */
 325
 326 /* Based at pbm->controller_regs */
 327 #define FIRE_PARITY_CONTROL     0x470010UL
 328 #define  FIRE_PARITY_ENAB       0x8000000000000000UL
 329 #define FIRE_FATAL_RESET_CTL    0x471028UL
 330 #define  FIRE_FATAL_RESET_SPARE 0x0000000004000000UL
 331 #define  FIRE_FATAL_RESET_MB    0x0000000002000000UL
 332 #define  FIRE_FATAL_RESET_CPE   0x0000000000008000UL
 333 #define  FIRE_FATAL_RESET_APE   0x0000000000004000UL
 334 #define  FIRE_FATAL_RESET_PIO   0x0000000000000040UL
 335 #define  FIRE_FATAL_RESET_JW    0x0000000000000004UL
 336 #define  FIRE_FATAL_RESET_JI    0x0000000000000002UL
 337 #define  FIRE_FATAL_RESET_JR    0x0000000000000001UL
 338 #define FIRE_CORE_INTR_ENABLE   0x471800UL
 339
 340 /* Based at pbm->pbm_regs */
 341 #define FIRE_TLU_CTRL           0x80000UL
 342 #define  FIRE_TLU_CTRL_TIM      0x00000000da000000UL
 343 #define  FIRE_TLU_CTRL_QDET     0x0000000000000100UL
 344 #define  FIRE_TLU_CTRL_CFG      0x0000000000000001UL
 345 #define FIRE_TLU_DEV_CTRL       0x90008UL
 346 #define FIRE_TLU_LINK_CTRL      0x90020UL
 347 #define FIRE_TLU_LINK_CTRL_CLK  0x0000000000000040UL
 348 #define FIRE_LPU_RESET          0xe2008UL
 349 #define FIRE_LPU_LLCFG          0xe2200UL
 350 #define  FIRE_LPU_LLCFG_VC0     0x0000000000000100UL
 351 #define FIRE_LPU_FCTRL_UCTRL    0xe2240UL
 352 #define  FIRE_LPU_FCTRL_UCTRL_N 0x0000000000000002UL
 353 #define  FIRE_LPU_FCTRL_UCTRL_P 0x0000000000000001UL
 354 #define FIRE_LPU_TXL_FIFOP      0xe2430UL
 355 #define FIRE_LPU_LTSSM_CFG2     0xe2788UL
 356 #define FIRE_LPU_LTSSM_CFG3     0xe2790UL
 357 #define FIRE_LPU_LTSSM_CFG4     0xe2798UL
 358 #define FIRE_LPU_LTSSM_CFG5     0xe27a0UL
 359 #define FIRE_DMC_IENAB          0x31800UL
 360 #define FIRE_DMC_DBG_SEL_A      0x53000UL
 361 #define FIRE_DMC_DBG_SEL_B      0x53008UL
 362 #define FIRE_PEC_IENAB          0x51800UL
 363
 364 static void pci_fire_hw_init(struct pci_pbm_info *pbm)
 365 {
 366         u64 val;
 367
 368         upa_writeq(FIRE_PARITY_ENAB,
 369                    pbm->controller_regs + FIRE_PARITY_CONTROL);
 370
 371         upa_writeq((FIRE_FATAL_RESET_SPARE |
 372                     FIRE_FATAL_RESET_MB |
 373                     FIRE_FATAL_RESET_CPE |
 374                     FIRE_FATAL_RESET_APE |
 375                     FIRE_FATAL_RESET_PIO |
 376                     FIRE_FATAL_RESET_JW |
 377                     FIRE_FATAL_RESET_JI |
 378                     FIRE_FATAL_RESET_JR),
 379                    pbm->controller_regs + FIRE_FATAL_RESET_CTL);
 380
 381         upa_writeq(~(u64)0, pbm->controller_regs + FIRE_CORE_INTR_ENABLE);
 382
 383         val = upa_readq(pbm->pbm_regs + FIRE_TLU_CTRL);
 384         val |= (FIRE_TLU_CTRL_TIM |
 385                 FIRE_TLU_CTRL_QDET |
 386                 FIRE_TLU_CTRL_CFG);
 387         upa_writeq(val, pbm->pbm_regs + FIRE_TLU_CTRL);
 388         upa_writeq(0, pbm->pbm_regs + FIRE_TLU_DEV_CTRL);
 389         upa_writeq(FIRE_TLU_LINK_CTRL_CLK,
 390                    pbm->pbm_regs + FIRE_TLU_LINK_CTRL);
 391
 392         upa_writeq(0, pbm->pbm_regs + FIRE_LPU_RESET);
 393         upa_writeq(FIRE_LPU_LLCFG_VC0, pbm->pbm_regs + FIRE_LPU_LLCFG);
 394         upa_writeq((FIRE_LPU_FCTRL_UCTRL_N | FIRE_LPU_FCTRL_UCTRL_P),
 395                    pbm->pbm_regs + FIRE_LPU_FCTRL_UCTRL);
 396         upa_writeq(((0xffff << 16) | (0x0000 << 0)),
 397                    pbm->pbm_regs + FIRE_LPU_TXL_FIFOP);
 398         upa_writeq(3000000, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG2);
 399         upa_writeq(500000, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG3);
 400         upa_writeq((2 << 16) | (140 << 8),
 401                    pbm->pbm_regs + FIRE_LPU_LTSSM_CFG4);
 402         upa_writeq(0, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG5);
 403
 404         upa_writeq(~(u64)0, pbm->pbm_regs + FIRE_DMC_IENAB);
 405         upa_writeq(0, pbm->pbm_regs + FIRE_DMC_DBG_SEL_A);
 406         upa_writeq(0, pbm->pbm_regs + FIRE_DMC_DBG_SEL_B);
 407
 408         upa_writeq(~(u64)0, pbm->pbm_regs + FIRE_PEC_IENAB);
 409 }
 410
 411 static int __devinit pci_fire_pbm_init(struct pci_pbm_info *pbm,
 412                                        struct platform_device *op, u32 portid)
 413 {
 414         const struct linux_prom64_registers *regs;
 415         struct device_node *dp = op->dev.of_node;
 416         int err;
 417
 418         pbm->numa_node = -1;
 419
 420         pbm->pci_ops = &sun4u_pci_ops;
 421         pbm->config_space_reg_bits = 12;
 422
 423         pbm->index = pci_num_pbms++;
 424
 425         pbm->portid = portid;
 426         pbm->op = op;
 427         pbm->name = dp->full_name;
 428
 429         regs = of_get_property(dp, "reg", NULL);
 430         pbm->pbm_regs = regs[0].phys_addr;
 431         pbm->controller_regs = regs[1].phys_addr - 0x410000UL;
 432
 433         printk("%s: SUN4U PCIE Bus Module\n", pbm->name);
 434
 435         pci_determine_mem_io_space(pbm);
 436
 437         pci_get_pbm_props(pbm);
 438
 439         pci_fire_hw_init(pbm);
 440
 441         err = pci_fire_pbm_iommu_init(pbm);
 442         if (err)
 443                 return err;
 444
 445         pci_fire_msi_init(pbm);
 446
 447         pbm->pci_bus = pci_scan_one_pbm(pbm, &op->dev);
 448
 449         /* XXX register error interrupt handlers XXX */
 450
 451         pbm->next = pci_pbm_root;
 452         pci_pbm_root = pbm;
 453
 454         return 0;
 455 }
 456
 457 static int __devinit fire_probe(struct platform_device *op)
 458 {
 459         struct device_node *dp = op->dev.of_node;
 460         struct pci_pbm_info *pbm;
 461         struct iommu *iommu;
 462         u32 portid;
 463         int err;
 464
 465         portid = of_getintprop_default(dp, "portid", 0xff);
 466
 467         err = -ENOMEM;
 468         pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
 469         if (!pbm) {
 470                 printk(KERN_ERR PFX "Cannot allocate pci_pbminfo.\n");
 471                 goto out_err;
 472         }
 473
 474         iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
 475         if (!iommu) {
 476                 printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n");
 477                 goto out_free_controller;
 478         }
 479
 480         pbm->iommu = iommu;
 481
 482         err = pci_fire_pbm_init(pbm, op, portid);
 483         if (err)
 484                 goto out_free_iommu;
 485
 486         dev_set_drvdata(&op->dev, pbm);
 487
 488         return 0;
 489
 490 out_free_iommu:
 491         kfree(pbm->iommu);
 492
 493 out_free_controller:
 494         kfree(pbm);
 495
 496 out_err:
 497         return err;
 498 }
 499
 500 static const struct of_device_id fire_match[] = {
 501         {
 502                 .name = "pci",
 503                 .compatible = "pciex108e,80f0",
 504         },
 505         {},
 506 };
 507
 508 static struct platform_driver fire_driver = {
 509         .driver = {
 510                 .name = DRIVER_NAME,
 511                 .owner = THIS_MODULE,
 512                 .of_match_table = fire_match,
 513         },
 514         .probe          = fire_probe,
 515 };
 516
 517 static int __init fire_init(void)
 518 {
 519         return platform_driver_register(&fire_driver);
 520 }
 521
 522 subsys_initcall(fire_init);