arch/x86/kernel/cpu/intel.c

   1 #include <linux/init.h>
   2 #include <linux/kernel.h>
   3
   4 #include <linux/string.h>
   5 #include <linux/bitops.h>
   6 #include <linux/smp.h>
   7 #include <linux/sched.h>
   8 #include <linux/thread_info.h>
   9 #include <linux/module.h>
  10 #include <linux/uaccess.h>
  11
  12 #include <asm/processor.h>
  13 #include <asm/pgtable.h>
  14 #include <asm/msr.h>
  15 #include <asm/bugs.h>
  16 #include <asm/cpu.h>
  17
  18 #ifdef CONFIG_X86_64
  19 #include <linux/topology.h>
  20 #include <asm/numa_64.h>
  21 #endif
  22
  23 #include "cpu.h"
  24
  25 #ifdef CONFIG_X86_LOCAL_APIC
  26 #include <asm/mpspec.h>
  27 #include <asm/apic.h>
  28 #endif
  29
  30 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
  31 {
  32         u64 misc_enable;
  33         bool allow_fast_string = true;
  34
  35         /* Unmask CPUID levels if masked: */
  36         if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
  37                 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
  38
  39                 if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
  40                         misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
  41                         wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
  42                         c->cpuid_level = cpuid_eax(0);
  43                         get_cpu_cap(c);
  44                 }
  45         }
  46
  47         if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
  48                 (c->x86 == 0x6 && c->x86_model >= 0x0e))
  49                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
  50
  51         if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) {
  52                 unsigned lower_word;
  53
  54                 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
  55                 /* Required by the SDM */
  56                 sync_core();
  57                 rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode);
  58         }
  59
  60         /*
  61          * Atom erratum AAE44/AAF40/AAG38/AAH41:
  62          *
  63          * A race condition between speculative fetches and invalidating
  64          * a large page.  This is worked around in microcode, but we
  65          * need the microcode to have already been loaded... so if it is
  66          * not, recommend a BIOS update and disable large pages.
  67          */
  68         if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
  69             c->microcode < 0x20e) {
  70                 printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
  71                 clear_cpu_cap(c, X86_FEATURE_PSE);
  72         }
  73
  74 #ifdef CONFIG_X86_64
  75         set_cpu_cap(c, X86_FEATURE_SYSENTER32);
  76 #else
  77         /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
  78         if (c->x86 == 15 && c->x86_cache_alignment == 64)
  79                 c->x86_cache_alignment = 128;
  80 #endif
  81
  82         /* CPUID workaround for 0F33/0F34 CPU */
  83         if (c->x86 == 0xF && c->x86_model == 0x3
  84             && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
  85                 c->x86_phys_bits = 36;
  86
  87         /*
  88          * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
  89          * with P/T states and does not stop in deep C-states.
  90          *
  91          * It is also reliable across cores and sockets. (but not across
  92          * cabinets - we turn it off in that case explicitly.)
  93          */
  94         if (c->x86_power & (1 << 8)) {
  95                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
  96                 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
  97                 if (!check_tsc_unstable())
  98                         sched_clock_stable = 1;
  99         }
 100
 101         /*
 102          * There is a known erratum on Pentium III and Core Solo
 103          * and Core Duo CPUs.
 104          * " Page with PAT set to WC while associated MTRR is UC
 105          *   may consolidate to UC "
 106          * Because of this erratum, it is better to stick with
 107          * setting WC in MTRR rather than using PAT on these CPUs.
 108          *
 109          * Enable PAT WC only on P4, Core 2 or later CPUs.
 110          */
 111         if (c->x86 == 6 && c->x86_model < 15)
 112                 clear_cpu_cap(c, X86_FEATURE_PAT);
 113
 114 #ifdef CONFIG_KMEMCHECK
 115         /*
 116          * P4s have a "fast strings" feature which causes single-
 117          * stepping REP instructions to only generate a #DB on
 118          * cache-line boundaries.
 119          *
 120          * Ingo Molnar reported a Pentium D (model 6) and a Xeon
 121          * (model 2) with the same problem.
 122          */
 123         if (c->x86 == 15) {
 124                 allow_fast_string = false;
 125
 126                 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
 127                 if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) {
 128                         printk_once(KERN_INFO "kmemcheck: Disabling fast string operations\n");
 129
 130                         misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING;
 131                         wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
 132                 }
 133         }
 134 #endif
 135
 136         /*
 137          * If BIOS didn't enable fast string operation, try to enable
 138          * it ourselves.  If that fails, then clear the fast string
 139          * and enhanced fast string CPU capabilities.
 140          */
 141         if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
 142                 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
 143
 144                 if (allow_fast_string &&
 145                     !(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
 146                         misc_enable |= MSR_IA32_MISC_ENABLE_FAST_STRING;
 147                         wrmsr_safe(MSR_IA32_MISC_ENABLE, (u32)misc_enable,
 148                                    (u32)(misc_enable >> 32));
 149
 150                         /* Re-read to make sure it stuck. */
 151                         rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
 152
 153                         if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)
 154                                 printk_once(KERN_INFO FW_WARN "IA32_MISC_ENABLE.FAST_STRING_ENABLE was not set\n");
 155                 }
 156
 157                 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
 158                         if (allow_fast_string)
 159                                 printk_once(KERN_INFO "Failed to enable fast string operations\n");
 160                         setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
 161                         setup_clear_cpu_cap(X86_FEATURE_ERMS);
 162                 }
 163         }
 164 }
 165
 166 #ifdef CONFIG_X86_32
 167 /*
 168  *      Early probe support logic for ppro memory erratum #50
 169  *
 170  *      This is called before we do cpu ident work
 171  */
 172
 173 int __cpuinit ppro_with_ram_bug(void)
 174 {
 175         /* Uses data from early_cpu_detect now */
 176         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
 177             boot_cpu_data.x86 == 6 &&
 178             boot_cpu_data.x86_model == 1 &&
 179             boot_cpu_data.x86_mask < 8) {
 180                 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
 181                 return 1;
 182         }
 183         return 0;
 184 }
 185
 186 #ifdef CONFIG_X86_F00F_BUG
 187 static void __cpuinit trap_init_f00f_bug(void)
 188 {
 189         __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
 190
 191         /*
 192          * Update the IDT descriptor and reload the IDT so that
 193          * it uses the read-only mapped virtual address.
 194          */
 195         idt_descr.address = fix_to_virt(FIX_F00F_IDT);
 196         load_idt(&idt_descr);
 197 }
 198 #endif
 199
 200 static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c)
 201 {
 202         /* calling is from identify_secondary_cpu() ? */
 203         if (!c->cpu_index)
 204                 return;
 205
 206         /*
 207          * Mask B, Pentium, but not Pentium MMX
 208          */
 209         if (c->x86 == 5 &&
 210             c->x86_mask >= 1 && c->x86_mask <= 4 &&
 211             c->x86_model <= 3) {
 212                 /*
 213                  * Remember we have B step Pentia with bugs
 214                  */
 215                 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
 216                                     "with B stepping processors.\n");
 217         }
 218 }
 219
 220 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
 221 {
 222         unsigned long lo, hi;
 223
 224 #ifdef CONFIG_X86_F00F_BUG
 225         /*
 226          * All current models of Pentium and Pentium with MMX technology CPUs
 227          * have the F0 0F bug, which lets nonprivileged users lock up the
 228          * system.
 229          * Note that the workaround only should be initialized once...
 230          */
 231         c->f00f_bug = 0;
 232         if (!paravirt_enabled() && c->x86 == 5) {
 233                 static int f00f_workaround_enabled;
 234
 235                 c->f00f_bug = 1;
 236                 if (!f00f_workaround_enabled) {
 237                         trap_init_f00f_bug();
 238                         printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
 239                         f00f_workaround_enabled = 1;
 240                 }
 241         }
 242 #endif
 243
 244         /*
 245          * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
 246          * model 3 mask 3
 247          */
 248         if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
 249                 clear_cpu_cap(c, X86_FEATURE_SEP);
 250
 251         /*
 252          * P4 Xeon errata 037 workaround.
 253          * Hardware prefetcher may cause stale data to be loaded into the cache.
 254          */
 255         if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
 256                 rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
 257                 if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) {
 258                         printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
 259                         printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
 260                         lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;
 261                         wrmsr(MSR_IA32_MISC_ENABLE, lo, hi);
 262                 }
 263         }
 264
 265         /*
 266          * See if we have a good local APIC by checking for buggy Pentia,
 267          * i.e. all B steppings and the C2 stepping of P54C when using their
 268          * integrated APIC (see 11AP erratum in "Pentium Processor
 269          * Specification Update").
 270          */
 271         if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
 272             (c->x86_mask < 0x6 || c->x86_mask == 0xb))
 273                 set_cpu_cap(c, X86_FEATURE_11AP);
 274
 275
 276 #ifdef CONFIG_X86_INTEL_USERCOPY
 277         /*
 278          * Set up the preferred alignment for movsl bulk memory moves
 279          */
 280         switch (c->x86) {
 281         case 4:         /* 486: untested */
 282                 break;
 283         case 5:         /* Old Pentia: untested */
 284                 break;
 285         case 6:         /* PII/PIII only like movsl with 8-byte alignment */
 286                 movsl_mask.mask = 7;
 287                 break;
 288         case 15:        /* P4 is OK down to 8-byte alignment */
 289                 movsl_mask.mask = 7;
 290                 break;
 291         }
 292 #endif
 293
 294 #ifdef CONFIG_X86_NUMAQ
 295         numaq_tsc_disable();
 296 #endif
 297
 298         intel_smp_check(c);
 299 }
 300 #else
 301 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
 302 {
 303 }
 304 #endif
 305
 306 static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
 307 {
 308 #ifdef CONFIG_NUMA
 309         unsigned node;
 310         int cpu = smp_processor_id();
 311
 312         /* Don't do the funky fallback heuristics the AMD version employs
 313            for now. */
 314         node = numa_cpu_node(cpu);
 315         if (node == NUMA_NO_NODE || !node_online(node)) {
 316                 /* reuse the value from init_cpu_to_node() */
 317                 node = cpu_to_node(cpu);
 318         }
 319         numa_set_node(cpu, node);
 320 #endif
 321 }
 322
 323 /*
 324  * find out the number of processor cores on the die
 325  */
 326 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
 327 {
 328         unsigned int eax, ebx, ecx, edx;
 329
 330         if (c->cpuid_level < 4)
 331                 return 1;
 332
 333         /* Intel has a non-standard dependency on %ecx for this CPUID level. */
 334         cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
 335         if (eax & 0x1f)
 336                 return (eax >> 26) + 1;
 337         else
 338                 return 1;
 339 }
 340
 341 static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
 342 {
 343         /* Intel VMX MSR indicated features */
 344 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW    0x00200000
 345 #define X86_VMX_FEATURE_PROC_CTLS_VNMI          0x00400000
 346 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS      0x80000000
 347 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC    0x00000001
 348 #define X86_VMX_FEATURE_PROC_CTLS2_EPT          0x00000002
 349 #define X86_VMX_FEATURE_PROC_CTLS2_VPID         0x00000020
 350
 351         u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
 352
 353         clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
 354         clear_cpu_cap(c, X86_FEATURE_VNMI);
 355         clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
 356         clear_cpu_cap(c, X86_FEATURE_EPT);
 357         clear_cpu_cap(c, X86_FEATURE_VPID);
 358
 359         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
 360         msr_ctl = vmx_msr_high | vmx_msr_low;
 361         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
 362                 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
 363         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
 364                 set_cpu_cap(c, X86_FEATURE_VNMI);
 365         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
 366                 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
 367                       vmx_msr_low, vmx_msr_high);
 368                 msr_ctl2 = vmx_msr_high | vmx_msr_low;
 369                 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
 370                     (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
 371                         set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
 372                 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
 373                         set_cpu_cap(c, X86_FEATURE_EPT);
 374                 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
 375                         set_cpu_cap(c, X86_FEATURE_VPID);
 376         }
 377 }
 378
 379 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 380 {
 381         unsigned int l2 = 0;
 382
 383         early_init_intel(c);
 384
 385         intel_workarounds(c);
 386
 387         /*
 388          * Detect the extended topology information if available. This
 389          * will reinitialise the initial_apicid which will be used
 390          * in init_intel_cacheinfo()
 391          */
 392         detect_extended_topology(c);
 393
 394         l2 = init_intel_cacheinfo(c);
 395         if (c->cpuid_level > 9) {
 396                 unsigned eax = cpuid_eax(10);
 397                 /* Check for version and the number of counters */
 398                 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
 399                         set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
 400         }
 401
 402         if (cpu_has_xmm2)
 403                 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
 404         if (cpu_has_ds) {
 405                 unsigned int l1;
 406                 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
 407                 if (!(l1 & (1<<11)))
 408                         set_cpu_cap(c, X86_FEATURE_BTS);
 409                 if (!(l1 & (1<<12)))
 410                         set_cpu_cap(c, X86_FEATURE_PEBS);
 411         }
 412
 413         if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush)
 414                 set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);
 415
 416 #ifdef CONFIG_X86_64
 417         if (c->x86 == 15)
 418                 c->x86_cache_alignment = c->x86_clflush_size * 2;
 419         if (c->x86 == 6)
 420                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 421 #else
 422         /*
 423          * Names for the Pentium II/Celeron processors
 424          * detectable only by also checking the cache size.
 425          * Dixon is NOT a Celeron.
 426          */
 427         if (c->x86 == 6) {
 428                 char *p = NULL;
 429
 430                 switch (c->x86_model) {
 431                 case 5:
 432                         if (l2 == 0)
 433                                 p = "Celeron (Covington)";
 434                         else if (l2 == 256)
 435                                 p = "Mobile Pentium II (Dixon)";
 436                         break;
 437
 438                 case 6:
 439                         if (l2 == 128)
 440                                 p = "Celeron (Mendocino)";
 441                         else if (c->x86_mask == 0 || c->x86_mask == 5)
 442                                 p = "Celeron-A";
 443                         break;
 444
 445                 case 8:
 446                         if (l2 == 128)
 447                                 p = "Celeron (Coppermine)";
 448                         break;
 449                 }
 450
 451                 if (p)
 452                         strcpy(c->x86_model_id, p);
 453         }
 454
 455         if (c->x86 == 15)
 456                 set_cpu_cap(c, X86_FEATURE_P4);
 457         if (c->x86 == 6)
 458                 set_cpu_cap(c, X86_FEATURE_P3);
 459 #endif
 460
 461         if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
 462                 /*
 463                  * let's use the legacy cpuid vector 0x1 and 0x4 for topology
 464                  * detection.
 465                  */
 466                 c->x86_max_cores = intel_num_cpu_cores(c);
 467 #ifdef CONFIG_X86_32
 468                 detect_ht(c);
 469 #endif
 470         }
 471
 472         /* Work around errata */
 473         srat_detect_node(c);
 474
 475         if (cpu_has(c, X86_FEATURE_VMX))
 476                 detect_vmx_virtcap(c);
 477
 478         /*
 479          * Initialize MSR_IA32_ENERGY_PERF_BIAS if BIOS did not.
 480          * x86_energy_perf_policy(8) is available to change it at run-time
 481          */
 482         if (cpu_has(c, X86_FEATURE_EPB)) {
 483                 u64 epb;
 484
 485                 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
 486                 if ((epb & 0xF) == ENERGY_PERF_BIAS_PERFORMANCE) {
 487                         printk_once(KERN_WARNING "ENERGY_PERF_BIAS:"
 488                                 " Set to 'normal', was 'performance'\n"
 489                                 "ENERGY_PERF_BIAS: View and update with"
 490                                 " x86_energy_perf_policy(8)\n");
 491                         epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL;
 492                         wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
 493                 }
 494         }
 495
 496         /* Enable monitor/mwait if BIOS didn't do it for us. */
 497         if (!cpu_has(c, X86_FEATURE_MWAIT) && cpu_has(c, X86_FEATURE_XMM3)
 498             && c->x86 >= 6 && !(c->x86 == 6 && c->x86_model < 0x1c)
 499             && !(c->x86 == 0xf && c->x86_model < 3)) {
 500                 u64 misc_enable;
 501                 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
 502                 misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
 503
 504                 /*
 505                  * Some non-SSE3 cpus will #GP.  We check for that,
 506                  * but it can't hurt to be safe.
 507                  */
 508                 wrmsr_safe(MSR_IA32_MISC_ENABLE, (u32)misc_enable,
 509                            (u32)(misc_enable >> 32));
 510
 511                 /* Re-read monitor capability. */
 512                 if (cpuid_ecx(1) & 0x8) {
 513                         set_cpu_cap(c, X86_FEATURE_MWAIT);
 514
 515                         printk(KERN_WARNING FW_WARN "IA32_MISC_ENABLE.ENABLE_MONITOR_FSM was not set\n");
 516                 }
 517         }
 518 }
 519
 520 #ifdef CONFIG_X86_32
 521 static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
 522 {
 523         /*
 524          * Intel PIII Tualatin. This comes in two flavours.
 525          * One has 256kb of cache, the other 512. We have no way
 526          * to determine which, so we use a boottime override
 527          * for the 512kb model, and assume 256 otherwise.
 528          */
 529         if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
 530                 size = 256;
 531         return size;
 532 }
 533 #endif
 534
 535 static const struct cpu_dev __cpuinitconst intel_cpu_dev = {
 536         .c_vendor       = "Intel",
 537         .c_ident        = { "GenuineIntel" },
 538 #ifdef CONFIG_X86_32
 539         .c_models = {
 540                 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
 541                   {
 542                           [0] = "486 DX-25/33",
 543                           [1] = "486 DX-50",
 544                           [2] = "486 SX",
 545                           [3] = "486 DX/2",
 546                           [4] = "486 SL",
 547                           [5] = "486 SX/2",
 548                           [7] = "486 DX/2-WB",
 549                           [8] = "486 DX/4",
 550                           [9] = "486 DX/4-WB"
 551                   }
 552                 },
 553                 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
 554                   {
 555                           [0] = "Pentium 60/66 A-step",
 556                           [1] = "Pentium 60/66",
 557                           [2] = "Pentium 75 - 200",
 558                           [3] = "OverDrive PODP5V83",
 559                           [4] = "Pentium MMX",
 560                           [7] = "Mobile Pentium 75 - 200",
 561                           [8] = "Mobile Pentium MMX"
 562                   }
 563                 },
 564                 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
 565                   {
 566                           [0] = "Pentium Pro A-step",
 567                           [1] = "Pentium Pro",
 568                           [3] = "Pentium II (Klamath)",
 569                           [4] = "Pentium II (Deschutes)",
 570                           [5] = "Pentium II (Deschutes)",
 571                           [6] = "Mobile Pentium II",
 572                           [7] = "Pentium III (Katmai)",
 573                           [8] = "Pentium III (Coppermine)",
 574                           [10] = "Pentium III (Cascades)",
 575                           [11] = "Pentium III (Tualatin)",
 576                   }
 577                 },
 578                 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
 579                   {
 580                           [0] = "Pentium 4 (Unknown)",
 581                           [1] = "Pentium 4 (Willamette)",
 582                           [2] = "Pentium 4 (Northwood)",
 583                           [4] = "Pentium 4 (Foster)",
 584                           [5] = "Pentium 4 (Foster)",
 585                   }
 586                 },
 587         },
 588         .c_size_cache   = intel_size_cache,
 589 #endif
 590         .c_early_init   = early_init_intel,
 591         .c_init         = init_intel,
 592         .c_x86_vendor   = X86_VENDOR_INTEL,
 593 };
 594
 595 cpu_dev_register(intel_cpu_dev);
 596