drivers/gpu/drm/gma500/cdv_device.c

   1 /**************************************************************************
   2  * Copyright (c) 2011, Intel Corporation.
   3  * All Rights Reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  **************************************************************************/
  19
  20 #include <linux/backlight.h>
  21 #include <drm/drmP.h>
  22 #include <drm/drm.h>
  23 #include "gma_drm.h"
  24 #include "psb_drv.h"
  25 #include "psb_reg.h"
  26 #include "psb_intel_reg.h"
  27 #include "intel_bios.h"
  28 #include "cdv_device.h"
  29
  30 #define VGA_SR_INDEX            0x3c4
  31 #define VGA_SR_DATA             0x3c5
  32
  33 static void cdv_disable_vga(struct drm_device *dev)
  34 {
  35         u8 sr1;
  36         u32 vga_reg;
  37
  38         vga_reg = VGACNTRL;
  39
  40         outb(1, VGA_SR_INDEX);
  41         sr1 = inb(VGA_SR_DATA);
  42         outb(sr1 | 1<<5, VGA_SR_DATA);
  43         udelay(300);
  44
  45         REG_WRITE(vga_reg, VGA_DISP_DISABLE);
  46         REG_READ(vga_reg);
  47 }
  48
  49 static int cdv_output_init(struct drm_device *dev)
  50 {
  51         struct drm_psb_private *dev_priv = dev->dev_private;
  52         cdv_disable_vga(dev);
  53
  54         cdv_intel_crt_init(dev, &dev_priv->mode_dev);
  55         cdv_intel_lvds_init(dev, &dev_priv->mode_dev);
  56
  57         /* These bits indicate HDMI not SDVO on CDV, but we don't yet support
  58            the HDMI interface */
  59         if (REG_READ(SDVOB) & SDVO_DETECTED)
  60                 cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOB);
  61         if (REG_READ(SDVOC) & SDVO_DETECTED)
  62                 cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOC);
  63         return 0;
  64 }
  65
  66 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
  67
  68 /*
  69  *      Poulsbo Backlight Interfaces
  70  */
  71
  72 #define BLC_PWM_PRECISION_FACTOR 100    /* 10000000 */
  73 #define BLC_PWM_FREQ_CALC_CONSTANT 32
  74 #define MHz 1000000
  75
  76 #define PSB_BLC_PWM_PRECISION_FACTOR    10
  77 #define PSB_BLC_MAX_PWM_REG_FREQ        0xFFFE
  78 #define PSB_BLC_MIN_PWM_REG_FREQ        0x2
  79
  80 #define PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR (0xFFFE)
  81 #define PSB_BACKLIGHT_PWM_CTL_SHIFT     (16)
  82
  83 static int cdv_brightness;
  84 static struct backlight_device *cdv_backlight_device;
  85
  86 static int cdv_get_brightness(struct backlight_device *bd)
  87 {
  88         /* return locally cached var instead of HW read (due to DPST etc.) */
  89         /* FIXME: ideally return actual value in case firmware fiddled with
  90            it */
  91         return cdv_brightness;
  92 }
  93
  94
  95 static int cdv_backlight_setup(struct drm_device *dev)
  96 {
  97         struct drm_psb_private *dev_priv = dev->dev_private;
  98         unsigned long core_clock;
  99         /* u32 bl_max_freq; */
 100         /* unsigned long value; */
 101         u16 bl_max_freq;
 102         uint32_t value;
 103         uint32_t blc_pwm_precision_factor;
 104
 105         /* get bl_max_freq and pol from dev_priv*/
 106         if (!dev_priv->lvds_bl) {
 107                 dev_err(dev->dev, "Has no valid LVDS backlight info\n");
 108                 return -ENOENT;
 109         }
 110         bl_max_freq = dev_priv->lvds_bl->freq;
 111         blc_pwm_precision_factor = PSB_BLC_PWM_PRECISION_FACTOR;
 112
 113         core_clock = dev_priv->core_freq;
 114
 115         value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
 116         value *= blc_pwm_precision_factor;
 117         value /= bl_max_freq;
 118         value /= blc_pwm_precision_factor;
 119
 120         if (value > (unsigned long long)PSB_BLC_MAX_PWM_REG_FREQ ||
 121                  value < (unsigned long long)PSB_BLC_MIN_PWM_REG_FREQ)
 122                                 return -ERANGE;
 123         else {
 124                 /* FIXME */
 125         }
 126         return 0;
 127 }
 128
 129 static int cdv_set_brightness(struct backlight_device *bd)
 130 {
 131         int level = bd->props.brightness;
 132
 133         /* Percentage 1-100% being valid */
 134         if (level < 1)
 135                 level = 1;
 136
 137         /*cdv_intel_lvds_set_brightness(dev, level); FIXME */
 138         cdv_brightness = level;
 139         return 0;
 140 }
 141
 142 static const struct backlight_ops cdv_ops = {
 143         .get_brightness = cdv_get_brightness,
 144         .update_status  = cdv_set_brightness,
 145 };
 146
 147 static int cdv_backlight_init(struct drm_device *dev)
 148 {
 149         struct drm_psb_private *dev_priv = dev->dev_private;
 150         int ret;
 151         struct backlight_properties props;
 152
 153         memset(&props, 0, sizeof(struct backlight_properties));
 154         props.max_brightness = 100;
 155         props.type = BACKLIGHT_PLATFORM;
 156
 157         cdv_backlight_device = backlight_device_register("psb-bl",
 158                                         NULL, (void *)dev, &cdv_ops, &props);
 159         if (IS_ERR(cdv_backlight_device))
 160                 return PTR_ERR(cdv_backlight_device);
 161
 162         ret = cdv_backlight_setup(dev);
 163         if (ret < 0) {
 164                 backlight_device_unregister(cdv_backlight_device);
 165                 cdv_backlight_device = NULL;
 166                 return ret;
 167         }
 168         cdv_backlight_device->props.brightness = 100;
 169         cdv_backlight_device->props.max_brightness = 100;
 170         backlight_update_status(cdv_backlight_device);
 171         dev_priv->backlight_device = cdv_backlight_device;
 172         return 0;
 173 }
 174
 175 #endif
 176
 177 /*
 178  *      Provide the Cedarview specific chip logic and low level methods
 179  *      for power management
 180  *
 181  *      FIXME: we need to implement the apm/ospm base management bits
 182  *      for this and the MID devices.
 183  */
 184
 185 static inline u32 CDV_MSG_READ32(uint port, uint offset)
 186 {
 187         int mcr = (0x10<<24) | (port << 16) | (offset << 8);
 188         uint32_t ret_val = 0;
 189         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 190         pci_write_config_dword(pci_root, 0xD0, mcr);
 191         pci_read_config_dword(pci_root, 0xD4, &ret_val);
 192         pci_dev_put(pci_root);
 193         return ret_val;
 194 }
 195
 196 static inline void CDV_MSG_WRITE32(uint port, uint offset, u32 value)
 197 {
 198         int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
 199         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 200         pci_write_config_dword(pci_root, 0xD4, value);
 201         pci_write_config_dword(pci_root, 0xD0, mcr);
 202         pci_dev_put(pci_root);
 203 }
 204
 205 #define PSB_APM_CMD                     0x0
 206 #define PSB_APM_STS                     0x04
 207 #define PSB_PM_SSC                      0x20
 208 #define PSB_PM_SSS                      0x30
 209 #define PSB_PWRGT_GFX_MASK              0x3
 210 #define CDV_PWRGT_DISPLAY_CNTR          0x000fc00c
 211 #define CDV_PWRGT_DISPLAY_STS           0x000fc00c
 212
 213 static void cdv_init_pm(struct drm_device *dev)
 214 {
 215         struct drm_psb_private *dev_priv = dev->dev_private;
 216         u32 pwr_cnt;
 217         int i;
 218
 219         dev_priv->apm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
 220                                                         PSB_APMBA) & 0xFFFF;
 221         dev_priv->ospm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
 222                                                         PSB_OSPMBA) & 0xFFFF;
 223
 224         /* Force power on for now */
 225         pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
 226         pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
 227
 228         outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
 229         for (i = 0; i < 5; i++) {
 230                 u32 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
 231                 if ((pwr_sts & PSB_PWRGT_GFX_MASK) == 0)
 232                         break;
 233                 udelay(10);
 234         }
 235         pwr_cnt = inl(dev_priv->ospm_base + PSB_PM_SSC);
 236         pwr_cnt &= ~CDV_PWRGT_DISPLAY_CNTR;
 237         outl(pwr_cnt, dev_priv->ospm_base + PSB_PM_SSC);
 238         for (i = 0; i < 5; i++) {
 239                 u32 pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
 240                 if ((pwr_sts & CDV_PWRGT_DISPLAY_STS) == 0)
 241                         break;
 242                 udelay(10);
 243         }
 244 }
 245
 246 /**
 247  *      cdv_save_display_registers      -       save registers lost on suspend
 248  *      @dev: our DRM device
 249  *
 250  *      Save the state we need in order to be able to restore the interface
 251  *      upon resume from suspend
 252  *
 253  *      FIXME: review
 254  */
 255 static int cdv_save_display_registers(struct drm_device *dev)
 256 {
 257         return 0;
 258 }
 259
 260 /**
 261  *      cdv_restore_display_registers   -       restore lost register state
 262  *      @dev: our DRM device
 263  *
 264  *      Restore register state that was lost during suspend and resume.
 265  *
 266  *      FIXME: review
 267  */
 268 static int cdv_restore_display_registers(struct drm_device *dev)
 269 {
 270         return 0;
 271 }
 272
 273 static int cdv_power_down(struct drm_device *dev)
 274 {
 275         return 0;
 276 }
 277
 278 static int cdv_power_up(struct drm_device *dev)
 279 {
 280         return 0;
 281 }
 282
 283 /* FIXME ? - shared with Poulsbo */
 284 static void cdv_get_core_freq(struct drm_device *dev)
 285 {
 286         uint32_t clock;
 287         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 288         struct drm_psb_private *dev_priv = dev->dev_private;
 289
 290         pci_write_config_dword(pci_root, 0xD0, 0xD0050300);
 291         pci_read_config_dword(pci_root, 0xD4, &clock);
 292         pci_dev_put(pci_root);
 293
 294         switch (clock & 0x07) {
 295         case 0:
 296                 dev_priv->core_freq = 100;
 297                 break;
 298         case 1:
 299                 dev_priv->core_freq = 133;
 300                 break;
 301         case 2:
 302                 dev_priv->core_freq = 150;
 303                 break;
 304         case 3:
 305                 dev_priv->core_freq = 178;
 306                 break;
 307         case 4:
 308                 dev_priv->core_freq = 200;
 309                 break;
 310         case 5:
 311         case 6:
 312         case 7:
 313                 dev_priv->core_freq = 266;
 314         default:
 315                 dev_priv->core_freq = 0;
 316         }
 317 }
 318
 319 static int cdv_chip_setup(struct drm_device *dev)
 320 {
 321         cdv_get_core_freq(dev);
 322         gma_intel_opregion_init(dev);
 323         psb_intel_init_bios(dev);
 324         REG_WRITE(PORT_HOTPLUG_EN, 0);
 325         REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
 326         return 0;
 327 }
 328
 329 /* CDV is much like Poulsbo but has MID like SGX offsets and PM */
 330
 331 const struct psb_ops cdv_chip_ops = {
 332         .name = "GMA3600/3650",
 333         .accel_2d = 0,
 334         .pipes = 2,
 335         .crtcs = 2,
 336         .sgx_offset = MRST_SGX_OFFSET,
 337         .chip_setup = cdv_chip_setup,
 338
 339         .crtc_helper = &cdv_intel_helper_funcs,
 340         .crtc_funcs = &cdv_intel_crtc_funcs,
 341
 342         .output_init = cdv_output_init,
 343
 344 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
 345         .backlight_init = cdv_backlight_init,
 346 #endif
 347
 348         .init_pm = cdv_init_pm,
 349         .save_regs = cdv_save_display_registers,
 350         .restore_regs = cdv_restore_display_registers,
 351         .power_down = cdv_power_down,
 352         .power_up = cdv_power_up,
 353 };