drivers/gpu/drm/gma500/psb_irq.c

   1 /**************************************************************************
   2  * Copyright (c) 2007, Intel Corporation.
   3  * All Rights Reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
  19  * develop this driver.
  20  *
  21  **************************************************************************/
  22 /*
  23  */
  24
  25 #include <drm/drmP.h>
  26 #include "psb_drv.h"
  27 #include "psb_reg.h"
  28 #include "psb_intel_reg.h"
  29 #include "power.h"
  30
  31 /*
  32  * inline functions
  33  */
  34
  35 static inline u32
  36 psb_pipestat(int pipe)
  37 {
  38         if (pipe == 0)
  39                 return PIPEASTAT;
  40         if (pipe == 1)
  41                 return PIPEBSTAT;
  42         if (pipe == 2)
  43                 return PIPECSTAT;
  44         BUG();
  45 }
  46
  47 static inline u32
  48 mid_pipe_event(int pipe)
  49 {
  50         if (pipe == 0)
  51                 return _PSB_PIPEA_EVENT_FLAG;
  52         if (pipe == 1)
  53                 return _MDFLD_PIPEB_EVENT_FLAG;
  54         if (pipe == 2)
  55                 return _MDFLD_PIPEC_EVENT_FLAG;
  56         BUG();
  57 }
  58
  59 static inline u32
  60 mid_pipe_vsync(int pipe)
  61 {
  62         if (pipe == 0)
  63                 return _PSB_VSYNC_PIPEA_FLAG;
  64         if (pipe == 1)
  65                 return _PSB_VSYNC_PIPEB_FLAG;
  66         if (pipe == 2)
  67                 return _MDFLD_PIPEC_VBLANK_FLAG;
  68         BUG();
  69 }
  70
  71 static inline u32
  72 mid_pipeconf(int pipe)
  73 {
  74         if (pipe == 0)
  75                 return PIPEACONF;
  76         if (pipe == 1)
  77                 return PIPEBCONF;
  78         if (pipe == 2)
  79                 return PIPECCONF;
  80         BUG();
  81 }
  82
  83 void
  84 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
  85 {
  86         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  87                 u32 reg = psb_pipestat(pipe);
  88                 dev_priv->pipestat[pipe] |= mask;
  89                 /* Enable the interrupt, clear any pending status */
  90                 if (gma_power_begin(dev_priv->dev, false)) {
  91                         u32 writeVal = PSB_RVDC32(reg);
  92                         writeVal |= (mask | (mask >> 16));
  93                         PSB_WVDC32(writeVal, reg);
  94                         (void) PSB_RVDC32(reg);
  95                         gma_power_end(dev_priv->dev);
  96                 }
  97         }
  98 }
  99
 100 void
 101 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
 102 {
 103         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 104                 u32 reg = psb_pipestat(pipe);
 105                 dev_priv->pipestat[pipe] &= ~mask;
 106                 if (gma_power_begin(dev_priv->dev, false)) {
 107                         u32 writeVal = PSB_RVDC32(reg);
 108                         writeVal &= ~mask;
 109                         PSB_WVDC32(writeVal, reg);
 110                         (void) PSB_RVDC32(reg);
 111                         gma_power_end(dev_priv->dev);
 112                 }
 113         }
 114 }
 115
 116 void mid_enable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
 117 {
 118         if (gma_power_begin(dev_priv->dev, false)) {
 119                 u32 pipe_event = mid_pipe_event(pipe);
 120                 dev_priv->vdc_irq_mask |= pipe_event;
 121                 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 122                 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 123                 gma_power_end(dev_priv->dev);
 124         }
 125 }
 126
 127 void mid_disable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
 128 {
 129         if (dev_priv->pipestat[pipe] == 0) {
 130                 if (gma_power_begin(dev_priv->dev, false)) {
 131                         u32 pipe_event = mid_pipe_event(pipe);
 132                         dev_priv->vdc_irq_mask &= ~pipe_event;
 133                         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 134                         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 135                         gma_power_end(dev_priv->dev);
 136                 }
 137         }
 138 }
 139
 140 /**
 141  * Display controller interrupt handler for pipe event.
 142  *
 143  */
 144 static void mid_pipe_event_handler(struct drm_device *dev, int pipe)
 145 {
 146         struct drm_psb_private *dev_priv =
 147             (struct drm_psb_private *) dev->dev_private;
 148
 149         uint32_t pipe_stat_val = 0;
 150         uint32_t pipe_stat_reg = psb_pipestat(pipe);
 151         uint32_t pipe_enable = dev_priv->pipestat[pipe];
 152         uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16;
 153         uint32_t pipe_clear;
 154         uint32_t i = 0;
 155
 156         spin_lock(&dev_priv->irqmask_lock);
 157
 158         pipe_stat_val = PSB_RVDC32(pipe_stat_reg);
 159         pipe_stat_val &= pipe_enable | pipe_status;
 160         pipe_stat_val &= pipe_stat_val >> 16;
 161
 162         spin_unlock(&dev_priv->irqmask_lock);
 163
 164         /* Clear the 2nd level interrupt status bits
 165          * Sometimes the bits are very sticky so we repeat until they unstick */
 166         for (i = 0; i < 0xffff; i++) {
 167                 PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg);
 168                 pipe_clear = PSB_RVDC32(pipe_stat_reg) & pipe_status;
 169
 170                 if (pipe_clear == 0)
 171                         break;
 172         }
 173
 174         if (pipe_clear)
 175                 dev_err(dev->dev,
 176                 "%s, can't clear status bits for pipe %d, its value = 0x%x.\n",
 177                 __func__, pipe, PSB_RVDC32(pipe_stat_reg));
 178
 179         if (pipe_stat_val & PIPE_VBLANK_STATUS)
 180                 drm_handle_vblank(dev, pipe);
 181
 182         if (pipe_stat_val & PIPE_TE_STATUS)
 183                 drm_handle_vblank(dev, pipe);
 184 }
 185
 186 /*
 187  * Display controller interrupt handler.
 188  */
 189 static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat)
 190 {
 191         if (vdc_stat & _PSB_VSYNC_PIPEA_FLAG)
 192                 mid_pipe_event_handler(dev, 0);
 193
 194         if (vdc_stat & _PSB_VSYNC_PIPEB_FLAG)
 195                 mid_pipe_event_handler(dev, 1);
 196 }
 197
 198 irqreturn_t psb_irq_handler(DRM_IRQ_ARGS)
 199 {
 200         struct drm_device *dev = (struct drm_device *) arg;
 201         struct drm_psb_private *dev_priv =
 202             (struct drm_psb_private *) dev->dev_private;
 203
 204         uint32_t vdc_stat, dsp_int = 0, sgx_int = 0;
 205         int handled = 0;
 206
 207         spin_lock(&dev_priv->irqmask_lock);
 208
 209         vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R);
 210
 211         if (vdc_stat & _PSB_PIPE_EVENT_FLAG)
 212                 dsp_int = 1;
 213
 214         /* FIXME: Handle Medfield
 215         if (vdc_stat & _MDFLD_DISP_ALL_IRQ_FLAG)
 216                 dsp_int = 1;
 217         */
 218
 219         if (vdc_stat & _PSB_IRQ_SGX_FLAG)
 220                 sgx_int = 1;
 221
 222         vdc_stat &= dev_priv->vdc_irq_mask;
 223         spin_unlock(&dev_priv->irqmask_lock);
 224
 225         if (dsp_int && gma_power_is_on(dev)) {
 226                 psb_vdc_interrupt(dev, vdc_stat);
 227                 handled = 1;
 228         }
 229
 230         if (sgx_int) {
 231                 /* Not expected - we have it masked, shut it up */
 232                 u32 s, s2;
 233                 s = PSB_RSGX32(PSB_CR_EVENT_STATUS);
 234                 s2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
 235                 PSB_WSGX32(s, PSB_CR_EVENT_HOST_CLEAR);
 236                 PSB_WSGX32(s2, PSB_CR_EVENT_HOST_CLEAR2);
 237                 /* if s & _PSB_CE_TWOD_COMPLETE we have 2D done but
 238                    we may as well poll even if we add that ! */
 239                 handled = 1;
 240         }
 241
 242         PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R);
 243         (void) PSB_RVDC32(PSB_INT_IDENTITY_R);
 244         DRM_READMEMORYBARRIER();
 245
 246         if (!handled)
 247                 return IRQ_NONE;
 248
 249         return IRQ_HANDLED;
 250 }
 251
 252 void psb_irq_preinstall(struct drm_device *dev)
 253 {
 254         struct drm_psb_private *dev_priv =
 255             (struct drm_psb_private *) dev->dev_private;
 256         unsigned long irqflags;
 257
 258         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 259
 260         if (gma_power_is_on(dev))
 261                 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 262         if (dev->vblank_enabled[0])
 263                 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
 264         if (dev->vblank_enabled[1])
 265                 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
 266
 267         /* FIXME: Handle Medfield irq mask
 268         if (dev->vblank_enabled[1])
 269                 dev_priv->vdc_irq_mask |= _MDFLD_PIPEB_EVENT_FLAG;
 270         if (dev->vblank_enabled[2])
 271                 dev_priv->vdc_irq_mask |= _MDFLD_PIPEC_EVENT_FLAG;
 272         */
 273
 274         /* This register is safe even if display island is off */
 275         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 276         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 277 }
 278
 279 int psb_irq_postinstall(struct drm_device *dev)
 280 {
 281         struct drm_psb_private *dev_priv =
 282             (struct drm_psb_private *) dev->dev_private;
 283         unsigned long irqflags;
 284
 285         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 286
 287         /* This register is safe even if display island is off */
 288         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 289         PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 290
 291         if (dev->vblank_enabled[0])
 292                 psb_enable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
 293         else
 294                 psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
 295
 296         if (dev->vblank_enabled[1])
 297                 psb_enable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
 298         else
 299                 psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
 300
 301         if (dev->vblank_enabled[2])
 302                 psb_enable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
 303         else
 304                 psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
 305
 306         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 307         return 0;
 308 }
 309
 310 void psb_irq_uninstall(struct drm_device *dev)
 311 {
 312         struct drm_psb_private *dev_priv =
 313             (struct drm_psb_private *) dev->dev_private;
 314         unsigned long irqflags;
 315
 316         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 317
 318         PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 319
 320         if (dev->vblank_enabled[0])
 321                 psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
 322
 323         if (dev->vblank_enabled[1])
 324                 psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
 325
 326         if (dev->vblank_enabled[2])
 327                 psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
 328
 329         dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG |
 330                                   _PSB_IRQ_MSVDX_FLAG |
 331                                   _LNC_IRQ_TOPAZ_FLAG;
 332
 333         /* These two registers are safe even if display island is off */
 334         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 335         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 336
 337         wmb();
 338
 339         /* This register is safe even if display island is off */
 340         PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R);
 341         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 342 }
 343
 344 void psb_irq_turn_on_dpst(struct drm_device *dev)
 345 {
 346         struct drm_psb_private *dev_priv =
 347                 (struct drm_psb_private *) dev->dev_private;
 348         u32 hist_reg;
 349         u32 pwm_reg;
 350
 351         if (gma_power_begin(dev, false)) {
 352                 PSB_WVDC32(1 << 31, HISTOGRAM_LOGIC_CONTROL);
 353                 hist_reg = PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
 354                 PSB_WVDC32(1 << 31, HISTOGRAM_INT_CONTROL);
 355                 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
 356
 357                 PSB_WVDC32(0x80010100, PWM_CONTROL_LOGIC);
 358                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 359                 PSB_WVDC32(pwm_reg | PWM_PHASEIN_ENABLE
 360                                                 | PWM_PHASEIN_INT_ENABLE,
 361                                                            PWM_CONTROL_LOGIC);
 362                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 363
 364                 psb_enable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
 365
 366                 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
 367                 PSB_WVDC32(hist_reg | HISTOGRAM_INT_CTRL_CLEAR,
 368                                                         HISTOGRAM_INT_CONTROL);
 369                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 370                 PSB_WVDC32(pwm_reg | 0x80010100 | PWM_PHASEIN_ENABLE,
 371                                                         PWM_CONTROL_LOGIC);
 372
 373                 gma_power_end(dev);
 374         }
 375 }
 376
 377 int psb_irq_enable_dpst(struct drm_device *dev)
 378 {
 379         struct drm_psb_private *dev_priv =
 380                 (struct drm_psb_private *) dev->dev_private;
 381         unsigned long irqflags;
 382
 383         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 384
 385         /* enable DPST */
 386         mid_enable_pipe_event(dev_priv, 0);
 387         psb_irq_turn_on_dpst(dev);
 388
 389         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 390         return 0;
 391 }
 392
 393 void psb_irq_turn_off_dpst(struct drm_device *dev)
 394 {
 395         struct drm_psb_private *dev_priv =
 396             (struct drm_psb_private *) dev->dev_private;
 397         u32 hist_reg;
 398         u32 pwm_reg;
 399
 400         if (gma_power_begin(dev, false)) {
 401                 PSB_WVDC32(0x00000000, HISTOGRAM_INT_CONTROL);
 402                 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
 403
 404                 psb_disable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
 405
 406                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 407                 PSB_WVDC32(pwm_reg & !(PWM_PHASEIN_INT_ENABLE),
 408                                                         PWM_CONTROL_LOGIC);
 409                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 410
 411                 gma_power_end(dev);
 412         }
 413 }
 414
 415 int psb_irq_disable_dpst(struct drm_device *dev)
 416 {
 417         struct drm_psb_private *dev_priv =
 418             (struct drm_psb_private *) dev->dev_private;
 419         unsigned long irqflags;
 420
 421         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 422
 423         mid_disable_pipe_event(dev_priv, 0);
 424         psb_irq_turn_off_dpst(dev);
 425
 426         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 427
 428         return 0;
 429 }
 430
 431 #ifdef PSB_FIXME
 432 static int psb_vblank_do_wait(struct drm_device *dev,
 433                               unsigned int *sequence, atomic_t *counter)
 434 {
 435         unsigned int cur_vblank;
 436         int ret = 0;
 437         DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
 438                     (((cur_vblank = atomic_read(counter))
 439                       - *sequence) <= (1 << 23)));
 440         *sequence = cur_vblank;
 441
 442         return ret;
 443 }
 444 #endif
 445
 446 /*
 447  * It is used to enable VBLANK interrupt
 448  */
 449 int psb_enable_vblank(struct drm_device *dev, int pipe)
 450 {
 451         struct drm_psb_private *dev_priv = dev->dev_private;
 452         unsigned long irqflags;
 453         uint32_t reg_val = 0;
 454         uint32_t pipeconf_reg = mid_pipeconf(pipe);
 455
 456         if (gma_power_begin(dev, false)) {
 457                 reg_val = REG_READ(pipeconf_reg);
 458                 gma_power_end(dev);
 459         }
 460
 461         if (!(reg_val & PIPEACONF_ENABLE))
 462                 return -EINVAL;
 463
 464         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 465
 466         if (pipe == 0)
 467                 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
 468         else if (pipe == 1)
 469                 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
 470
 471         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 472         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 473         psb_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
 474
 475         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 476
 477         return 0;
 478 }
 479
 480 /*
 481  * It is used to disable VBLANK interrupt
 482  */
 483 void psb_disable_vblank(struct drm_device *dev, int pipe)
 484 {
 485         struct drm_psb_private *dev_priv = dev->dev_private;
 486         unsigned long irqflags;
 487
 488         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 489
 490         if (pipe == 0)
 491                 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEA_FLAG;
 492         else if (pipe == 1)
 493                 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEB_FLAG;
 494
 495         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 496         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 497         psb_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
 498
 499         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 500 }
 501
 502 /* Called from drm generic code, passed a 'crtc', which
 503  * we use as a pipe index
 504  */
 505 u32 psb_get_vblank_counter(struct drm_device *dev, int pipe)
 506 {
 507         uint32_t high_frame = PIPEAFRAMEHIGH;
 508         uint32_t low_frame = PIPEAFRAMEPIXEL;
 509         uint32_t pipeconf_reg = PIPEACONF;
 510         uint32_t reg_val = 0;
 511         uint32_t high1 = 0, high2 = 0, low = 0, count = 0;
 512
 513         switch (pipe) {
 514         case 0:
 515                 break;
 516         case 1:
 517                 high_frame = PIPEBFRAMEHIGH;
 518                 low_frame = PIPEBFRAMEPIXEL;
 519                 pipeconf_reg = PIPEBCONF;
 520                 break;
 521         case 2:
 522                 high_frame = PIPECFRAMEHIGH;
 523                 low_frame = PIPECFRAMEPIXEL;
 524                 pipeconf_reg = PIPECCONF;
 525                 break;
 526         default:
 527                 dev_err(dev->dev, "%s, invalid pipe.\n", __func__);
 528                 return 0;
 529         }
 530
 531         if (!gma_power_begin(dev, false))
 532                 return 0;
 533
 534         reg_val = REG_READ(pipeconf_reg);
 535
 536         if (!(reg_val & PIPEACONF_ENABLE)) {
 537                 dev_err(dev->dev, "trying to get vblank count for disabled pipe %d\n",
 538                                                                 pipe);
 539                 goto psb_get_vblank_counter_exit;
 540         }
 541
 542         /*
 543          * High & low register fields aren't synchronized, so make sure
 544          * we get a low value that's stable across two reads of the high
 545          * register.
 546          */
 547         do {
 548                 high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 549                          PIPE_FRAME_HIGH_SHIFT);
 550                 low =  ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 551                         PIPE_FRAME_LOW_SHIFT);
 552                 high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 553                          PIPE_FRAME_HIGH_SHIFT);
 554         } while (high1 != high2);
 555
 556         count = (high1 << 8) | low;
 557
 558 psb_get_vblank_counter_exit:
 559
 560         gma_power_end(dev);
 561
 562         return count;
 563 }
 564