drivers/gpu/drm/nouveau/nv50_vm.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include "drmP.h"
  26
  27 #include "nouveau_drv.h"
  28 #include "nouveau_vm.h"
  29
  30 void
  31 nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde,
  32                 struct nouveau_gpuobj *pgt[2])
  33 {
  34         u64 phys = 0xdeadcafe00000000ULL;
  35         u32 coverage = 0;
  36
  37         if (pgt[0]) {
  38                 phys = 0x00000003 | pgt[0]->vinst; /* present, 4KiB pages */
  39                 coverage = (pgt[0]->size >> 3) << 12;
  40         } else
  41         if (pgt[1]) {
  42                 phys = 0x00000001 | pgt[1]->vinst; /* present */
  43                 coverage = (pgt[1]->size >> 3) << 16;
  44         }
  45
  46         if (phys & 1) {
  47                 if (coverage <= 32 * 1024 * 1024)
  48                         phys |= 0x60;
  49                 else if (coverage <= 64 * 1024 * 1024)
  50                         phys |= 0x40;
  51                 else if (coverage <= 128 * 1024 * 1024)
  52                         phys |= 0x20;
  53         }
  54
  55         nv_wo32(pgd, (pde * 8) + 0, lower_32_bits(phys));
  56         nv_wo32(pgd, (pde * 8) + 4, upper_32_bits(phys));
  57 }
  58
  59 static inline u64
  60 nv50_vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target)
  61 {
  62         struct drm_nouveau_private *dev_priv = vma->vm->dev->dev_private;
  63
  64         phys |= 1; /* present */
  65         phys |= (u64)memtype << 40;
  66
  67         /* IGPs don't have real VRAM, re-target to stolen system memory */
  68         if (target == 0 && dev_priv->vram_sys_base) {
  69                 phys  += dev_priv->vram_sys_base;
  70                 target = 3;
  71         }
  72
  73         phys |= target << 4;
  74
  75         if (vma->access & NV_MEM_ACCESS_SYS)
  76                 phys |= (1 << 6);
  77
  78         if (!(vma->access & NV_MEM_ACCESS_WO))
  79                 phys |= (1 << 3);
  80
  81         return phys;
  82 }
  83
  84 void
  85 nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
  86             struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta)
  87 {
  88         u32 comp = (mem->memtype & 0x180) >> 7;
  89         u32 block;
  90         int i;
  91
  92         phys  = nv50_vm_addr(vma, phys, mem->memtype, 0);
  93         pte <<= 3;
  94         cnt <<= 3;
  95
  96         while (cnt) {
  97                 u32 offset_h = upper_32_bits(phys);
  98                 u32 offset_l = lower_32_bits(phys);
  99
 100                 for (i = 7; i >= 0; i--) {
 101                         block = 1 << (i + 3);
 102                         if (cnt >= block && !(pte & (block - 1)))
 103                                 break;
 104                 }
 105                 offset_l |= (i << 7);
 106
 107                 phys += block << (vma->node->type - 3);
 108                 cnt  -= block;
 109                 if (comp) {
 110                         u32 tag = mem->tag->start + ((delta >> 16) * comp);
 111                         offset_h |= (tag << 17);
 112                         delta    += block << (vma->node->type - 3);
 113                 }
 114
 115                 while (block) {
 116                         nv_wo32(pgt, pte + 0, offset_l);
 117                         nv_wo32(pgt, pte + 4, offset_h);
 118                         pte += 8;
 119                         block -= 8;
 120                 }
 121         }
 122 }
 123
 124 void
 125 nv50_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
 126                struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
 127 {
 128         pte <<= 3;
 129         while (cnt--) {
 130                 u64 phys = nv50_vm_addr(vma, (u64)*list++, mem->memtype, 2);
 131                 nv_wo32(pgt, pte + 0, lower_32_bits(phys));
 132                 nv_wo32(pgt, pte + 4, upper_32_bits(phys));
 133                 pte += 8;
 134         }
 135 }
 136
 137 void
 138 nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
 139 {
 140         pte <<= 3;
 141         while (cnt--) {
 142                 nv_wo32(pgt, pte + 0, 0x00000000);
 143                 nv_wo32(pgt, pte + 4, 0x00000000);
 144                 pte += 8;
 145         }
 146 }
 147
 148 void
 149 nv50_vm_flush(struct nouveau_vm *vm)
 150 {
 151         struct drm_nouveau_private *dev_priv = vm->dev->dev_private;
 152         struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
 153         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 154         int i;
 155
 156         pinstmem->flush(vm->dev);
 157
 158         /* BAR */
 159         if (vm == dev_priv->bar1_vm || vm == dev_priv->bar3_vm) {
 160                 nv50_vm_flush_engine(vm->dev, 6);
 161                 return;
 162         }
 163
 164         pfifo->tlb_flush(vm->dev);
 165         for (i = 0; i < NVOBJ_ENGINE_NR; i++) {
 166                 if (atomic_read(&vm->engref[i]))
 167                         dev_priv->eng[i]->tlb_flush(vm->dev, i);
 168         }
 169 }
 170
 171 void
 172 nv50_vm_flush_engine(struct drm_device *dev, int engine)
 173 {
 174         struct drm_nouveau_private *dev_priv = dev->dev_private;
 175         unsigned long flags;
 176
 177         spin_lock_irqsave(&dev_priv->vm_lock, flags);
 178         nv_wr32(dev, 0x100c80, (engine << 16) | 1);
 179         if (!nv_wait(dev, 0x100c80, 0x00000001, 0x00000000))
 180                 NV_ERROR(dev, "vm flush timeout: engine %d\n", engine);
 181         spin_unlock_irqrestore(&dev_priv->vm_lock, flags);
 182 }