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Merge tag 'v3.3.7' into 3.3/master
[zen-stable.git] / drivers / gpu / drm / radeon / r600_cs.c
blob387fcc9f03ef242011fe7dba4dbb447902db3583
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/kernel.h>
29 #include "drmP.h"
30 #include "radeon.h"
31 #include "r600d.h"
32 #include "r600_reg_safe.h"
33
34 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
35 struct radeon_cs_reloc **cs_reloc);
36 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
37 struct radeon_cs_reloc **cs_reloc);
38 typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
39 static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
40 extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
41
42
43 struct r600_cs_track {
44 /* configuration we miror so that we use same code btw kms/ums */
45 u32 group_size;
46 u32 nbanks;
47 u32 npipes;
48 /* value we track */
49 u32 sq_config;
50 u32 nsamples;
51 u32 cb_color_base_last[8];
52 struct radeon_bo *cb_color_bo[8];
53 u64 cb_color_bo_mc[8];
54 u32 cb_color_bo_offset[8];
55 struct radeon_bo *cb_color_frag_bo[8];
56 struct radeon_bo *cb_color_tile_bo[8];
57 u32 cb_color_info[8];
58 u32 cb_color_size_idx[8];
59 u32 cb_target_mask;
60 u32 cb_shader_mask;
61 u32 cb_color_size[8];
62 u32 vgt_strmout_en;
63 u32 vgt_strmout_buffer_en;
64 u32 db_depth_control;
65 u32 db_depth_info;
66 u32 db_depth_size_idx;
67 u32 db_depth_view;
68 u32 db_depth_size;
69 u32 db_offset;
70 struct radeon_bo *db_bo;
71 u64 db_bo_mc;
72 };
73
74 #define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc, CHIP_R600 }
75 #define FMT_16_BIT(fmt, vc) [fmt] = { 1, 1, 2, vc, CHIP_R600 }
76 #define FMT_24_BIT(fmt) [fmt] = { 1, 1, 3, 0, CHIP_R600 }
77 #define FMT_32_BIT(fmt, vc) [fmt] = { 1, 1, 4, vc, CHIP_R600 }
78 #define FMT_48_BIT(fmt) [fmt] = { 1, 1, 6, 0, CHIP_R600 }
79 #define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc, CHIP_R600 }
80 #define FMT_96_BIT(fmt) [fmt] = { 1, 1, 12, 0, CHIP_R600 }
81 #define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16,vc, CHIP_R600 }
82
83 struct gpu_formats {
84 unsigned blockwidth;
85 unsigned blockheight;
86 unsigned blocksize;
87 unsigned valid_color;
88 enum radeon_family min_family;
89 };
90
91 static const struct gpu_formats color_formats_table[] = {
92 /* 8 bit */
93 FMT_8_BIT(V_038004_COLOR_8, 1),
94 FMT_8_BIT(V_038004_COLOR_4_4, 1),
95 FMT_8_BIT(V_038004_COLOR_3_3_2, 1),
96 FMT_8_BIT(V_038004_FMT_1, 0),
97
98 /* 16-bit */
99 FMT_16_BIT(V_038004_COLOR_16, 1),
100 FMT_16_BIT(V_038004_COLOR_16_FLOAT, 1),
101 FMT_16_BIT(V_038004_COLOR_8_8, 1),
102 FMT_16_BIT(V_038004_COLOR_5_6_5, 1),
103 FMT_16_BIT(V_038004_COLOR_6_5_5, 1),
104 FMT_16_BIT(V_038004_COLOR_1_5_5_5, 1),
105 FMT_16_BIT(V_038004_COLOR_4_4_4_4, 1),
106 FMT_16_BIT(V_038004_COLOR_5_5_5_1, 1),
107
108 /* 24-bit */
109 FMT_24_BIT(V_038004_FMT_8_8_8),
110
111 /* 32-bit */
112 FMT_32_BIT(V_038004_COLOR_32, 1),
113 FMT_32_BIT(V_038004_COLOR_32_FLOAT, 1),
114 FMT_32_BIT(V_038004_COLOR_16_16, 1),
115 FMT_32_BIT(V_038004_COLOR_16_16_FLOAT, 1),
116 FMT_32_BIT(V_038004_COLOR_8_24, 1),
117 FMT_32_BIT(V_038004_COLOR_8_24_FLOAT, 1),
118 FMT_32_BIT(V_038004_COLOR_24_8, 1),
119 FMT_32_BIT(V_038004_COLOR_24_8_FLOAT, 1),
120 FMT_32_BIT(V_038004_COLOR_10_11_11, 1),
121 FMT_32_BIT(V_038004_COLOR_10_11_11_FLOAT, 1),
122 FMT_32_BIT(V_038004_COLOR_11_11_10, 1),
123 FMT_32_BIT(V_038004_COLOR_11_11_10_FLOAT, 1),
124 FMT_32_BIT(V_038004_COLOR_2_10_10_10, 1),
125 FMT_32_BIT(V_038004_COLOR_8_8_8_8, 1),
126 FMT_32_BIT(V_038004_COLOR_10_10_10_2, 1),
127 FMT_32_BIT(V_038004_FMT_5_9_9_9_SHAREDEXP, 0),
128 FMT_32_BIT(V_038004_FMT_32_AS_8, 0),
129 FMT_32_BIT(V_038004_FMT_32_AS_8_8, 0),
130
131 /* 48-bit */
132 FMT_48_BIT(V_038004_FMT_16_16_16),
133 FMT_48_BIT(V_038004_FMT_16_16_16_FLOAT),
134
135 /* 64-bit */
136 FMT_64_BIT(V_038004_COLOR_X24_8_32_FLOAT, 1),
137 FMT_64_BIT(V_038004_COLOR_32_32, 1),
138 FMT_64_BIT(V_038004_COLOR_32_32_FLOAT, 1),
139 FMT_64_BIT(V_038004_COLOR_16_16_16_16, 1),
140 FMT_64_BIT(V_038004_COLOR_16_16_16_16_FLOAT, 1),
141
142 FMT_96_BIT(V_038004_FMT_32_32_32),
143 FMT_96_BIT(V_038004_FMT_32_32_32_FLOAT),
144
145 /* 128-bit */
146 FMT_128_BIT(V_038004_COLOR_32_32_32_32, 1),
147 FMT_128_BIT(V_038004_COLOR_32_32_32_32_FLOAT, 1),
148
149 [V_038004_FMT_GB_GR] = { 2, 1, 4, 0 },
150 [V_038004_FMT_BG_RG] = { 2, 1, 4, 0 },
151
152 /* block compressed formats */
153 [V_038004_FMT_BC1] = { 4, 4, 8, 0 },
154 [V_038004_FMT_BC2] = { 4, 4, 16, 0 },
155 [V_038004_FMT_BC3] = { 4, 4, 16, 0 },
156 [V_038004_FMT_BC4] = { 4, 4, 8, 0 },
157 [V_038004_FMT_BC5] = { 4, 4, 16, 0},
158 [V_038004_FMT_BC6] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
159 [V_038004_FMT_BC7] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
160
161 /* The other Evergreen formats */
162 [V_038004_FMT_32_AS_32_32_32_32] = { 1, 1, 4, 0, CHIP_CEDAR},
163 };
164
165 static bool fmt_is_valid_color(u32 format)
166 {
167 if (format >= ARRAY_SIZE(color_formats_table))
168 return false;
169
170 if (color_formats_table[format].valid_color)
171 return true;
172
173 return false;
174 }
175
176 static bool fmt_is_valid_texture(u32 format, enum radeon_family family)
177 {
178 if (format >= ARRAY_SIZE(color_formats_table))
179 return false;
180
181 if (family < color_formats_table[format].min_family)
182 return false;
183
184 if (color_formats_table[format].blockwidth > 0)
185 return true;
186
187 return false;
188 }
189
190 static int fmt_get_blocksize(u32 format)
191 {
192 if (format >= ARRAY_SIZE(color_formats_table))
193 return 0;
194
195 return color_formats_table[format].blocksize;
196 }
197
198 static int fmt_get_nblocksx(u32 format, u32 w)
199 {
200 unsigned bw;
201
202 if (format >= ARRAY_SIZE(color_formats_table))
203 return 0;
204
205 bw = color_formats_table[format].blockwidth;
206 if (bw == 0)
207 return 0;
208
209 return (w + bw - 1) / bw;
210 }
211
212 static int fmt_get_nblocksy(u32 format, u32 h)
213 {
214 unsigned bh;
215
216 if (format >= ARRAY_SIZE(color_formats_table))
217 return 0;
218
219 bh = color_formats_table[format].blockheight;
220 if (bh == 0)
221 return 0;
222
223 return (h + bh - 1) / bh;
224 }
225
226 struct array_mode_checker {
227 int array_mode;
228 u32 group_size;
229 u32 nbanks;
230 u32 npipes;
231 u32 nsamples;
232 u32 blocksize;
233 };
234
235 /* returns alignment in pixels for pitch/height/depth and bytes for base */
236 static int r600_get_array_mode_alignment(struct array_mode_checker *values,
237 u32 *pitch_align,
238 u32 *height_align,
239 u32 *depth_align,
240 u64 *base_align)
241 {
242 u32 tile_width = 8;
243 u32 tile_height = 8;
244 u32 macro_tile_width = values->nbanks;
245 u32 macro_tile_height = values->npipes;
246 u32 tile_bytes = tile_width * tile_height * values->blocksize * values->nsamples;
247 u32 macro_tile_bytes = macro_tile_width * macro_tile_height * tile_bytes;
248
249 switch (values->array_mode) {
250 case ARRAY_LINEAR_GENERAL:
251 /* technically tile_width/_height for pitch/height */
252 *pitch_align = 1; /* tile_width */
253 *height_align = 1; /* tile_height */
254 *depth_align = 1;
255 *base_align = 1;
256 break;
257 case ARRAY_LINEAR_ALIGNED:
258 *pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize));
259 *height_align = tile_height;
260 *depth_align = 1;
261 *base_align = values->group_size;
262 break;
263 case ARRAY_1D_TILED_THIN1:
264 *pitch_align = max((u32)tile_width,
265 (u32)(values->group_size /
266 (tile_height * values->blocksize * values->nsamples)));
267 *height_align = tile_height;
268 *depth_align = 1;
269 *base_align = values->group_size;
270 break;
271 case ARRAY_2D_TILED_THIN1:
272 *pitch_align = max((u32)macro_tile_width,
273 (u32)(((values->group_size / tile_height) /
274 (values->blocksize * values->nsamples)) *
275 values->nbanks)) * tile_width;
276 *height_align = macro_tile_height * tile_height;
277 *depth_align = 1;
278 *base_align = max(macro_tile_bytes,
279 (*pitch_align) * values->blocksize * (*height_align) * values->nsamples);
280 break;
281 default:
282 return -EINVAL;
283 }
284
285 return 0;
286 }
287
288 static void r600_cs_track_init(struct r600_cs_track *track)
289 {
290 int i;
291
292 /* assume DX9 mode */
293 track->sq_config = DX9_CONSTS;
294 for (i = 0; i < 8; i++) {
295 track->cb_color_base_last[i] = 0;
296 track->cb_color_size[i] = 0;
297 track->cb_color_size_idx[i] = 0;
298 track->cb_color_info[i] = 0;
299 track->cb_color_bo[i] = NULL;
300 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
301 track->cb_color_bo_mc[i] = 0xFFFFFFFF;
302 }
303 track->cb_target_mask = 0xFFFFFFFF;
304 track->cb_shader_mask = 0xFFFFFFFF;
305 track->db_bo = NULL;
306 track->db_bo_mc = 0xFFFFFFFF;
307 /* assume the biggest format and that htile is enabled */
308 track->db_depth_info = 7 | (1 << 25);
309 track->db_depth_view = 0xFFFFC000;
310 track->db_depth_size = 0xFFFFFFFF;
311 track->db_depth_size_idx = 0;
312 track->db_depth_control = 0xFFFFFFFF;
313 }
314
315 static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
316 {
317 struct r600_cs_track *track = p->track;
318 u32 slice_tile_max, size, tmp;
319 u32 height, height_align, pitch, pitch_align, depth_align;
320 u64 base_offset, base_align;
321 struct array_mode_checker array_check;
322 volatile u32 *ib = p->ib->ptr;
323 unsigned array_mode;
324 u32 format;
325 if (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
326 dev_warn(p->dev, "FMASK or CMASK buffer are not supported by this kernel\n");
327 return -EINVAL;
328 }
329 size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
330 format = G_0280A0_FORMAT(track->cb_color_info[i]);
331 if (!fmt_is_valid_color(format)) {
332 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
333 __func__, __LINE__, format,
334 i, track->cb_color_info[i]);
335 return -EINVAL;
336 }
337 /* pitch in pixels */
338 pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8;
339 slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
340 slice_tile_max *= 64;
341 height = slice_tile_max / pitch;
342 if (height > 8192)
343 height = 8192;
344 array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]);
345
346 base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i];
347 array_check.array_mode = array_mode;
348 array_check.group_size = track->group_size;
349 array_check.nbanks = track->nbanks;
350 array_check.npipes = track->npipes;
351 array_check.nsamples = track->nsamples;
352 array_check.blocksize = fmt_get_blocksize(format);
353 if (r600_get_array_mode_alignment(&array_check,
354 &pitch_align, &height_align, &depth_align, &base_align)) {
355 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
356 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
357 track->cb_color_info[i]);
358 return -EINVAL;
359 }
360 switch (array_mode) {
361 case V_0280A0_ARRAY_LINEAR_GENERAL:
362 break;
363 case V_0280A0_ARRAY_LINEAR_ALIGNED:
364 break;
365 case V_0280A0_ARRAY_1D_TILED_THIN1:
366 /* avoid breaking userspace */
367 if (height > 7)
368 height &= ~0x7;
369 break;
370 case V_0280A0_ARRAY_2D_TILED_THIN1:
371 break;
372 default:
373 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
374 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
375 track->cb_color_info[i]);
376 return -EINVAL;
377 }
378
379 if (!IS_ALIGNED(pitch, pitch_align)) {
380 dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n",
381 __func__, __LINE__, pitch, pitch_align, array_mode);
382 return -EINVAL;
383 }
384 if (!IS_ALIGNED(height, height_align)) {
385 dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n",
386 __func__, __LINE__, height, height_align, array_mode);
387 return -EINVAL;
388 }
389 if (!IS_ALIGNED(base_offset, base_align)) {
390 dev_warn(p->dev, "%s offset[%d] 0x%llx 0x%llx, %d not aligned\n", __func__, i,
391 base_offset, base_align, array_mode);
392 return -EINVAL;
393 }
394
395 /* check offset */
396 tmp = fmt_get_nblocksy(format, height) * fmt_get_nblocksx(format, pitch) * fmt_get_blocksize(format);
397 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
398 if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) {
399 /* the initial DDX does bad things with the CB size occasionally */
400 /* it rounds up height too far for slice tile max but the BO is smaller */
401 /* r600c,g also seem to flush at bad times in some apps resulting in
402 * bogus values here. So for linear just allow anything to avoid breaking
403 * broken userspace.
404 */
405 } else {
406 dev_warn(p->dev, "%s offset[%d] %d %d %d %lu too big\n", __func__, i,
407 array_mode,
408 track->cb_color_bo_offset[i], tmp,
409 radeon_bo_size(track->cb_color_bo[i]));
410 return -EINVAL;
411 }
412 }
413 /* limit max tile */
414 tmp = (height * pitch) >> 6;
415 if (tmp < slice_tile_max)
416 slice_tile_max = tmp;
417 tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) |
418 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
419 ib[track->cb_color_size_idx[i]] = tmp;
420 return 0;
421 }
422
423 static int r600_cs_track_check(struct radeon_cs_parser *p)
424 {
425 struct r600_cs_track *track = p->track;
426 u32 tmp;
427 int r, i;
428 volatile u32 *ib = p->ib->ptr;
429
430 /* on legacy kernel we don't perform advanced check */
431 if (p->rdev == NULL)
432 return 0;
433 /* we don't support out buffer yet */
434 if (track->vgt_strmout_en || track->vgt_strmout_buffer_en) {
435 dev_warn(p->dev, "this kernel doesn't support SMX output buffer\n");
436 return -EINVAL;
437 }
438 /* check that we have a cb for each enabled target, we don't check
439 * shader_mask because it seems mesa isn't always setting it :(
440 */
441 tmp = track->cb_target_mask;
442 for (i = 0; i < 8; i++) {
443 if ((tmp >> (i * 4)) & 0xF) {
444 /* at least one component is enabled */
445 if (track->cb_color_bo[i] == NULL) {
446 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
447 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
448 return -EINVAL;
449 }
450 /* perform rewrite of CB_COLOR[0-7]_SIZE */
451 r = r600_cs_track_validate_cb(p, i);
452 if (r)
453 return r;
454 }
455 }
456 /* Check depth buffer */
457 if (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
458 G_028800_Z_ENABLE(track->db_depth_control)) {
459 u32 nviews, bpe, ntiles, size, slice_tile_max;
460 u32 height, height_align, pitch, pitch_align, depth_align;
461 u64 base_offset, base_align;
462 struct array_mode_checker array_check;
463 int array_mode;
464
465 if (track->db_bo == NULL) {
466 dev_warn(p->dev, "z/stencil with no depth buffer\n");
467 return -EINVAL;
468 }
469 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
470 dev_warn(p->dev, "this kernel doesn't support z/stencil htile\n");
471 return -EINVAL;
472 }
473 switch (G_028010_FORMAT(track->db_depth_info)) {
474 case V_028010_DEPTH_16:
475 bpe = 2;
476 break;
477 case V_028010_DEPTH_X8_24:
478 case V_028010_DEPTH_8_24:
479 case V_028010_DEPTH_X8_24_FLOAT:
480 case V_028010_DEPTH_8_24_FLOAT:
481 case V_028010_DEPTH_32_FLOAT:
482 bpe = 4;
483 break;
484 case V_028010_DEPTH_X24_8_32_FLOAT:
485 bpe = 8;
486 break;
487 default:
488 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
489 return -EINVAL;
490 }
491 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
492 if (!track->db_depth_size_idx) {
493 dev_warn(p->dev, "z/stencil buffer size not set\n");
494 return -EINVAL;
495 }
496 tmp = radeon_bo_size(track->db_bo) - track->db_offset;
497 tmp = (tmp / bpe) >> 6;
498 if (!tmp) {
499 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
500 track->db_depth_size, bpe, track->db_offset,
501 radeon_bo_size(track->db_bo));
502 return -EINVAL;
503 }
504 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
505 } else {
506 size = radeon_bo_size(track->db_bo);
507 /* pitch in pixels */
508 pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;
509 slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
510 slice_tile_max *= 64;
511 height = slice_tile_max / pitch;
512 if (height > 8192)
513 height = 8192;
514 base_offset = track->db_bo_mc + track->db_offset;
515 array_mode = G_028010_ARRAY_MODE(track->db_depth_info);
516 array_check.array_mode = array_mode;
517 array_check.group_size = track->group_size;
518 array_check.nbanks = track->nbanks;
519 array_check.npipes = track->npipes;
520 array_check.nsamples = track->nsamples;
521 array_check.blocksize = bpe;
522 if (r600_get_array_mode_alignment(&array_check,
523 &pitch_align, &height_align, &depth_align, &base_align)) {
524 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
525 G_028010_ARRAY_MODE(track->db_depth_info),
526 track->db_depth_info);
527 return -EINVAL;
528 }
529 switch (array_mode) {
530 case V_028010_ARRAY_1D_TILED_THIN1:
531 /* don't break userspace */
532 height &= ~0x7;
533 break;
534 case V_028010_ARRAY_2D_TILED_THIN1:
535 break;
536 default:
537 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
538 G_028010_ARRAY_MODE(track->db_depth_info),
539 track->db_depth_info);
540 return -EINVAL;
541 }
542
543 if (!IS_ALIGNED(pitch, pitch_align)) {
544 dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n",
545 __func__, __LINE__, pitch, pitch_align, array_mode);
546 return -EINVAL;
547 }
548 if (!IS_ALIGNED(height, height_align)) {
549 dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n",
550 __func__, __LINE__, height, height_align, array_mode);
551 return -EINVAL;
552 }
553 if (!IS_ALIGNED(base_offset, base_align)) {
554 dev_warn(p->dev, "%s offset[%d] 0x%llx, 0x%llx, %d not aligned\n", __func__, i,
555 base_offset, base_align, array_mode);
556 return -EINVAL;
557 }
558
559 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
560 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
561 tmp = ntiles * bpe * 64 * nviews;
562 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
563 dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n",
564 array_mode,
565 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
566 radeon_bo_size(track->db_bo));
567 return -EINVAL;
568 }
569 }
570 }
571 return 0;
572 }
573
574 /**
575 * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
576 * @parser: parser structure holding parsing context.
577 * @pkt: where to store packet informations
578 *
579 * Assume that chunk_ib_index is properly set. Will return -EINVAL
580 * if packet is bigger than remaining ib size. or if packets is unknown.
581 **/
582 int r600_cs_packet_parse(struct radeon_cs_parser *p,
583 struct radeon_cs_packet *pkt,
584 unsigned idx)
585 {
586 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
587 uint32_t header;
588
589 if (idx >= ib_chunk->length_dw) {
590 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
591 idx, ib_chunk->length_dw);
592 return -EINVAL;
593 }
594 header = radeon_get_ib_value(p, idx);
595 pkt->idx = idx;
596 pkt->type = CP_PACKET_GET_TYPE(header);
597 pkt->count = CP_PACKET_GET_COUNT(header);
598 pkt->one_reg_wr = 0;
599 switch (pkt->type) {
600 case PACKET_TYPE0:
601 pkt->reg = CP_PACKET0_GET_REG(header);
602 break;
603 case PACKET_TYPE3:
604 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
605 break;
606 case PACKET_TYPE2:
607 pkt->count = -1;
608 break;
609 default:
610 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
611 return -EINVAL;
612 }
613 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
614 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
615 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
616 return -EINVAL;
617 }
618 return 0;
619 }
620
621 /**
622 * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
623 * @parser: parser structure holding parsing context.
624 * @data: pointer to relocation data
625 * @offset_start: starting offset
626 * @offset_mask: offset mask (to align start offset on)
627 * @reloc: reloc informations
628 *
629 * Check next packet is relocation packet3, do bo validation and compute
630 * GPU offset using the provided start.
631 **/
632 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
633 struct radeon_cs_reloc **cs_reloc)
634 {
635 struct radeon_cs_chunk *relocs_chunk;
636 struct radeon_cs_packet p3reloc;
637 unsigned idx;
638 int r;
639
640 if (p->chunk_relocs_idx == -1) {
641 DRM_ERROR("No relocation chunk !\n");
642 return -EINVAL;
643 }
644 *cs_reloc = NULL;
645 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
646 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
647 if (r) {
648 return r;
649 }
650 p->idx += p3reloc.count + 2;
651 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
652 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
653 p3reloc.idx);
654 return -EINVAL;
655 }
656 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
657 if (idx >= relocs_chunk->length_dw) {
658 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
659 idx, relocs_chunk->length_dw);
660 return -EINVAL;
661 }
662 /* FIXME: we assume reloc size is 4 dwords */
663 *cs_reloc = p->relocs_ptr[(idx / 4)];
664 return 0;
665 }
666
667 /**
668 * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
669 * @parser: parser structure holding parsing context.
670 * @data: pointer to relocation data
671 * @offset_start: starting offset
672 * @offset_mask: offset mask (to align start offset on)
673 * @reloc: reloc informations
674 *
675 * Check next packet is relocation packet3, do bo validation and compute
676 * GPU offset using the provided start.
677 **/
678 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
679 struct radeon_cs_reloc **cs_reloc)
680 {
681 struct radeon_cs_chunk *relocs_chunk;
682 struct radeon_cs_packet p3reloc;
683 unsigned idx;
684 int r;
685
686 if (p->chunk_relocs_idx == -1) {
687 DRM_ERROR("No relocation chunk !\n");
688 return -EINVAL;
689 }
690 *cs_reloc = NULL;
691 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
692 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
693 if (r) {
694 return r;
695 }
696 p->idx += p3reloc.count + 2;
697 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
698 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
699 p3reloc.idx);
700 return -EINVAL;
701 }
702 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
703 if (idx >= relocs_chunk->length_dw) {
704 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
705 idx, relocs_chunk->length_dw);
706 return -EINVAL;
707 }
708 *cs_reloc = p->relocs;
709 (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
710 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
711 return 0;
712 }
713
714 /**
715 * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
716 * @parser: parser structure holding parsing context.
717 *
718 * Check next packet is relocation packet3, do bo validation and compute
719 * GPU offset using the provided start.
720 **/
721 static int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
722 {
723 struct radeon_cs_packet p3reloc;
724 int r;
725
726 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
727 if (r) {
728 return 0;
729 }
730 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
731 return 0;
732 }
733 return 1;
734 }
735
736 /**
737 * r600_cs_packet_next_vline() - parse userspace VLINE packet
738 * @parser: parser structure holding parsing context.
739 *
740 * Userspace sends a special sequence for VLINE waits.
741 * PACKET0 - VLINE_START_END + value
742 * PACKET3 - WAIT_REG_MEM poll vline status reg
743 * RELOC (P3) - crtc_id in reloc.
744 *
745 * This function parses this and relocates the VLINE START END
746 * and WAIT_REG_MEM packets to the correct crtc.
747 * It also detects a switched off crtc and nulls out the
748 * wait in that case.
749 */
750 static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
751 {
752 struct drm_mode_object *obj;
753 struct drm_crtc *crtc;
754 struct radeon_crtc *radeon_crtc;
755 struct radeon_cs_packet p3reloc, wait_reg_mem;
756 int crtc_id;
757 int r;
758 uint32_t header, h_idx, reg, wait_reg_mem_info;
759 volatile uint32_t *ib;
760
761 ib = p->ib->ptr;
762
763 /* parse the WAIT_REG_MEM */
764 r = r600_cs_packet_parse(p, &wait_reg_mem, p->idx);
765 if (r)
766 return r;
767
768 /* check its a WAIT_REG_MEM */
769 if (wait_reg_mem.type != PACKET_TYPE3 ||
770 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
771 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
772 return -EINVAL;
773 }
774
775 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
776 /* bit 4 is reg (0) or mem (1) */
777 if (wait_reg_mem_info & 0x10) {
778 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
779 return -EINVAL;
780 }
781 /* waiting for value to be equal */
782 if ((wait_reg_mem_info & 0x7) != 0x3) {
783 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
784 return -EINVAL;
785 }
786 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) {
787 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
788 return -EINVAL;
789 }
790
791 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) {
792 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
793 return -EINVAL;
794 }
795
796 /* jump over the NOP */
797 r = r600_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
798 if (r)
799 return r;
800
801 h_idx = p->idx - 2;
802 p->idx += wait_reg_mem.count + 2;
803 p->idx += p3reloc.count + 2;
804
805 header = radeon_get_ib_value(p, h_idx);
806 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
807 reg = CP_PACKET0_GET_REG(header);
808
809 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
810 if (!obj) {
811 DRM_ERROR("cannot find crtc %d\n", crtc_id);
812 return -EINVAL;
813 }
814 crtc = obj_to_crtc(obj);
815 radeon_crtc = to_radeon_crtc(crtc);
816 crtc_id = radeon_crtc->crtc_id;
817
818 if (!crtc->enabled) {
819 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
820 ib[h_idx + 2] = PACKET2(0);
821 ib[h_idx + 3] = PACKET2(0);
822 ib[h_idx + 4] = PACKET2(0);
823 ib[h_idx + 5] = PACKET2(0);
824 ib[h_idx + 6] = PACKET2(0);
825 ib[h_idx + 7] = PACKET2(0);
826 ib[h_idx + 8] = PACKET2(0);
827 } else if (crtc_id == 1) {
828 switch (reg) {
829 case AVIVO_D1MODE_VLINE_START_END:
830 header &= ~R600_CP_PACKET0_REG_MASK;
831 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
832 break;
833 default:
834 DRM_ERROR("unknown crtc reloc\n");
835 return -EINVAL;
836 }
837 ib[h_idx] = header;
838 ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2;
839 }
840
841 return 0;
842 }
843
844 static int r600_packet0_check(struct radeon_cs_parser *p,
845 struct radeon_cs_packet *pkt,
846 unsigned idx, unsigned reg)
847 {
848 int r;
849
850 switch (reg) {
851 case AVIVO_D1MODE_VLINE_START_END:
852 r = r600_cs_packet_parse_vline(p);
853 if (r) {
854 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
855 idx, reg);
856 return r;
857 }
858 break;
859 default:
860 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
861 reg, idx);
862 return -EINVAL;
863 }
864 return 0;
865 }
866
867 static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
868 struct radeon_cs_packet *pkt)
869 {
870 unsigned reg, i;
871 unsigned idx;
872 int r;
873
874 idx = pkt->idx + 1;
875 reg = pkt->reg;
876 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
877 r = r600_packet0_check(p, pkt, idx, reg);
878 if (r) {
879 return r;
880 }
881 }
882 return 0;
883 }
884
885 /**
886 * r600_cs_check_reg() - check if register is authorized or not
887 * @parser: parser structure holding parsing context
888 * @reg: register we are testing
889 * @idx: index into the cs buffer
890 *
891 * This function will test against r600_reg_safe_bm and return 0
892 * if register is safe. If register is not flag as safe this function
893 * will test it against a list of register needind special handling.
894 */
895 static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
896 {
897 struct r600_cs_track *track = (struct r600_cs_track *)p->track;
898 struct radeon_cs_reloc *reloc;
899 u32 m, i, tmp, *ib;
900 int r;
901
902 i = (reg >> 7);
903 if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
904 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
905 return -EINVAL;
906 }
907 m = 1 << ((reg >> 2) & 31);
908 if (!(r600_reg_safe_bm[i] & m))
909 return 0;
910 ib = p->ib->ptr;
911 switch (reg) {
912 /* force following reg to 0 in an attempt to disable out buffer
913 * which will need us to better understand how it works to perform
914 * security check on it (Jerome)
915 */
916 case R_0288A8_SQ_ESGS_RING_ITEMSIZE:
917 case R_008C44_SQ_ESGS_RING_SIZE:
918 case R_0288B0_SQ_ESTMP_RING_ITEMSIZE:
919 case R_008C54_SQ_ESTMP_RING_SIZE:
920 case R_0288C0_SQ_FBUF_RING_ITEMSIZE:
921 case R_008C74_SQ_FBUF_RING_SIZE:
922 case R_0288B4_SQ_GSTMP_RING_ITEMSIZE:
923 case R_008C5C_SQ_GSTMP_RING_SIZE:
924 case R_0288AC_SQ_GSVS_RING_ITEMSIZE:
925 case R_008C4C_SQ_GSVS_RING_SIZE:
926 case R_0288BC_SQ_PSTMP_RING_ITEMSIZE:
927 case R_008C6C_SQ_PSTMP_RING_SIZE:
928 case R_0288C4_SQ_REDUC_RING_ITEMSIZE:
929 case R_008C7C_SQ_REDUC_RING_SIZE:
930 case R_0288B8_SQ_VSTMP_RING_ITEMSIZE:
931 case R_008C64_SQ_VSTMP_RING_SIZE:
932 case R_0288C8_SQ_GS_VERT_ITEMSIZE:
933 /* get value to populate the IB don't remove */
934 tmp =radeon_get_ib_value(p, idx);
935 ib[idx] = 0;
936 break;
937 case SQ_CONFIG:
938 track->sq_config = radeon_get_ib_value(p, idx);
939 break;
940 case R_028800_DB_DEPTH_CONTROL:
941 track->db_depth_control = radeon_get_ib_value(p, idx);
942 break;
943 case R_028010_DB_DEPTH_INFO:
944 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
945 r600_cs_packet_next_is_pkt3_nop(p)) {
946 r = r600_cs_packet_next_reloc(p, &reloc);
947 if (r) {
948 dev_warn(p->dev, "bad SET_CONTEXT_REG "
949 "0x%04X\n", reg);
950 return -EINVAL;
951 }
952 track->db_depth_info = radeon_get_ib_value(p, idx);
953 ib[idx] &= C_028010_ARRAY_MODE;
954 track->db_depth_info &= C_028010_ARRAY_MODE;
955 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
956 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
957 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
958 } else {
959 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
960 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
961 }
962 } else
963 track->db_depth_info = radeon_get_ib_value(p, idx);
964 break;
965 case R_028004_DB_DEPTH_VIEW:
966 track->db_depth_view = radeon_get_ib_value(p, idx);
967 break;
968 case R_028000_DB_DEPTH_SIZE:
969 track->db_depth_size = radeon_get_ib_value(p, idx);
970 track->db_depth_size_idx = idx;
971 break;
972 case R_028AB0_VGT_STRMOUT_EN:
973 track->vgt_strmout_en = radeon_get_ib_value(p, idx);
974 break;
975 case R_028B20_VGT_STRMOUT_BUFFER_EN:
976 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
977 break;
978 case R_028238_CB_TARGET_MASK:
979 track->cb_target_mask = radeon_get_ib_value(p, idx);
980 break;
981 case R_02823C_CB_SHADER_MASK:
982 track->cb_shader_mask = radeon_get_ib_value(p, idx);
983 break;
984 case R_028C04_PA_SC_AA_CONFIG:
985 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
986 track->nsamples = 1 << tmp;
987 break;
988 case R_0280A0_CB_COLOR0_INFO:
989 case R_0280A4_CB_COLOR1_INFO:
990 case R_0280A8_CB_COLOR2_INFO:
991 case R_0280AC_CB_COLOR3_INFO:
992 case R_0280B0_CB_COLOR4_INFO:
993 case R_0280B4_CB_COLOR5_INFO:
994 case R_0280B8_CB_COLOR6_INFO:
995 case R_0280BC_CB_COLOR7_INFO:
996 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
997 r600_cs_packet_next_is_pkt3_nop(p)) {
998 r = r600_cs_packet_next_reloc(p, &reloc);
999 if (r) {
1000 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1001 return -EINVAL;
1002 }
1003 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1004 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1005 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1006 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1007 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1008 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1009 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1010 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1011 }
1012 } else {
1013 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1014 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1015 }
1016 break;
1017 case R_028060_CB_COLOR0_SIZE:
1018 case R_028064_CB_COLOR1_SIZE:
1019 case R_028068_CB_COLOR2_SIZE:
1020 case R_02806C_CB_COLOR3_SIZE:
1021 case R_028070_CB_COLOR4_SIZE:
1022 case R_028074_CB_COLOR5_SIZE:
1023 case R_028078_CB_COLOR6_SIZE:
1024 case R_02807C_CB_COLOR7_SIZE:
1025 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
1026 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
1027 track->cb_color_size_idx[tmp] = idx;
1028 break;
1029 /* This register were added late, there is userspace
1030 * which does provide relocation for those but set
1031 * 0 offset. In order to avoid breaking old userspace
1032 * we detect this and set address to point to last
1033 * CB_COLOR0_BASE, note that if userspace doesn't set
1034 * CB_COLOR0_BASE before this register we will report
1035 * error. Old userspace always set CB_COLOR0_BASE
1036 * before any of this.
1037 */
1038 case R_0280E0_CB_COLOR0_FRAG:
1039 case R_0280E4_CB_COLOR1_FRAG:
1040 case R_0280E8_CB_COLOR2_FRAG:
1041 case R_0280EC_CB_COLOR3_FRAG:
1042 case R_0280F0_CB_COLOR4_FRAG:
1043 case R_0280F4_CB_COLOR5_FRAG:
1044 case R_0280F8_CB_COLOR6_FRAG:
1045 case R_0280FC_CB_COLOR7_FRAG:
1046 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
1047 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
1048 if (!track->cb_color_base_last[tmp]) {
1049 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1050 return -EINVAL;
1051 }
1052 ib[idx] = track->cb_color_base_last[tmp];
1053 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
1054 } else {
1055 r = r600_cs_packet_next_reloc(p, &reloc);
1056 if (r) {
1057 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1058 return -EINVAL;
1059 }
1060 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1061 track->cb_color_frag_bo[tmp] = reloc->robj;
1062 }
1063 break;
1064 case R_0280C0_CB_COLOR0_TILE:
1065 case R_0280C4_CB_COLOR1_TILE:
1066 case R_0280C8_CB_COLOR2_TILE:
1067 case R_0280CC_CB_COLOR3_TILE:
1068 case R_0280D0_CB_COLOR4_TILE:
1069 case R_0280D4_CB_COLOR5_TILE:
1070 case R_0280D8_CB_COLOR6_TILE:
1071 case R_0280DC_CB_COLOR7_TILE:
1072 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
1073 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
1074 if (!track->cb_color_base_last[tmp]) {
1075 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1076 return -EINVAL;
1077 }
1078 ib[idx] = track->cb_color_base_last[tmp];
1079 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
1080 } else {
1081 r = r600_cs_packet_next_reloc(p, &reloc);
1082 if (r) {
1083 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1084 return -EINVAL;
1085 }
1086 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1087 track->cb_color_tile_bo[tmp] = reloc->robj;
1088 }
1089 break;
1090 case CB_COLOR0_BASE:
1091 case CB_COLOR1_BASE:
1092 case CB_COLOR2_BASE:
1093 case CB_COLOR3_BASE:
1094 case CB_COLOR4_BASE:
1095 case CB_COLOR5_BASE:
1096 case CB_COLOR6_BASE:
1097 case CB_COLOR7_BASE:
1098 r = r600_cs_packet_next_reloc(p, &reloc);
1099 if (r) {
1100 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1101 "0x%04X\n", reg);
1102 return -EINVAL;
1103 }
1104 tmp = (reg - CB_COLOR0_BASE) / 4;
1105 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1106 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1107 track->cb_color_base_last[tmp] = ib[idx];
1108 track->cb_color_bo[tmp] = reloc->robj;
1109 track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset;
1110 break;
1111 case DB_DEPTH_BASE:
1112 r = r600_cs_packet_next_reloc(p, &reloc);
1113 if (r) {
1114 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1115 "0x%04X\n", reg);
1116 return -EINVAL;
1117 }
1118 track->db_offset = radeon_get_ib_value(p, idx) << 8;
1119 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1120 track->db_bo = reloc->robj;
1121 track->db_bo_mc = reloc->lobj.gpu_offset;
1122 break;
1123 case DB_HTILE_DATA_BASE:
1124 case SQ_PGM_START_FS:
1125 case SQ_PGM_START_ES:
1126 case SQ_PGM_START_VS:
1127 case SQ_PGM_START_GS:
1128 case SQ_PGM_START_PS:
1129 case SQ_ALU_CONST_CACHE_GS_0:
1130 case SQ_ALU_CONST_CACHE_GS_1:
1131 case SQ_ALU_CONST_CACHE_GS_2:
1132 case SQ_ALU_CONST_CACHE_GS_3:
1133 case SQ_ALU_CONST_CACHE_GS_4:
1134 case SQ_ALU_CONST_CACHE_GS_5:
1135 case SQ_ALU_CONST_CACHE_GS_6:
1136 case SQ_ALU_CONST_CACHE_GS_7:
1137 case SQ_ALU_CONST_CACHE_GS_8:
1138 case SQ_ALU_CONST_CACHE_GS_9:
1139 case SQ_ALU_CONST_CACHE_GS_10:
1140 case SQ_ALU_CONST_CACHE_GS_11:
1141 case SQ_ALU_CONST_CACHE_GS_12:
1142 case SQ_ALU_CONST_CACHE_GS_13:
1143 case SQ_ALU_CONST_CACHE_GS_14:
1144 case SQ_ALU_CONST_CACHE_GS_15:
1145 case SQ_ALU_CONST_CACHE_PS_0:
1146 case SQ_ALU_CONST_CACHE_PS_1:
1147 case SQ_ALU_CONST_CACHE_PS_2:
1148 case SQ_ALU_CONST_CACHE_PS_3:
1149 case SQ_ALU_CONST_CACHE_PS_4:
1150 case SQ_ALU_CONST_CACHE_PS_5:
1151 case SQ_ALU_CONST_CACHE_PS_6:
1152 case SQ_ALU_CONST_CACHE_PS_7:
1153 case SQ_ALU_CONST_CACHE_PS_8:
1154 case SQ_ALU_CONST_CACHE_PS_9:
1155 case SQ_ALU_CONST_CACHE_PS_10:
1156 case SQ_ALU_CONST_CACHE_PS_11:
1157 case SQ_ALU_CONST_CACHE_PS_12:
1158 case SQ_ALU_CONST_CACHE_PS_13:
1159 case SQ_ALU_CONST_CACHE_PS_14:
1160 case SQ_ALU_CONST_CACHE_PS_15:
1161 case SQ_ALU_CONST_CACHE_VS_0:
1162 case SQ_ALU_CONST_CACHE_VS_1:
1163 case SQ_ALU_CONST_CACHE_VS_2:
1164 case SQ_ALU_CONST_CACHE_VS_3:
1165 case SQ_ALU_CONST_CACHE_VS_4:
1166 case SQ_ALU_CONST_CACHE_VS_5:
1167 case SQ_ALU_CONST_CACHE_VS_6:
1168 case SQ_ALU_CONST_CACHE_VS_7:
1169 case SQ_ALU_CONST_CACHE_VS_8:
1170 case SQ_ALU_CONST_CACHE_VS_9:
1171 case SQ_ALU_CONST_CACHE_VS_10:
1172 case SQ_ALU_CONST_CACHE_VS_11:
1173 case SQ_ALU_CONST_CACHE_VS_12:
1174 case SQ_ALU_CONST_CACHE_VS_13:
1175 case SQ_ALU_CONST_CACHE_VS_14:
1176 case SQ_ALU_CONST_CACHE_VS_15:
1177 r = r600_cs_packet_next_reloc(p, &reloc);
1178 if (r) {
1179 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1180 "0x%04X\n", reg);
1181 return -EINVAL;
1182 }
1183 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1184 break;
1185 case SX_MEMORY_EXPORT_BASE:
1186 r = r600_cs_packet_next_reloc(p, &reloc);
1187 if (r) {
1188 dev_warn(p->dev, "bad SET_CONFIG_REG "
1189 "0x%04X\n", reg);
1190 return -EINVAL;
1191 }
1192 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1193 break;
1194 default:
1195 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1196 return -EINVAL;
1197 }
1198 return 0;
1199 }
1200
1201 static unsigned mip_minify(unsigned size, unsigned level)
1202 {
1203 unsigned val;
1204
1205 val = max(1U, size >> level);
1206 if (level > 0)
1207 val = roundup_pow_of_two(val);
1208 return val;
1209 }
1210
1211 static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
1212 unsigned w0, unsigned h0, unsigned d0, unsigned format,
1213 unsigned block_align, unsigned height_align, unsigned base_align,
1214 unsigned *l0_size, unsigned *mipmap_size)
1215 {
1216 unsigned offset, i, level;
1217 unsigned width, height, depth, size;
1218 unsigned blocksize;
1219 unsigned nbx, nby;
1220 unsigned nlevels = llevel - blevel + 1;
1221
1222 *l0_size = -1;
1223 blocksize = fmt_get_blocksize(format);
1224
1225 w0 = mip_minify(w0, 0);
1226 h0 = mip_minify(h0, 0);
1227 d0 = mip_minify(d0, 0);
1228 for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) {
1229 width = mip_minify(w0, i);
1230 nbx = fmt_get_nblocksx(format, width);
1231
1232 nbx = round_up(nbx, block_align);
1233
1234 height = mip_minify(h0, i);
1235 nby = fmt_get_nblocksy(format, height);
1236 nby = round_up(nby, height_align);
1237
1238 depth = mip_minify(d0, i);
1239
1240 size = nbx * nby * blocksize;
1241 if (nfaces)
1242 size *= nfaces;
1243 else
1244 size *= depth;
1245
1246 if (i == 0)
1247 *l0_size = size;
1248
1249 if (i == 0 || i == 1)
1250 offset = round_up(offset, base_align);
1251
1252 offset += size;
1253 }
1254 *mipmap_size = offset;
1255 if (llevel == 0)
1256 *mipmap_size = *l0_size;
1257 if (!blevel)
1258 *mipmap_size -= *l0_size;
1259 }
1260
1261 /**
1262 * r600_check_texture_resource() - check if register is authorized or not
1263 * @p: parser structure holding parsing context
1264 * @idx: index into the cs buffer
1265 * @texture: texture's bo structure
1266 * @mipmap: mipmap's bo structure
1267 *
1268 * This function will check that the resource has valid field and that
1269 * the texture and mipmap bo object are big enough to cover this resource.
1270 */
1271 static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
1272 struct radeon_bo *texture,
1273 struct radeon_bo *mipmap,
1274 u64 base_offset,
1275 u64 mip_offset,
1276 u32 tiling_flags)
1277 {
1278 struct r600_cs_track *track = p->track;
1279 u32 nfaces, llevel, blevel, w0, h0, d0;
1280 u32 word0, word1, l0_size, mipmap_size, word2, word3;
1281 u32 height_align, pitch, pitch_align, depth_align;
1282 u32 array, barray, larray;
1283 u64 base_align;
1284 struct array_mode_checker array_check;
1285 u32 format;
1286
1287 /* on legacy kernel we don't perform advanced check */
1288 if (p->rdev == NULL)
1289 return 0;
1290
1291 /* convert to bytes */
1292 base_offset <<= 8;
1293 mip_offset <<= 8;
1294
1295 word0 = radeon_get_ib_value(p, idx + 0);
1296 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1297 if (tiling_flags & RADEON_TILING_MACRO)
1298 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1299 else if (tiling_flags & RADEON_TILING_MICRO)
1300 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1301 }
1302 word1 = radeon_get_ib_value(p, idx + 1);
1303 w0 = G_038000_TEX_WIDTH(word0) + 1;
1304 h0 = G_038004_TEX_HEIGHT(word1) + 1;
1305 d0 = G_038004_TEX_DEPTH(word1);
1306 nfaces = 1;
1307 array = 0;
1308 switch (G_038000_DIM(word0)) {
1309 case V_038000_SQ_TEX_DIM_1D:
1310 case V_038000_SQ_TEX_DIM_2D:
1311 case V_038000_SQ_TEX_DIM_3D:
1312 break;
1313 case V_038000_SQ_TEX_DIM_CUBEMAP:
1314 if (p->family >= CHIP_RV770)
1315 nfaces = 8;
1316 else
1317 nfaces = 6;
1318 break;
1319 case V_038000_SQ_TEX_DIM_1D_ARRAY:
1320 case V_038000_SQ_TEX_DIM_2D_ARRAY:
1321 array = 1;
1322 break;
1323 case V_038000_SQ_TEX_DIM_2D_MSAA:
1324 case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
1325 default:
1326 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));
1327 return -EINVAL;
1328 }
1329 format = G_038004_DATA_FORMAT(word1);
1330 if (!fmt_is_valid_texture(format, p->family)) {
1331 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
1332 __func__, __LINE__, format);
1333 return -EINVAL;
1334 }
1335
1336 /* pitch in texels */
1337 pitch = (G_038000_PITCH(word0) + 1) * 8;
1338 array_check.array_mode = G_038000_TILE_MODE(word0);
1339 array_check.group_size = track->group_size;
1340 array_check.nbanks = track->nbanks;
1341 array_check.npipes = track->npipes;
1342 array_check.nsamples = 1;
1343 array_check.blocksize = fmt_get_blocksize(format);
1344 if (r600_get_array_mode_alignment(&array_check,
1345 &pitch_align, &height_align, &depth_align, &base_align)) {
1346 dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n",
1347 __func__, __LINE__, G_038000_TILE_MODE(word0));
1348 return -EINVAL;
1349 }
1350
1351 /* XXX check height as well... */
1352
1353 if (!IS_ALIGNED(pitch, pitch_align)) {
1354 dev_warn(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n",
1355 __func__, __LINE__, pitch, pitch_align, G_038000_TILE_MODE(word0));
1356 return -EINVAL;
1357 }
1358 if (!IS_ALIGNED(base_offset, base_align)) {
1359 dev_warn(p->dev, "%s:%d tex base offset (0x%llx, 0x%llx, %d) invalid\n",
1360 __func__, __LINE__, base_offset, base_align, G_038000_TILE_MODE(word0));
1361 return -EINVAL;
1362 }
1363 if (!IS_ALIGNED(mip_offset, base_align)) {
1364 dev_warn(p->dev, "%s:%d tex mip offset (0x%llx, 0x%llx, %d) invalid\n",
1365 __func__, __LINE__, mip_offset, base_align, G_038000_TILE_MODE(word0));
1366 return -EINVAL;
1367 }
1368
1369 word2 = radeon_get_ib_value(p, idx + 2) << 8;
1370 word3 = radeon_get_ib_value(p, idx + 3) << 8;
1371
1372 word0 = radeon_get_ib_value(p, idx + 4);
1373 word1 = radeon_get_ib_value(p, idx + 5);
1374 blevel = G_038010_BASE_LEVEL(word0);
1375 llevel = G_038014_LAST_LEVEL(word1);
1376 if (array == 1) {
1377 barray = G_038014_BASE_ARRAY(word1);
1378 larray = G_038014_LAST_ARRAY(word1);
1379
1380 nfaces = larray - barray + 1;
1381 }
1382 r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, format,
1383 pitch_align, height_align, base_align,
1384 &l0_size, &mipmap_size);
1385 /* using get ib will give us the offset into the texture bo */
1386 if ((l0_size + word2) > radeon_bo_size(texture)) {
1387 dev_warn(p->dev, "texture bo too small (%d %d %d %d -> %d have %ld)\n",
1388 w0, h0, format, word2, l0_size, radeon_bo_size(texture));
1389 dev_warn(p->dev, "alignments %d %d %d %lld\n", pitch, pitch_align, height_align, base_align);
1390 return -EINVAL;
1391 }
1392 /* using get ib will give us the offset into the mipmap bo */
1393 word3 = radeon_get_ib_value(p, idx + 3) << 8;
1394 if ((mipmap_size + word3) > radeon_bo_size(mipmap)) {
1395 /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
1396 w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/
1397 }
1398 return 0;
1399 }
1400
1401 static int r600_packet3_check(struct radeon_cs_parser *p,
1402 struct radeon_cs_packet *pkt)
1403 {
1404 struct radeon_cs_reloc *reloc;
1405 struct r600_cs_track *track;
1406 volatile u32 *ib;
1407 unsigned idx;
1408 unsigned i;
1409 unsigned start_reg, end_reg, reg;
1410 int r;
1411 u32 idx_value;
1412
1413 track = (struct r600_cs_track *)p->track;
1414 ib = p->ib->ptr;
1415 idx = pkt->idx + 1;
1416 idx_value = radeon_get_ib_value(p, idx);
1417
1418 switch (pkt->opcode) {
1419 case PACKET3_SET_PREDICATION:
1420 {
1421 int pred_op;
1422 int tmp;
1423 if (pkt->count != 1) {
1424 DRM_ERROR("bad SET PREDICATION\n");
1425 return -EINVAL;
1426 }
1427
1428 tmp = radeon_get_ib_value(p, idx + 1);
1429 pred_op = (tmp >> 16) & 0x7;
1430
1431 /* for the clear predicate operation */
1432 if (pred_op == 0)
1433 return 0;
1434
1435 if (pred_op > 2) {
1436 DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op);
1437 return -EINVAL;
1438 }
1439
1440 r = r600_cs_packet_next_reloc(p, &reloc);
1441 if (r) {
1442 DRM_ERROR("bad SET PREDICATION\n");
1443 return -EINVAL;
1444 }
1445
1446 ib[idx + 0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1447 ib[idx + 1] = tmp + (upper_32_bits(reloc->lobj.gpu_offset) & 0xff);
1448 }
1449 break;
1450
1451 case PACKET3_START_3D_CMDBUF:
1452 if (p->family >= CHIP_RV770 || pkt->count) {
1453 DRM_ERROR("bad START_3D\n");
1454 return -EINVAL;
1455 }
1456 break;
1457 case PACKET3_CONTEXT_CONTROL:
1458 if (pkt->count != 1) {
1459 DRM_ERROR("bad CONTEXT_CONTROL\n");
1460 return -EINVAL;
1461 }
1462 break;
1463 case PACKET3_INDEX_TYPE:
1464 case PACKET3_NUM_INSTANCES:
1465 if (pkt->count) {
1466 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
1467 return -EINVAL;
1468 }
1469 break;
1470 case PACKET3_DRAW_INDEX:
1471 if (pkt->count != 3) {
1472 DRM_ERROR("bad DRAW_INDEX\n");
1473 return -EINVAL;
1474 }
1475 r = r600_cs_packet_next_reloc(p, &reloc);
1476 if (r) {
1477 DRM_ERROR("bad DRAW_INDEX\n");
1478 return -EINVAL;
1479 }
1480 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1481 ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1482 r = r600_cs_track_check(p);
1483 if (r) {
1484 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1485 return r;
1486 }
1487 break;
1488 case PACKET3_DRAW_INDEX_AUTO:
1489 if (pkt->count != 1) {
1490 DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1491 return -EINVAL;
1492 }
1493 r = r600_cs_track_check(p);
1494 if (r) {
1495 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1496 return r;
1497 }
1498 break;
1499 case PACKET3_DRAW_INDEX_IMMD_BE:
1500 case PACKET3_DRAW_INDEX_IMMD:
1501 if (pkt->count < 2) {
1502 DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1503 return -EINVAL;
1504 }
1505 r = r600_cs_track_check(p);
1506 if (r) {
1507 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1508 return r;
1509 }
1510 break;
1511 case PACKET3_WAIT_REG_MEM:
1512 if (pkt->count != 5) {
1513 DRM_ERROR("bad WAIT_REG_MEM\n");
1514 return -EINVAL;
1515 }
1516 /* bit 4 is reg (0) or mem (1) */
1517 if (idx_value & 0x10) {
1518 r = r600_cs_packet_next_reloc(p, &reloc);
1519 if (r) {
1520 DRM_ERROR("bad WAIT_REG_MEM\n");
1521 return -EINVAL;
1522 }
1523 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1524 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1525 }
1526 break;
1527 case PACKET3_SURFACE_SYNC:
1528 if (pkt->count != 3) {
1529 DRM_ERROR("bad SURFACE_SYNC\n");
1530 return -EINVAL;
1531 }
1532 /* 0xffffffff/0x0 is flush all cache flag */
1533 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
1534 radeon_get_ib_value(p, idx + 2) != 0) {
1535 r = r600_cs_packet_next_reloc(p, &reloc);
1536 if (r) {
1537 DRM_ERROR("bad SURFACE_SYNC\n");
1538 return -EINVAL;
1539 }
1540 ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1541 }
1542 break;
1543 case PACKET3_EVENT_WRITE:
1544 if (pkt->count != 2 && pkt->count != 0) {
1545 DRM_ERROR("bad EVENT_WRITE\n");
1546 return -EINVAL;
1547 }
1548 if (pkt->count) {
1549 r = r600_cs_packet_next_reloc(p, &reloc);
1550 if (r) {
1551 DRM_ERROR("bad EVENT_WRITE\n");
1552 return -EINVAL;
1553 }
1554 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1555 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1556 }
1557 break;
1558 case PACKET3_EVENT_WRITE_EOP:
1559 if (pkt->count != 4) {
1560 DRM_ERROR("bad EVENT_WRITE_EOP\n");
1561 return -EINVAL;
1562 }
1563 r = r600_cs_packet_next_reloc(p, &reloc);
1564 if (r) {
1565 DRM_ERROR("bad EVENT_WRITE\n");
1566 return -EINVAL;
1567 }
1568 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1569 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1570 break;
1571 case PACKET3_SET_CONFIG_REG:
1572 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
1573 end_reg = 4 * pkt->count + start_reg - 4;
1574 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
1575 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
1576 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
1577 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
1578 return -EINVAL;
1579 }
1580 for (i = 0; i < pkt->count; i++) {
1581 reg = start_reg + (4 * i);
1582 r = r600_cs_check_reg(p, reg, idx+1+i);
1583 if (r)
1584 return r;
1585 }
1586 break;
1587 case PACKET3_SET_CONTEXT_REG:
1588 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
1589 end_reg = 4 * pkt->count + start_reg - 4;
1590 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
1591 (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
1592 (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
1593 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
1594 return -EINVAL;
1595 }
1596 for (i = 0; i < pkt->count; i++) {
1597 reg = start_reg + (4 * i);
1598 r = r600_cs_check_reg(p, reg, idx+1+i);
1599 if (r)
1600 return r;
1601 }
1602 break;
1603 case PACKET3_SET_RESOURCE:
1604 if (pkt->count % 7) {
1605 DRM_ERROR("bad SET_RESOURCE\n");
1606 return -EINVAL;
1607 }
1608 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
1609 end_reg = 4 * pkt->count + start_reg - 4;
1610 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
1611 (start_reg >= PACKET3_SET_RESOURCE_END) ||
1612 (end_reg >= PACKET3_SET_RESOURCE_END)) {
1613 DRM_ERROR("bad SET_RESOURCE\n");
1614 return -EINVAL;
1615 }
1616 for (i = 0; i < (pkt->count / 7); i++) {
1617 struct radeon_bo *texture, *mipmap;
1618 u32 size, offset, base_offset, mip_offset;
1619
1620 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
1621 case SQ_TEX_VTX_VALID_TEXTURE:
1622 /* tex base */
1623 r = r600_cs_packet_next_reloc(p, &reloc);
1624 if (r) {
1625 DRM_ERROR("bad SET_RESOURCE\n");
1626 return -EINVAL;
1627 }
1628 base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1629 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1630 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1631 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1632 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1633 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1634 }
1635 texture = reloc->robj;
1636 /* tex mip base */
1637 r = r600_cs_packet_next_reloc(p, &reloc);
1638 if (r) {
1639 DRM_ERROR("bad SET_RESOURCE\n");
1640 return -EINVAL;
1641 }
1642 mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1643 mipmap = reloc->robj;
1644 r = r600_check_texture_resource(p, idx+(i*7)+1,
1645 texture, mipmap,
1646 base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2),
1647 mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3),
1648 reloc->lobj.tiling_flags);
1649 if (r)
1650 return r;
1651 ib[idx+1+(i*7)+2] += base_offset;
1652 ib[idx+1+(i*7)+3] += mip_offset;
1653 break;
1654 case SQ_TEX_VTX_VALID_BUFFER:
1655 /* vtx base */
1656 r = r600_cs_packet_next_reloc(p, &reloc);
1657 if (r) {
1658 DRM_ERROR("bad SET_RESOURCE\n");
1659 return -EINVAL;
1660 }
1661 offset = radeon_get_ib_value(p, idx+1+(i*7)+0);
1662 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1;
1663 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
1664 /* force size to size of the buffer */
1665 dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n",
1666 size + offset, radeon_bo_size(reloc->robj));
1667 ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj);
1668 }
1669 ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
1670 ib[idx+1+(i*7)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1671 break;
1672 case SQ_TEX_VTX_INVALID_TEXTURE:
1673 case SQ_TEX_VTX_INVALID_BUFFER:
1674 default:
1675 DRM_ERROR("bad SET_RESOURCE\n");
1676 return -EINVAL;
1677 }
1678 }
1679 break;
1680 case PACKET3_SET_ALU_CONST:
1681 if (track->sq_config & DX9_CONSTS) {
1682 start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
1683 end_reg = 4 * pkt->count + start_reg - 4;
1684 if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
1685 (start_reg >= PACKET3_SET_ALU_CONST_END) ||
1686 (end_reg >= PACKET3_SET_ALU_CONST_END)) {
1687 DRM_ERROR("bad SET_ALU_CONST\n");
1688 return -EINVAL;
1689 }
1690 }
1691 break;
1692 case PACKET3_SET_BOOL_CONST:
1693 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
1694 end_reg = 4 * pkt->count + start_reg - 4;
1695 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
1696 (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
1697 (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
1698 DRM_ERROR("bad SET_BOOL_CONST\n");
1699 return -EINVAL;
1700 }
1701 break;
1702 case PACKET3_SET_LOOP_CONST:
1703 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
1704 end_reg = 4 * pkt->count + start_reg - 4;
1705 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
1706 (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
1707 (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
1708 DRM_ERROR("bad SET_LOOP_CONST\n");
1709 return -EINVAL;
1710 }
1711 break;
1712 case PACKET3_SET_CTL_CONST:
1713 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
1714 end_reg = 4 * pkt->count + start_reg - 4;
1715 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
1716 (start_reg >= PACKET3_SET_CTL_CONST_END) ||
1717 (end_reg >= PACKET3_SET_CTL_CONST_END)) {
1718 DRM_ERROR("bad SET_CTL_CONST\n");
1719 return -EINVAL;
1720 }
1721 break;
1722 case PACKET3_SET_SAMPLER:
1723 if (pkt->count % 3) {
1724 DRM_ERROR("bad SET_SAMPLER\n");
1725 return -EINVAL;
1726 }
1727 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
1728 end_reg = 4 * pkt->count + start_reg - 4;
1729 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
1730 (start_reg >= PACKET3_SET_SAMPLER_END) ||
1731 (end_reg >= PACKET3_SET_SAMPLER_END)) {
1732 DRM_ERROR("bad SET_SAMPLER\n");
1733 return -EINVAL;
1734 }
1735 break;
1736 case PACKET3_SURFACE_BASE_UPDATE:
1737 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
1738 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
1739 return -EINVAL;
1740 }
1741 if (pkt->count) {
1742 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
1743 return -EINVAL;
1744 }
1745 break;
1746 case PACKET3_NOP:
1747 break;
1748 default:
1749 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1750 return -EINVAL;
1751 }
1752 return 0;
1753 }
1754
1755 int r600_cs_parse(struct radeon_cs_parser *p)
1756 {
1757 struct radeon_cs_packet pkt;
1758 struct r600_cs_track *track;
1759 int r;
1760
1761 if (p->track == NULL) {
1762 /* initialize tracker, we are in kms */
1763 track = kzalloc(sizeof(*track), GFP_KERNEL);
1764 if (track == NULL)
1765 return -ENOMEM;
1766 r600_cs_track_init(track);
1767 if (p->rdev->family < CHIP_RV770) {
1768 track->npipes = p->rdev->config.r600.tiling_npipes;
1769 track->nbanks = p->rdev->config.r600.tiling_nbanks;
1770 track->group_size = p->rdev->config.r600.tiling_group_size;
1771 } else if (p->rdev->family <= CHIP_RV740) {
1772 track->npipes = p->rdev->config.rv770.tiling_npipes;
1773 track->nbanks = p->rdev->config.rv770.tiling_nbanks;
1774 track->group_size = p->rdev->config.rv770.tiling_group_size;
1775 }
1776 p->track = track;
1777 }
1778 do {
1779 r = r600_cs_packet_parse(p, &pkt, p->idx);
1780 if (r) {
1781 kfree(p->track);
1782 p->track = NULL;
1783 return r;
1784 }
1785 p->idx += pkt.count + 2;
1786 switch (pkt.type) {
1787 case PACKET_TYPE0:
1788 r = r600_cs_parse_packet0(p, &pkt);
1789 break;
1790 case PACKET_TYPE2:
1791 break;
1792 case PACKET_TYPE3:
1793 r = r600_packet3_check(p, &pkt);
1794 break;
1795 default:
1796 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1797 kfree(p->track);
1798 p->track = NULL;
1799 return -EINVAL;
1800 }
1801 if (r) {
1802 kfree(p->track);
1803 p->track = NULL;
1804 return r;
1805 }
1806 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1807 #if 0
1808 for (r = 0; r < p->ib->length_dw; r++) {
1809 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib->ptr[r]);
1810 mdelay(1);
1811 }
1812 #endif
1813 kfree(p->track);
1814 p->track = NULL;
1815 return 0;
1816 }
1817
1818 static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
1819 {
1820 if (p->chunk_relocs_idx == -1) {
1821 return 0;
1822 }
1823 p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL);
1824 if (p->relocs == NULL) {
1825 return -ENOMEM;
1826 }
1827 return 0;
1828 }
1829
1830 /**
1831 * cs_parser_fini() - clean parser states
1832 * @parser: parser structure holding parsing context.
1833 * @error: error number
1834 *
1835 * If error is set than unvalidate buffer, otherwise just free memory
1836 * used by parsing context.
1837 **/
1838 static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
1839 {
1840 unsigned i;
1841
1842 kfree(parser->relocs);
1843 for (i = 0; i < parser->nchunks; i++) {
1844 kfree(parser->chunks[i].kdata);
1845 kfree(parser->chunks[i].kpage[0]);
1846 kfree(parser->chunks[i].kpage[1]);
1847 }
1848 kfree(parser->chunks);
1849 kfree(parser->chunks_array);
1850 }
1851
1852 int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
1853 unsigned family, u32 *ib, int *l)
1854 {
1855 struct radeon_cs_parser parser;
1856 struct radeon_cs_chunk *ib_chunk;
1857 struct radeon_ib fake_ib;
1858 struct r600_cs_track *track;
1859 int r;
1860
1861 /* initialize tracker */
1862 track = kzalloc(sizeof(*track), GFP_KERNEL);
1863 if (track == NULL)
1864 return -ENOMEM;
1865 r600_cs_track_init(track);
1866 r600_cs_legacy_get_tiling_conf(dev, &track->npipes, &track->nbanks, &track->group_size);
1867 /* initialize parser */
1868 memset(&parser, 0, sizeof(struct radeon_cs_parser));
1869 parser.filp = filp;
1870 parser.dev = &dev->pdev->dev;
1871 parser.rdev = NULL;
1872 parser.family = family;
1873 parser.ib = &fake_ib;
1874 parser.track = track;
1875 fake_ib.ptr = ib;
1876 r = radeon_cs_parser_init(&parser, data);
1877 if (r) {
1878 DRM_ERROR("Failed to initialize parser !\n");
1879 r600_cs_parser_fini(&parser, r);
1880 return r;
1881 }
1882 r = r600_cs_parser_relocs_legacy(&parser);
1883 if (r) {
1884 DRM_ERROR("Failed to parse relocation !\n");
1885 r600_cs_parser_fini(&parser, r);
1886 return r;
1887 }
1888 /* Copy the packet into the IB, the parser will read from the
1889 * input memory (cached) and write to the IB (which can be
1890 * uncached). */
1891 ib_chunk = &parser.chunks[parser.chunk_ib_idx];
1892 parser.ib->length_dw = ib_chunk->length_dw;
1893 *l = parser.ib->length_dw;
1894 r = r600_cs_parse(&parser);
1895 if (r) {
1896 DRM_ERROR("Invalid command stream !\n");
1897 r600_cs_parser_fini(&parser, r);
1898 return r;
1899 }
1900 r = radeon_cs_finish_pages(&parser);
1901 if (r) {
1902 DRM_ERROR("Invalid command stream !\n");
1903 r600_cs_parser_fini(&parser, r);
1904 return r;
1905 }
1906 r600_cs_parser_fini(&parser, r);
1907 return r;
1908 }
1909
1910 void r600_cs_legacy_init(void)
1911 {
1912 r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
1913 }