Merge tag 'v3.3.7' into 3.3/master
[zen-stable.git] / drivers / infiniband / hw / ipath / ipath_eeprom.c
blobfc7181985e8e8886a48cbbcbfcce3cc499e6b871
1 /*
2 * Copyright (c) 2006, 2007, 2008 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
34 #include <linux/delay.h>
35 #include <linux/pci.h>
36 #include <linux/vmalloc.h>
38 #include "ipath_kernel.h"
41 * InfiniPath I2C driver for a serial eeprom. This is not a generic
42 * I2C interface. For a start, the device we're using (Atmel AT24C11)
43 * doesn't work like a regular I2C device. It looks like one
44 * electrically, but not logically. Normal I2C devices have a single
45 * 7-bit or 10-bit I2C address that they respond to. Valid 7-bit
46 * addresses range from 0x03 to 0x77. Addresses 0x00 to 0x02 and 0x78
47 * to 0x7F are special reserved addresses (e.g. 0x00 is the "general
48 * call" address.) The Atmel device, on the other hand, responds to ALL
49 * 7-bit addresses. It's designed to be the only device on a given I2C
50 * bus. A 7-bit address corresponds to the memory address within the
51 * Atmel device itself.
53 * Also, the timing requirements mean more than simple software
54 * bitbanging, with readbacks from chip to ensure timing (simple udelay
55 * is not enough).
57 * This all means that accessing the device is specialized enough
58 * that using the standard kernel I2C bitbanging interface would be
59 * impossible. For example, the core I2C eeprom driver expects to find
60 * a device at one or more of a limited set of addresses only. It doesn't
61 * allow writing to an eeprom. It also doesn't provide any means of
62 * accessing eeprom contents from within the kernel, only via sysfs.
65 /* Added functionality for IBA7220-based cards */
66 #define IPATH_EEPROM_DEV_V1 0xA0
67 #define IPATH_EEPROM_DEV_V2 0xA2
68 #define IPATH_TEMP_DEV 0x98
69 #define IPATH_BAD_DEV (IPATH_EEPROM_DEV_V2+2)
70 #define IPATH_NO_DEV (0xFF)
73 * The number of I2C chains is proliferating. Table below brings
74 * some order to the madness. The basic principle is that the
75 * table is scanned from the top, and a "probe" is made to the
76 * device probe_dev. If that succeeds, the chain is considered
77 * to be of that type, and dd->i2c_chain_type is set to the index+1
78 * of the entry.
79 * The +1 is so static initialization can mean "unknown, do probe."
81 static struct i2c_chain_desc {
82 u8 probe_dev; /* If seen at probe, chain is this type */
83 u8 eeprom_dev; /* Dev addr (if any) for EEPROM */
84 u8 temp_dev; /* Dev Addr (if any) for Temp-sense */
85 } i2c_chains[] = {
86 { IPATH_BAD_DEV, IPATH_NO_DEV, IPATH_NO_DEV }, /* pre-iba7220 bds */
87 { IPATH_EEPROM_DEV_V1, IPATH_EEPROM_DEV_V1, IPATH_TEMP_DEV}, /* V1 */
88 { IPATH_EEPROM_DEV_V2, IPATH_EEPROM_DEV_V2, IPATH_TEMP_DEV}, /* V2 */
89 { IPATH_NO_DEV }
92 enum i2c_type {
93 i2c_line_scl = 0,
94 i2c_line_sda
97 enum i2c_state {
98 i2c_line_low = 0,
99 i2c_line_high
102 #define READ_CMD 1
103 #define WRITE_CMD 0
106 * i2c_gpio_set - set a GPIO line
107 * @dd: the infinipath device
108 * @line: the line to set
109 * @new_line_state: the state to set
111 * Returns 0 if the line was set to the new state successfully, non-zero
112 * on error.
114 static int i2c_gpio_set(struct ipath_devdata *dd,
115 enum i2c_type line,
116 enum i2c_state new_line_state)
118 u64 out_mask, dir_mask, *gpioval;
119 unsigned long flags = 0;
121 gpioval = &dd->ipath_gpio_out;
123 if (line == i2c_line_scl) {
124 dir_mask = dd->ipath_gpio_scl;
125 out_mask = (1UL << dd->ipath_gpio_scl_num);
126 } else {
127 dir_mask = dd->ipath_gpio_sda;
128 out_mask = (1UL << dd->ipath_gpio_sda_num);
131 spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
132 if (new_line_state == i2c_line_high) {
133 /* tri-state the output rather than force high */
134 dd->ipath_extctrl &= ~dir_mask;
135 } else {
136 /* config line to be an output */
137 dd->ipath_extctrl |= dir_mask;
139 ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, dd->ipath_extctrl);
141 /* set output as well (no real verify) */
142 if (new_line_state == i2c_line_high)
143 *gpioval |= out_mask;
144 else
145 *gpioval &= ~out_mask;
147 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_out, *gpioval);
148 spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
150 return 0;
154 * i2c_gpio_get - get a GPIO line state
155 * @dd: the infinipath device
156 * @line: the line to get
157 * @curr_statep: where to put the line state
159 * Returns 0 if the line was set to the new state successfully, non-zero
160 * on error. curr_state is not set on error.
162 static int i2c_gpio_get(struct ipath_devdata *dd,
163 enum i2c_type line,
164 enum i2c_state *curr_statep)
166 u64 read_val, mask;
167 int ret;
168 unsigned long flags = 0;
170 /* check args */
171 if (curr_statep == NULL) {
172 ret = 1;
173 goto bail;
176 /* config line to be an input */
177 if (line == i2c_line_scl)
178 mask = dd->ipath_gpio_scl;
179 else
180 mask = dd->ipath_gpio_sda;
182 spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
183 dd->ipath_extctrl &= ~mask;
184 ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, dd->ipath_extctrl);
186 * Below is very unlikely to reflect true input state if Output
187 * Enable actually changed.
189 read_val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
190 spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
192 if (read_val & mask)
193 *curr_statep = i2c_line_high;
194 else
195 *curr_statep = i2c_line_low;
197 ret = 0;
199 bail:
200 return ret;
204 * i2c_wait_for_writes - wait for a write
205 * @dd: the infinipath device
207 * We use this instead of udelay directly, so we can make sure
208 * that previous register writes have been flushed all the way
209 * to the chip. Since we are delaying anyway, the cost doesn't
210 * hurt, and makes the bit twiddling more regular
212 static void i2c_wait_for_writes(struct ipath_devdata *dd)
214 (void)ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
215 rmb();
218 static void scl_out(struct ipath_devdata *dd, u8 bit)
220 udelay(1);
221 i2c_gpio_set(dd, i2c_line_scl, bit ? i2c_line_high : i2c_line_low);
223 i2c_wait_for_writes(dd);
226 static void sda_out(struct ipath_devdata *dd, u8 bit)
228 i2c_gpio_set(dd, i2c_line_sda, bit ? i2c_line_high : i2c_line_low);
230 i2c_wait_for_writes(dd);
233 static u8 sda_in(struct ipath_devdata *dd, int wait)
235 enum i2c_state bit;
237 if (i2c_gpio_get(dd, i2c_line_sda, &bit))
238 ipath_dbg("get bit failed!\n");
240 if (wait)
241 i2c_wait_for_writes(dd);
243 return bit == i2c_line_high ? 1U : 0;
247 * i2c_ackrcv - see if ack following write is true
248 * @dd: the infinipath device
250 static int i2c_ackrcv(struct ipath_devdata *dd)
252 u8 ack_received;
254 /* AT ENTRY SCL = LOW */
255 /* change direction, ignore data */
256 ack_received = sda_in(dd, 1);
257 scl_out(dd, i2c_line_high);
258 ack_received = sda_in(dd, 1) == 0;
259 scl_out(dd, i2c_line_low);
260 return ack_received;
264 * rd_byte - read a byte, leaving ACK, STOP, etc up to caller
265 * @dd: the infinipath device
267 * Returns byte shifted out of device
269 static int rd_byte(struct ipath_devdata *dd)
271 int bit_cntr, data;
273 data = 0;
275 for (bit_cntr = 7; bit_cntr >= 0; --bit_cntr) {
276 data <<= 1;
277 scl_out(dd, i2c_line_high);
278 data |= sda_in(dd, 0);
279 scl_out(dd, i2c_line_low);
281 return data;
285 * wr_byte - write a byte, one bit at a time
286 * @dd: the infinipath device
287 * @data: the byte to write
289 * Returns 0 if we got the following ack, otherwise 1
291 static int wr_byte(struct ipath_devdata *dd, u8 data)
293 int bit_cntr;
294 u8 bit;
296 for (bit_cntr = 7; bit_cntr >= 0; bit_cntr--) {
297 bit = (data >> bit_cntr) & 1;
298 sda_out(dd, bit);
299 scl_out(dd, i2c_line_high);
300 scl_out(dd, i2c_line_low);
302 return (!i2c_ackrcv(dd)) ? 1 : 0;
305 static void send_ack(struct ipath_devdata *dd)
307 sda_out(dd, i2c_line_low);
308 scl_out(dd, i2c_line_high);
309 scl_out(dd, i2c_line_low);
310 sda_out(dd, i2c_line_high);
314 * i2c_startcmd - transmit the start condition, followed by address/cmd
315 * @dd: the infinipath device
316 * @offset_dir: direction byte
318 * (both clock/data high, clock high, data low while clock is high)
320 static int i2c_startcmd(struct ipath_devdata *dd, u8 offset_dir)
322 int res;
324 /* issue start sequence */
325 sda_out(dd, i2c_line_high);
326 scl_out(dd, i2c_line_high);
327 sda_out(dd, i2c_line_low);
328 scl_out(dd, i2c_line_low);
330 /* issue length and direction byte */
331 res = wr_byte(dd, offset_dir);
333 if (res)
334 ipath_cdbg(VERBOSE, "No ack to complete start\n");
336 return res;
340 * stop_cmd - transmit the stop condition
341 * @dd: the infinipath device
343 * (both clock/data low, clock high, data high while clock is high)
345 static void stop_cmd(struct ipath_devdata *dd)
347 scl_out(dd, i2c_line_low);
348 sda_out(dd, i2c_line_low);
349 scl_out(dd, i2c_line_high);
350 sda_out(dd, i2c_line_high);
351 udelay(2);
355 * eeprom_reset - reset I2C communication
356 * @dd: the infinipath device
359 static int eeprom_reset(struct ipath_devdata *dd)
361 int clock_cycles_left = 9;
362 u64 *gpioval = &dd->ipath_gpio_out;
363 int ret;
364 unsigned long flags;
366 spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
367 /* Make sure shadows are consistent */
368 dd->ipath_extctrl = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extctrl);
369 *gpioval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_gpio_out);
370 spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
372 ipath_cdbg(VERBOSE, "Resetting i2c eeprom; initial gpioout reg "
373 "is %llx\n", (unsigned long long) *gpioval);
376 * This is to get the i2c into a known state, by first going low,
377 * then tristate sda (and then tristate scl as first thing
378 * in loop)
380 scl_out(dd, i2c_line_low);
381 sda_out(dd, i2c_line_high);
383 /* Clock up to 9 cycles looking for SDA hi, then issue START and STOP */
384 while (clock_cycles_left--) {
385 scl_out(dd, i2c_line_high);
387 /* SDA seen high, issue START by dropping it while SCL high */
388 if (sda_in(dd, 0)) {
389 sda_out(dd, i2c_line_low);
390 scl_out(dd, i2c_line_low);
391 /* ATMEL spec says must be followed by STOP. */
392 scl_out(dd, i2c_line_high);
393 sda_out(dd, i2c_line_high);
394 ret = 0;
395 goto bail;
398 scl_out(dd, i2c_line_low);
401 ret = 1;
403 bail:
404 return ret;
408 * Probe for I2C device at specified address. Returns 0 for "success"
409 * to match rest of this file.
410 * Leave bus in "reasonable" state for further commands.
412 static int i2c_probe(struct ipath_devdata *dd, int devaddr)
414 int ret = 0;
416 ret = eeprom_reset(dd);
417 if (ret) {
418 ipath_dev_err(dd, "Failed reset probing device 0x%02X\n",
419 devaddr);
420 return ret;
423 * Reset no longer leaves bus in start condition, so normal
424 * i2c_startcmd() will do.
426 ret = i2c_startcmd(dd, devaddr | READ_CMD);
427 if (ret)
428 ipath_cdbg(VERBOSE, "Failed startcmd for device 0x%02X\n",
429 devaddr);
430 else {
432 * Device did respond. Complete a single-byte read, because some
433 * devices apparently cannot handle STOP immediately after they
434 * ACK the start-cmd.
436 int data;
437 data = rd_byte(dd);
438 stop_cmd(dd);
439 ipath_cdbg(VERBOSE, "Response from device 0x%02X\n", devaddr);
441 return ret;
445 * Returns the "i2c type". This is a pointer to a struct that describes
446 * the I2C chain on this board. To minimize impact on struct ipath_devdata,
447 * the (small integer) index into the table is actually memoized, rather
448 * then the pointer.
449 * Memoization is because the type is determined on the first call per chip.
450 * An alternative would be to move type determination to early
451 * init code.
453 static struct i2c_chain_desc *ipath_i2c_type(struct ipath_devdata *dd)
455 int idx;
457 /* Get memoized index, from previous successful probes */
458 idx = dd->ipath_i2c_chain_type - 1;
459 if (idx >= 0 && idx < (ARRAY_SIZE(i2c_chains) - 1))
460 goto done;
462 idx = 0;
463 while (i2c_chains[idx].probe_dev != IPATH_NO_DEV) {
464 /* if probe succeeds, this is type */
465 if (!i2c_probe(dd, i2c_chains[idx].probe_dev))
466 break;
467 ++idx;
471 * Old EEPROM (first entry) may require a reset after probe,
472 * rather than being able to "start" after "stop"
474 if (idx == 0)
475 eeprom_reset(dd);
477 if (i2c_chains[idx].probe_dev == IPATH_NO_DEV)
478 idx = -1;
479 else
480 dd->ipath_i2c_chain_type = idx + 1;
481 done:
482 return (idx >= 0) ? i2c_chains + idx : NULL;
485 static int ipath_eeprom_internal_read(struct ipath_devdata *dd,
486 u8 eeprom_offset, void *buffer, int len)
488 int ret;
489 struct i2c_chain_desc *icd;
490 u8 *bp = buffer;
492 ret = 1;
493 icd = ipath_i2c_type(dd);
494 if (!icd)
495 goto bail;
497 if (icd->eeprom_dev == IPATH_NO_DEV) {
498 /* legacy not-really-I2C */
499 ipath_cdbg(VERBOSE, "Start command only address\n");
500 eeprom_offset = (eeprom_offset << 1) | READ_CMD;
501 ret = i2c_startcmd(dd, eeprom_offset);
502 } else {
503 /* Actual I2C */
504 ipath_cdbg(VERBOSE, "Start command uses devaddr\n");
505 if (i2c_startcmd(dd, icd->eeprom_dev | WRITE_CMD)) {
506 ipath_dbg("Failed EEPROM startcmd\n");
507 stop_cmd(dd);
508 ret = 1;
509 goto bail;
511 ret = wr_byte(dd, eeprom_offset);
512 stop_cmd(dd);
513 if (ret) {
514 ipath_dev_err(dd, "Failed to write EEPROM address\n");
515 ret = 1;
516 goto bail;
518 ret = i2c_startcmd(dd, icd->eeprom_dev | READ_CMD);
520 if (ret) {
521 ipath_dbg("Failed startcmd for dev %02X\n", icd->eeprom_dev);
522 stop_cmd(dd);
523 ret = 1;
524 goto bail;
528 * eeprom keeps clocking data out as long as we ack, automatically
529 * incrementing the address.
531 while (len-- > 0) {
532 /* get and store data */
533 *bp++ = rd_byte(dd);
534 /* send ack if not the last byte */
535 if (len)
536 send_ack(dd);
539 stop_cmd(dd);
541 ret = 0;
543 bail:
544 return ret;
547 static int ipath_eeprom_internal_write(struct ipath_devdata *dd, u8 eeprom_offset,
548 const void *buffer, int len)
550 int sub_len;
551 const u8 *bp = buffer;
552 int max_wait_time, i;
553 int ret;
554 struct i2c_chain_desc *icd;
556 ret = 1;
557 icd = ipath_i2c_type(dd);
558 if (!icd)
559 goto bail;
561 while (len > 0) {
562 if (icd->eeprom_dev == IPATH_NO_DEV) {
563 if (i2c_startcmd(dd,
564 (eeprom_offset << 1) | WRITE_CMD)) {
565 ipath_dbg("Failed to start cmd offset %u\n",
566 eeprom_offset);
567 goto failed_write;
569 } else {
570 /* Real I2C */
571 if (i2c_startcmd(dd, icd->eeprom_dev | WRITE_CMD)) {
572 ipath_dbg("Failed EEPROM startcmd\n");
573 goto failed_write;
575 ret = wr_byte(dd, eeprom_offset);
576 if (ret) {
577 ipath_dev_err(dd, "Failed to write EEPROM "
578 "address\n");
579 goto failed_write;
583 sub_len = min(len, 4);
584 eeprom_offset += sub_len;
585 len -= sub_len;
587 for (i = 0; i < sub_len; i++) {
588 if (wr_byte(dd, *bp++)) {
589 ipath_dbg("no ack after byte %u/%u (%u "
590 "total remain)\n", i, sub_len,
591 len + sub_len - i);
592 goto failed_write;
596 stop_cmd(dd);
599 * wait for write complete by waiting for a successful
600 * read (the chip replies with a zero after the write
601 * cmd completes, and before it writes to the eeprom.
602 * The startcmd for the read will fail the ack until
603 * the writes have completed. We do this inline to avoid
604 * the debug prints that are in the real read routine
605 * if the startcmd fails.
606 * We also use the proper device address, so it doesn't matter
607 * whether we have real eeprom_dev. legacy likes any address.
609 max_wait_time = 100;
610 while (i2c_startcmd(dd, icd->eeprom_dev | READ_CMD)) {
611 stop_cmd(dd);
612 if (!--max_wait_time) {
613 ipath_dbg("Did not get successful read to "
614 "complete write\n");
615 goto failed_write;
618 /* now read (and ignore) the resulting byte */
619 rd_byte(dd);
620 stop_cmd(dd);
623 ret = 0;
624 goto bail;
626 failed_write:
627 stop_cmd(dd);
628 ret = 1;
630 bail:
631 return ret;
635 * ipath_eeprom_read - receives bytes from the eeprom via I2C
636 * @dd: the infinipath device
637 * @eeprom_offset: address to read from
638 * @buffer: where to store result
639 * @len: number of bytes to receive
641 int ipath_eeprom_read(struct ipath_devdata *dd, u8 eeprom_offset,
642 void *buff, int len)
644 int ret;
646 ret = mutex_lock_interruptible(&dd->ipath_eep_lock);
647 if (!ret) {
648 ret = ipath_eeprom_internal_read(dd, eeprom_offset, buff, len);
649 mutex_unlock(&dd->ipath_eep_lock);
652 return ret;
656 * ipath_eeprom_write - writes data to the eeprom via I2C
657 * @dd: the infinipath device
658 * @eeprom_offset: where to place data
659 * @buffer: data to write
660 * @len: number of bytes to write
662 int ipath_eeprom_write(struct ipath_devdata *dd, u8 eeprom_offset,
663 const void *buff, int len)
665 int ret;
667 ret = mutex_lock_interruptible(&dd->ipath_eep_lock);
668 if (!ret) {
669 ret = ipath_eeprom_internal_write(dd, eeprom_offset, buff, len);
670 mutex_unlock(&dd->ipath_eep_lock);
673 return ret;
676 static u8 flash_csum(struct ipath_flash *ifp, int adjust)
678 u8 *ip = (u8 *) ifp;
679 u8 csum = 0, len;
682 * Limit length checksummed to max length of actual data.
683 * Checksum of erased eeprom will still be bad, but we avoid
684 * reading past the end of the buffer we were passed.
686 len = ifp->if_length;
687 if (len > sizeof(struct ipath_flash))
688 len = sizeof(struct ipath_flash);
689 while (len--)
690 csum += *ip++;
691 csum -= ifp->if_csum;
692 csum = ~csum;
693 if (adjust)
694 ifp->if_csum = csum;
696 return csum;
700 * ipath_get_guid - get the GUID from the i2c device
701 * @dd: the infinipath device
703 * We have the capability to use the ipath_nguid field, and get
704 * the guid from the first chip's flash, to use for all of them.
706 void ipath_get_eeprom_info(struct ipath_devdata *dd)
708 void *buf;
709 struct ipath_flash *ifp;
710 __be64 guid;
711 int len, eep_stat;
712 u8 csum, *bguid;
713 int t = dd->ipath_unit;
714 struct ipath_devdata *dd0 = ipath_lookup(0);
716 if (t && dd0->ipath_nguid > 1 && t <= dd0->ipath_nguid) {
717 u8 oguid;
718 dd->ipath_guid = dd0->ipath_guid;
719 bguid = (u8 *) & dd->ipath_guid;
721 oguid = bguid[7];
722 bguid[7] += t;
723 if (oguid > bguid[7]) {
724 if (bguid[6] == 0xff) {
725 if (bguid[5] == 0xff) {
726 ipath_dev_err(
728 "Can't set %s GUID from "
729 "base, wraps to OUI!\n",
730 ipath_get_unit_name(t));
731 dd->ipath_guid = 0;
732 goto bail;
734 bguid[5]++;
736 bguid[6]++;
738 dd->ipath_nguid = 1;
740 ipath_dbg("nguid %u, so adding %u to device 0 guid, "
741 "for %llx\n",
742 dd0->ipath_nguid, t,
743 (unsigned long long) be64_to_cpu(dd->ipath_guid));
744 goto bail;
748 * read full flash, not just currently used part, since it may have
749 * been written with a newer definition
750 * */
751 len = sizeof(struct ipath_flash);
752 buf = vmalloc(len);
753 if (!buf) {
754 ipath_dev_err(dd, "Couldn't allocate memory to read %u "
755 "bytes from eeprom for GUID\n", len);
756 goto bail;
759 mutex_lock(&dd->ipath_eep_lock);
760 eep_stat = ipath_eeprom_internal_read(dd, 0, buf, len);
761 mutex_unlock(&dd->ipath_eep_lock);
763 if (eep_stat) {
764 ipath_dev_err(dd, "Failed reading GUID from eeprom\n");
765 goto done;
767 ifp = (struct ipath_flash *)buf;
769 csum = flash_csum(ifp, 0);
770 if (csum != ifp->if_csum) {
771 dev_info(&dd->pcidev->dev, "Bad I2C flash checksum: "
772 "0x%x, not 0x%x\n", csum, ifp->if_csum);
773 goto done;
775 if (*(__be64 *) ifp->if_guid == cpu_to_be64(0) ||
776 *(__be64 *) ifp->if_guid == ~cpu_to_be64(0)) {
777 ipath_dev_err(dd, "Invalid GUID %llx from flash; "
778 "ignoring\n",
779 *(unsigned long long *) ifp->if_guid);
780 /* don't allow GUID if all 0 or all 1's */
781 goto done;
784 /* complain, but allow it */
785 if (*(u64 *) ifp->if_guid == 0x100007511000000ULL)
786 dev_info(&dd->pcidev->dev, "Warning, GUID %llx is "
787 "default, probably not correct!\n",
788 *(unsigned long long *) ifp->if_guid);
790 bguid = ifp->if_guid;
791 if (!bguid[0] && !bguid[1] && !bguid[2]) {
792 /* original incorrect GUID format in flash; fix in
793 * core copy, by shifting up 2 octets; don't need to
794 * change top octet, since both it and shifted are
795 * 0.. */
796 bguid[1] = bguid[3];
797 bguid[2] = bguid[4];
798 bguid[3] = bguid[4] = 0;
799 guid = *(__be64 *) ifp->if_guid;
800 ipath_cdbg(VERBOSE, "Old GUID format in flash, top 3 zero, "
801 "shifting 2 octets\n");
802 } else
803 guid = *(__be64 *) ifp->if_guid;
804 dd->ipath_guid = guid;
805 dd->ipath_nguid = ifp->if_numguid;
807 * Things are slightly complicated by the desire to transparently
808 * support both the Pathscale 10-digit serial number and the QLogic
809 * 13-character version.
811 if ((ifp->if_fversion > 1) && ifp->if_sprefix[0]
812 && ((u8 *)ifp->if_sprefix)[0] != 0xFF) {
813 /* This board has a Serial-prefix, which is stored
814 * elsewhere for backward-compatibility.
816 char *snp = dd->ipath_serial;
817 memcpy(snp, ifp->if_sprefix, sizeof ifp->if_sprefix);
818 snp[sizeof ifp->if_sprefix] = '\0';
819 len = strlen(snp);
820 snp += len;
821 len = (sizeof dd->ipath_serial) - len;
822 if (len > sizeof ifp->if_serial) {
823 len = sizeof ifp->if_serial;
825 memcpy(snp, ifp->if_serial, len);
826 } else
827 memcpy(dd->ipath_serial, ifp->if_serial,
828 sizeof ifp->if_serial);
829 if (!strstr(ifp->if_comment, "Tested successfully"))
830 ipath_dev_err(dd, "Board SN %s did not pass functional "
831 "test: %s\n", dd->ipath_serial,
832 ifp->if_comment);
834 ipath_cdbg(VERBOSE, "Initted GUID to %llx from eeprom\n",
835 (unsigned long long) be64_to_cpu(dd->ipath_guid));
837 memcpy(&dd->ipath_eep_st_errs, &ifp->if_errcntp, IPATH_EEP_LOG_CNT);
839 * Power-on (actually "active") hours are kept as little-endian value
840 * in EEPROM, but as seconds in a (possibly as small as 24-bit)
841 * atomic_t while running.
843 atomic_set(&dd->ipath_active_time, 0);
844 dd->ipath_eep_hrs = ifp->if_powerhour[0] | (ifp->if_powerhour[1] << 8);
846 done:
847 vfree(buf);
849 bail:;
853 * ipath_update_eeprom_log - copy active-time and error counters to eeprom
854 * @dd: the infinipath device
856 * Although the time is kept as seconds in the ipath_devdata struct, it is
857 * rounded to hours for re-write, as we have only 16 bits in EEPROM.
858 * First-cut code reads whole (expected) struct ipath_flash, modifies,
859 * re-writes. Future direction: read/write only what we need, assuming
860 * that the EEPROM had to have been "good enough" for driver init, and
861 * if not, we aren't making it worse.
865 int ipath_update_eeprom_log(struct ipath_devdata *dd)
867 void *buf;
868 struct ipath_flash *ifp;
869 int len, hi_water;
870 uint32_t new_time, new_hrs;
871 u8 csum;
872 int ret, idx;
873 unsigned long flags;
875 /* first, check if we actually need to do anything. */
876 ret = 0;
877 for (idx = 0; idx < IPATH_EEP_LOG_CNT; ++idx) {
878 if (dd->ipath_eep_st_new_errs[idx]) {
879 ret = 1;
880 break;
883 new_time = atomic_read(&dd->ipath_active_time);
885 if (ret == 0 && new_time < 3600)
886 return 0;
889 * The quick-check above determined that there is something worthy
890 * of logging, so get current contents and do a more detailed idea.
891 * read full flash, not just currently used part, since it may have
892 * been written with a newer definition
894 len = sizeof(struct ipath_flash);
895 buf = vmalloc(len);
896 ret = 1;
897 if (!buf) {
898 ipath_dev_err(dd, "Couldn't allocate memory to read %u "
899 "bytes from eeprom for logging\n", len);
900 goto bail;
903 /* Grab semaphore and read current EEPROM. If we get an
904 * error, let go, but if not, keep it until we finish write.
906 ret = mutex_lock_interruptible(&dd->ipath_eep_lock);
907 if (ret) {
908 ipath_dev_err(dd, "Unable to acquire EEPROM for logging\n");
909 goto free_bail;
911 ret = ipath_eeprom_internal_read(dd, 0, buf, len);
912 if (ret) {
913 mutex_unlock(&dd->ipath_eep_lock);
914 ipath_dev_err(dd, "Unable read EEPROM for logging\n");
915 goto free_bail;
917 ifp = (struct ipath_flash *)buf;
919 csum = flash_csum(ifp, 0);
920 if (csum != ifp->if_csum) {
921 mutex_unlock(&dd->ipath_eep_lock);
922 ipath_dev_err(dd, "EEPROM cks err (0x%02X, S/B 0x%02X)\n",
923 csum, ifp->if_csum);
924 ret = 1;
925 goto free_bail;
927 hi_water = 0;
928 spin_lock_irqsave(&dd->ipath_eep_st_lock, flags);
929 for (idx = 0; idx < IPATH_EEP_LOG_CNT; ++idx) {
930 int new_val = dd->ipath_eep_st_new_errs[idx];
931 if (new_val) {
933 * If we have seen any errors, add to EEPROM values
934 * We need to saturate at 0xFF (255) and we also
935 * would need to adjust the checksum if we were
936 * trying to minimize EEPROM traffic
937 * Note that we add to actual current count in EEPROM,
938 * in case it was altered while we were running.
940 new_val += ifp->if_errcntp[idx];
941 if (new_val > 0xFF)
942 new_val = 0xFF;
943 if (ifp->if_errcntp[idx] != new_val) {
944 ifp->if_errcntp[idx] = new_val;
945 hi_water = offsetof(struct ipath_flash,
946 if_errcntp) + idx;
949 * update our shadow (used to minimize EEPROM
950 * traffic), to match what we are about to write.
952 dd->ipath_eep_st_errs[idx] = new_val;
953 dd->ipath_eep_st_new_errs[idx] = 0;
957 * now update active-time. We would like to round to the nearest hour
958 * but unless atomic_t are sure to be proper signed ints we cannot,
959 * because we need to account for what we "transfer" to EEPROM and
960 * if we log an hour at 31 minutes, then we would need to set
961 * active_time to -29 to accurately count the _next_ hour.
963 if (new_time >= 3600) {
964 new_hrs = new_time / 3600;
965 atomic_sub((new_hrs * 3600), &dd->ipath_active_time);
966 new_hrs += dd->ipath_eep_hrs;
967 if (new_hrs > 0xFFFF)
968 new_hrs = 0xFFFF;
969 dd->ipath_eep_hrs = new_hrs;
970 if ((new_hrs & 0xFF) != ifp->if_powerhour[0]) {
971 ifp->if_powerhour[0] = new_hrs & 0xFF;
972 hi_water = offsetof(struct ipath_flash, if_powerhour);
974 if ((new_hrs >> 8) != ifp->if_powerhour[1]) {
975 ifp->if_powerhour[1] = new_hrs >> 8;
976 hi_water = offsetof(struct ipath_flash, if_powerhour)
977 + 1;
981 * There is a tiny possibility that we could somehow fail to write
982 * the EEPROM after updating our shadows, but problems from holding
983 * the spinlock too long are a much bigger issue.
985 spin_unlock_irqrestore(&dd->ipath_eep_st_lock, flags);
986 if (hi_water) {
987 /* we made some change to the data, uopdate cksum and write */
988 csum = flash_csum(ifp, 1);
989 ret = ipath_eeprom_internal_write(dd, 0, buf, hi_water + 1);
991 mutex_unlock(&dd->ipath_eep_lock);
992 if (ret)
993 ipath_dev_err(dd, "Failed updating EEPROM\n");
995 free_bail:
996 vfree(buf);
997 bail:
998 return ret;
1003 * ipath_inc_eeprom_err - increment one of the four error counters
1004 * that are logged to EEPROM.
1005 * @dd: the infinipath device
1006 * @eidx: 0..3, the counter to increment
1007 * @incr: how much to add
1009 * Each counter is 8-bits, and saturates at 255 (0xFF). They
1010 * are copied to the EEPROM (aka flash) whenever ipath_update_eeprom_log()
1011 * is called, but it can only be called in a context that allows sleep.
1012 * This function can be called even at interrupt level.
1015 void ipath_inc_eeprom_err(struct ipath_devdata *dd, u32 eidx, u32 incr)
1017 uint new_val;
1018 unsigned long flags;
1020 spin_lock_irqsave(&dd->ipath_eep_st_lock, flags);
1021 new_val = dd->ipath_eep_st_new_errs[eidx] + incr;
1022 if (new_val > 255)
1023 new_val = 255;
1024 dd->ipath_eep_st_new_errs[eidx] = new_val;
1025 spin_unlock_irqrestore(&dd->ipath_eep_st_lock, flags);
1026 return;
1029 static int ipath_tempsense_internal_read(struct ipath_devdata *dd, u8 regnum)
1031 int ret;
1032 struct i2c_chain_desc *icd;
1034 ret = -ENOENT;
1036 icd = ipath_i2c_type(dd);
1037 if (!icd)
1038 goto bail;
1040 if (icd->temp_dev == IPATH_NO_DEV) {
1041 /* tempsense only exists on new, real-I2C boards */
1042 ret = -ENXIO;
1043 goto bail;
1046 if (i2c_startcmd(dd, icd->temp_dev | WRITE_CMD)) {
1047 ipath_dbg("Failed tempsense startcmd\n");
1048 stop_cmd(dd);
1049 ret = -ENXIO;
1050 goto bail;
1052 ret = wr_byte(dd, regnum);
1053 stop_cmd(dd);
1054 if (ret) {
1055 ipath_dev_err(dd, "Failed tempsense WR command %02X\n",
1056 regnum);
1057 ret = -ENXIO;
1058 goto bail;
1060 if (i2c_startcmd(dd, icd->temp_dev | READ_CMD)) {
1061 ipath_dbg("Failed tempsense RD startcmd\n");
1062 stop_cmd(dd);
1063 ret = -ENXIO;
1064 goto bail;
1067 * We can only clock out one byte per command, sensibly
1069 ret = rd_byte(dd);
1070 stop_cmd(dd);
1072 bail:
1073 return ret;
1076 #define VALID_TS_RD_REG_MASK 0xBF
1079 * ipath_tempsense_read - read register of temp sensor via I2C
1080 * @dd: the infinipath device
1081 * @regnum: register to read from
1083 * returns reg contents (0..255) or < 0 for error
1085 int ipath_tempsense_read(struct ipath_devdata *dd, u8 regnum)
1087 int ret;
1089 if (regnum > 7)
1090 return -EINVAL;
1092 /* return a bogus value for (the one) register we do not have */
1093 if (!((1 << regnum) & VALID_TS_RD_REG_MASK))
1094 return 0;
1096 ret = mutex_lock_interruptible(&dd->ipath_eep_lock);
1097 if (!ret) {
1098 ret = ipath_tempsense_internal_read(dd, regnum);
1099 mutex_unlock(&dd->ipath_eep_lock);
1103 * There are three possibilities here:
1104 * ret is actual value (0..255)
1105 * ret is -ENXIO or -EINVAL from code in this file
1106 * ret is -EINTR from mutex_lock_interruptible.
1108 return ret;
1111 static int ipath_tempsense_internal_write(struct ipath_devdata *dd,
1112 u8 regnum, u8 data)
1114 int ret = -ENOENT;
1115 struct i2c_chain_desc *icd;
1117 icd = ipath_i2c_type(dd);
1118 if (!icd)
1119 goto bail;
1121 if (icd->temp_dev == IPATH_NO_DEV) {
1122 /* tempsense only exists on new, real-I2C boards */
1123 ret = -ENXIO;
1124 goto bail;
1126 if (i2c_startcmd(dd, icd->temp_dev | WRITE_CMD)) {
1127 ipath_dbg("Failed tempsense startcmd\n");
1128 stop_cmd(dd);
1129 ret = -ENXIO;
1130 goto bail;
1132 ret = wr_byte(dd, regnum);
1133 if (ret) {
1134 stop_cmd(dd);
1135 ipath_dev_err(dd, "Failed to write tempsense command %02X\n",
1136 regnum);
1137 ret = -ENXIO;
1138 goto bail;
1140 ret = wr_byte(dd, data);
1141 stop_cmd(dd);
1142 ret = i2c_startcmd(dd, icd->temp_dev | READ_CMD);
1143 if (ret) {
1144 ipath_dev_err(dd, "Failed tempsense data wrt to %02X\n",
1145 regnum);
1146 ret = -ENXIO;
1149 bail:
1150 return ret;
1153 #define VALID_TS_WR_REG_MASK ((1 << 9) | (1 << 0xB) | (1 << 0xD))
1156 * ipath_tempsense_write - write register of temp sensor via I2C
1157 * @dd: the infinipath device
1158 * @regnum: register to write
1159 * @data: data to write
1161 * returns 0 for success or < 0 for error
1163 int ipath_tempsense_write(struct ipath_devdata *dd, u8 regnum, u8 data)
1165 int ret;
1167 if (regnum > 15 || !((1 << regnum) & VALID_TS_WR_REG_MASK))
1168 return -EINVAL;
1170 ret = mutex_lock_interruptible(&dd->ipath_eep_lock);
1171 if (!ret) {
1172 ret = ipath_tempsense_internal_write(dd, regnum, data);
1173 mutex_unlock(&dd->ipath_eep_lock);
1177 * There are three possibilities here:
1178 * ret is 0 for success
1179 * ret is -ENXIO or -EINVAL from code in this file
1180 * ret is -EINTR from mutex_lock_interruptible.
1182 return ret;