2 * Driver for mt2063 Micronas tuner
4 * Copyright (c) 2011 Mauro Carvalho Chehab <mchehab@redhat.com>
6 * This driver came from a driver originally written by:
7 * Henry Wang <Henry.wang@AzureWave.com>
8 * Made publicly available by Terratec, at:
9 * http://linux.terratec.de/files/TERRATEC_H7/20110323_TERRATEC_H7_Linux.tar.gz
10 * The original driver's license is GPL, as declared with MODULE_LICENSE()
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation under version 2 of the License.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
22 #include <linux/init.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/videodev2.h>
30 static unsigned int debug
;
31 module_param(debug
, int, 0644);
32 MODULE_PARM_DESC(debug
, "Set Verbosity level");
34 #define dprintk(level, fmt, arg...) do { \
36 printk(KERN_DEBUG "mt2063 %s: " fmt, __func__, ## arg); \
40 /* positive error codes used internally */
42 /* Info: Unavoidable LO-related spur may be present in the output */
43 #define MT2063_SPUR_PRESENT_ERR (0x00800000)
45 /* Info: Mask of bits used for # of LO-related spurs that were avoided during tuning */
46 #define MT2063_SPUR_CNT_MASK (0x001f0000)
47 #define MT2063_SPUR_SHIFT (16)
49 /* Info: Upconverter frequency is out of range (may be reason for MT_UPC_UNLOCK) */
50 #define MT2063_UPC_RANGE (0x04000000)
52 /* Info: Downconverter frequency is out of range (may be reason for MT_DPC_UNLOCK) */
53 #define MT2063_DNC_RANGE (0x08000000)
56 * Constant defining the version of the following structure
57 * and therefore the API for this code.
59 * When compiling the tuner driver, the preprocessor will
60 * check against this version number to make sure that
61 * it matches the version that the tuner driver knows about.
64 /* DECT Frequency Avoidance */
65 #define MT2063_DECT_AVOID_US_FREQS 0x00000001
67 #define MT2063_DECT_AVOID_EURO_FREQS 0x00000002
69 #define MT2063_EXCLUDE_US_DECT_FREQUENCIES(s) (((s) & MT2063_DECT_AVOID_US_FREQS) != 0)
71 #define MT2063_EXCLUDE_EURO_DECT_FREQUENCIES(s) (((s) & MT2063_DECT_AVOID_EURO_FREQS) != 0)
73 enum MT2063_DECT_Avoid_Type
{
74 MT2063_NO_DECT_AVOIDANCE
= 0, /* Do not create DECT exclusion zones. */
75 MT2063_AVOID_US_DECT
= MT2063_DECT_AVOID_US_FREQS
, /* Avoid US DECT frequencies. */
76 MT2063_AVOID_EURO_DECT
= MT2063_DECT_AVOID_EURO_FREQS
, /* Avoid European DECT frequencies. */
77 MT2063_AVOID_BOTH
/* Avoid both regions. Not typically used. */
80 #define MT2063_MAX_ZONES 48
82 struct MT2063_ExclZone_t
{
85 struct MT2063_ExclZone_t
*next_
;
89 * Structure of data needed for Spur Avoidance
91 struct MT2063_AvoidSpursData_t
{
103 u32 f_LO1_FracN_Avoid
;
104 u32 f_LO2_FracN_Avoid
;
106 u32 f_min_LO_Separation
;
109 enum MT2063_DECT_Avoid_Type avoidDECT
;
114 struct MT2063_ExclZone_t
*freeZones
;
115 struct MT2063_ExclZone_t
*usedZones
;
116 struct MT2063_ExclZone_t MT2063_ExclZones
[MT2063_MAX_ZONES
];
120 * Parameter for function MT2063_SetPowerMask that specifies the power down
121 * of various sections of the MT2063.
123 enum MT2063_Mask_Bits
{
124 MT2063_REG_SD
= 0x0040, /* Shutdown regulator */
125 MT2063_SRO_SD
= 0x0020, /* Shutdown SRO */
126 MT2063_AFC_SD
= 0x0010, /* Shutdown AFC A/D */
127 MT2063_PD_SD
= 0x0002, /* Enable power detector shutdown */
128 MT2063_PDADC_SD
= 0x0001, /* Enable power detector A/D shutdown */
129 MT2063_VCO_SD
= 0x8000, /* Enable VCO shutdown */
130 MT2063_LTX_SD
= 0x4000, /* Enable LTX shutdown */
131 MT2063_LT1_SD
= 0x2000, /* Enable LT1 shutdown */
132 MT2063_LNA_SD
= 0x1000, /* Enable LNA shutdown */
133 MT2063_UPC_SD
= 0x0800, /* Enable upconverter shutdown */
134 MT2063_DNC_SD
= 0x0400, /* Enable downconverter shutdown */
135 MT2063_VGA_SD
= 0x0200, /* Enable VGA shutdown */
136 MT2063_AMP_SD
= 0x0100, /* Enable AMP shutdown */
137 MT2063_ALL_SD
= 0xFF73, /* All shutdown bits for this tuner */
138 MT2063_NONE_SD
= 0x0000 /* No shutdown bits */
142 * Possible values for MT2063_DNC_OUTPUT
144 enum MT2063_DNC_Output_Enable
{
152 * Two-wire serial bus subaddresses of the tuner registers.
153 * Also known as the tuner's register addresses.
155 enum MT2063_Register_Offsets
{
156 MT2063_REG_PART_REV
= 0, /* 0x00: Part/Rev Code */
157 MT2063_REG_LO1CQ_1
, /* 0x01: LO1C Queued Byte 1 */
158 MT2063_REG_LO1CQ_2
, /* 0x02: LO1C Queued Byte 2 */
159 MT2063_REG_LO2CQ_1
, /* 0x03: LO2C Queued Byte 1 */
160 MT2063_REG_LO2CQ_2
, /* 0x04: LO2C Queued Byte 2 */
161 MT2063_REG_LO2CQ_3
, /* 0x05: LO2C Queued Byte 3 */
162 MT2063_REG_RSVD_06
, /* 0x06: Reserved */
163 MT2063_REG_LO_STATUS
, /* 0x07: LO Status */
164 MT2063_REG_FIFFC
, /* 0x08: FIFF Center */
165 MT2063_REG_CLEARTUNE
, /* 0x09: ClearTune Filter */
166 MT2063_REG_ADC_OUT
, /* 0x0A: ADC_OUT */
167 MT2063_REG_LO1C_1
, /* 0x0B: LO1C Byte 1 */
168 MT2063_REG_LO1C_2
, /* 0x0C: LO1C Byte 2 */
169 MT2063_REG_LO2C_1
, /* 0x0D: LO2C Byte 1 */
170 MT2063_REG_LO2C_2
, /* 0x0E: LO2C Byte 2 */
171 MT2063_REG_LO2C_3
, /* 0x0F: LO2C Byte 3 */
172 MT2063_REG_RSVD_10
, /* 0x10: Reserved */
173 MT2063_REG_PWR_1
, /* 0x11: PWR Byte 1 */
174 MT2063_REG_PWR_2
, /* 0x12: PWR Byte 2 */
175 MT2063_REG_TEMP_STATUS
, /* 0x13: Temp Status */
176 MT2063_REG_XO_STATUS
, /* 0x14: Crystal Status */
177 MT2063_REG_RF_STATUS
, /* 0x15: RF Attn Status */
178 MT2063_REG_FIF_STATUS
, /* 0x16: FIF Attn Status */
179 MT2063_REG_LNA_OV
, /* 0x17: LNA Attn Override */
180 MT2063_REG_RF_OV
, /* 0x18: RF Attn Override */
181 MT2063_REG_FIF_OV
, /* 0x19: FIF Attn Override */
182 MT2063_REG_LNA_TGT
, /* 0x1A: Reserved */
183 MT2063_REG_PD1_TGT
, /* 0x1B: Pwr Det 1 Target */
184 MT2063_REG_PD2_TGT
, /* 0x1C: Pwr Det 2 Target */
185 MT2063_REG_RSVD_1D
, /* 0x1D: Reserved */
186 MT2063_REG_RSVD_1E
, /* 0x1E: Reserved */
187 MT2063_REG_RSVD_1F
, /* 0x1F: Reserved */
188 MT2063_REG_RSVD_20
, /* 0x20: Reserved */
189 MT2063_REG_BYP_CTRL
, /* 0x21: Bypass Control */
190 MT2063_REG_RSVD_22
, /* 0x22: Reserved */
191 MT2063_REG_RSVD_23
, /* 0x23: Reserved */
192 MT2063_REG_RSVD_24
, /* 0x24: Reserved */
193 MT2063_REG_RSVD_25
, /* 0x25: Reserved */
194 MT2063_REG_RSVD_26
, /* 0x26: Reserved */
195 MT2063_REG_RSVD_27
, /* 0x27: Reserved */
196 MT2063_REG_FIFF_CTRL
, /* 0x28: FIFF Control */
197 MT2063_REG_FIFF_OFFSET
, /* 0x29: FIFF Offset */
198 MT2063_REG_CTUNE_CTRL
, /* 0x2A: Reserved */
199 MT2063_REG_CTUNE_OV
, /* 0x2B: Reserved */
200 MT2063_REG_CTRL_2C
, /* 0x2C: Reserved */
201 MT2063_REG_FIFF_CTRL2
, /* 0x2D: Fiff Control */
202 MT2063_REG_RSVD_2E
, /* 0x2E: Reserved */
203 MT2063_REG_DNC_GAIN
, /* 0x2F: DNC Control */
204 MT2063_REG_VGA_GAIN
, /* 0x30: VGA Gain Ctrl */
205 MT2063_REG_RSVD_31
, /* 0x31: Reserved */
206 MT2063_REG_TEMP_SEL
, /* 0x32: Temperature Selection */
207 MT2063_REG_RSVD_33
, /* 0x33: Reserved */
208 MT2063_REG_RSVD_34
, /* 0x34: Reserved */
209 MT2063_REG_RSVD_35
, /* 0x35: Reserved */
210 MT2063_REG_RSVD_36
, /* 0x36: Reserved */
211 MT2063_REG_RSVD_37
, /* 0x37: Reserved */
212 MT2063_REG_RSVD_38
, /* 0x38: Reserved */
213 MT2063_REG_RSVD_39
, /* 0x39: Reserved */
214 MT2063_REG_RSVD_3A
, /* 0x3A: Reserved */
215 MT2063_REG_RSVD_3B
, /* 0x3B: Reserved */
216 MT2063_REG_RSVD_3C
, /* 0x3C: Reserved */
220 struct mt2063_state
{
221 struct i2c_adapter
*i2c
;
225 const struct mt2063_config
*config
;
226 struct dvb_tuner_ops ops
;
227 struct dvb_frontend
*frontend
;
228 struct tuner_state status
;
236 struct MT2063_AvoidSpursData_t AS_Data
;
242 u8 reg
[MT2063_REG_END_REGS
];
246 * mt2063_write - Write data into the I2C bus
248 static u32
mt2063_write(struct mt2063_state
*state
, u8 reg
, u8
*data
, u32 len
)
250 struct dvb_frontend
*fe
= state
->frontend
;
253 struct i2c_msg msg
= {
254 .addr
= state
->config
->tuner_address
,
263 memcpy(msg
.buf
+ 1, data
, len
);
265 if (fe
->ops
.i2c_gate_ctrl
)
266 fe
->ops
.i2c_gate_ctrl(fe
, 1);
267 ret
= i2c_transfer(state
->i2c
, &msg
, 1);
268 if (fe
->ops
.i2c_gate_ctrl
)
269 fe
->ops
.i2c_gate_ctrl(fe
, 0);
272 printk(KERN_ERR
"%s error ret=%d\n", __func__
, ret
);
278 * mt2063_write - Write register data into the I2C bus, caching the value
280 static u32
mt2063_setreg(struct mt2063_state
*state
, u8 reg
, u8 val
)
286 if (reg
>= MT2063_REG_END_REGS
)
289 status
= mt2063_write(state
, reg
, &val
, 1);
293 state
->reg
[reg
] = val
;
299 * mt2063_read - Read data from the I2C bus
301 static u32
mt2063_read(struct mt2063_state
*state
,
302 u8 subAddress
, u8
*pData
, u32 cnt
)
304 u32 status
= 0; /* Status to be returned */
305 struct dvb_frontend
*fe
= state
->frontend
;
308 dprintk(2, "addr 0x%02x, cnt %d\n", subAddress
, cnt
);
310 if (fe
->ops
.i2c_gate_ctrl
)
311 fe
->ops
.i2c_gate_ctrl(fe
, 1);
313 for (i
= 0; i
< cnt
; i
++) {
314 u8 b0
[] = { subAddress
+ i
};
315 struct i2c_msg msg
[] = {
317 .addr
= state
->config
->tuner_address
,
322 .addr
= state
->config
->tuner_address
,
329 status
= i2c_transfer(state
->i2c
, msg
, 2);
330 dprintk(2, "addr 0x%02x, ret = %d, val = 0x%02x\n",
331 subAddress
+ i
, status
, *(pData
+ i
));
335 if (fe
->ops
.i2c_gate_ctrl
)
336 fe
->ops
.i2c_gate_ctrl(fe
, 0);
339 printk(KERN_ERR
"Can't read from address 0x%02x,\n",
346 * FIXME: Is this really needed?
348 static int MT2063_Sleep(struct dvb_frontend
*fe
)
351 * ToDo: Add code here to implement a OS blocking
359 * Microtune spur avoidance
362 /* Implement ceiling, floor functions. */
363 #define ceil(n, d) (((n) < 0) ? (-((-(n))/(d))) : (n)/(d) + ((n)%(d) != 0))
364 #define floor(n, d) (((n) < 0) ? (-((-(n))/(d))) - ((n)%(d) != 0) : (n)/(d))
366 struct MT2063_FIFZone_t
{
371 static struct MT2063_ExclZone_t
*InsertNode(struct MT2063_AvoidSpursData_t
373 struct MT2063_ExclZone_t
*pPrevNode
)
375 struct MT2063_ExclZone_t
*pNode
;
379 /* Check for a node in the free list */
380 if (pAS_Info
->freeZones
!= NULL
) {
381 /* Use one from the free list */
382 pNode
= pAS_Info
->freeZones
;
383 pAS_Info
->freeZones
= pNode
->next_
;
385 /* Grab a node from the array */
386 pNode
= &pAS_Info
->MT2063_ExclZones
[pAS_Info
->nZones
];
389 if (pPrevNode
!= NULL
) {
390 pNode
->next_
= pPrevNode
->next_
;
391 pPrevNode
->next_
= pNode
;
392 } else { /* insert at the beginning of the list */
394 pNode
->next_
= pAS_Info
->usedZones
;
395 pAS_Info
->usedZones
= pNode
;
402 static struct MT2063_ExclZone_t
*RemoveNode(struct MT2063_AvoidSpursData_t
404 struct MT2063_ExclZone_t
*pPrevNode
,
405 struct MT2063_ExclZone_t
408 struct MT2063_ExclZone_t
*pNext
= pNodeToRemove
->next_
;
412 /* Make previous node point to the subsequent node */
413 if (pPrevNode
!= NULL
)
414 pPrevNode
->next_
= pNext
;
416 /* Add pNodeToRemove to the beginning of the freeZones */
417 pNodeToRemove
->next_
= pAS_Info
->freeZones
;
418 pAS_Info
->freeZones
= pNodeToRemove
;
420 /* Decrement node count */
429 * Add (and merge) an exclusion zone into the list.
430 * If the range (f_min, f_max) is totally outside the
431 * 1st IF BW, ignore the entry.
432 * If the range (f_min, f_max) is negative, ignore the entry.
434 static void MT2063_AddExclZone(struct MT2063_AvoidSpursData_t
*pAS_Info
,
435 u32 f_min
, u32 f_max
)
437 struct MT2063_ExclZone_t
*pNode
= pAS_Info
->usedZones
;
438 struct MT2063_ExclZone_t
*pPrev
= NULL
;
439 struct MT2063_ExclZone_t
*pNext
= NULL
;
443 /* Check to see if this overlaps the 1st IF filter */
444 if ((f_max
> (pAS_Info
->f_if1_Center
- (pAS_Info
->f_if1_bw
/ 2)))
445 && (f_min
< (pAS_Info
->f_if1_Center
+ (pAS_Info
->f_if1_bw
/ 2)))
446 && (f_min
< f_max
)) {
450 * New entry: |---| |--| |--| |-| |---| |--|
452 * Existing: |--| |--| |--| |---| |-| |--|
455 /* Check for our place in the list */
456 while ((pNode
!= NULL
) && (pNode
->max_
< f_min
)) {
458 pNode
= pNode
->next_
;
461 if ((pNode
!= NULL
) && (pNode
->min_
< f_max
)) {
462 /* Combine me with pNode */
463 if (f_min
< pNode
->min_
)
465 if (f_max
> pNode
->max_
)
468 pNode
= InsertNode(pAS_Info
, pPrev
);
473 /* Look for merging possibilities */
474 pNext
= pNode
->next_
;
475 while ((pNext
!= NULL
) && (pNext
->min_
< pNode
->max_
)) {
476 if (pNext
->max_
> pNode
->max_
)
477 pNode
->max_
= pNext
->max_
;
478 /* Remove pNext, return ptr to pNext->next */
479 pNext
= RemoveNode(pAS_Info
, pNode
, pNext
);
485 * Reset all exclusion zones.
486 * Add zones to protect the PLL FracN regions near zero
488 static void MT2063_ResetExclZones(struct MT2063_AvoidSpursData_t
*pAS_Info
)
494 pAS_Info
->nZones
= 0; /* this clears the used list */
495 pAS_Info
->usedZones
= NULL
; /* reset ptr */
496 pAS_Info
->freeZones
= NULL
; /* reset ptr */
500 ((pAS_Info
->f_if1_Center
- pAS_Info
->f_if1_bw
/ 2 +
501 pAS_Info
->f_in
) / pAS_Info
->f_ref
) - pAS_Info
->f_in
;
503 pAS_Info
->f_if1_Center
+ pAS_Info
->f_if1_bw
/ 2 +
504 pAS_Info
->f_LO1_FracN_Avoid
) {
505 /* Exclude LO1 FracN */
506 MT2063_AddExclZone(pAS_Info
,
507 center
- pAS_Info
->f_LO1_FracN_Avoid
,
509 MT2063_AddExclZone(pAS_Info
, center
+ 1,
510 center
+ pAS_Info
->f_LO1_FracN_Avoid
);
511 center
+= pAS_Info
->f_ref
;
516 ((pAS_Info
->f_if1_Center
- pAS_Info
->f_if1_bw
/ 2 -
517 pAS_Info
->f_out
) / pAS_Info
->f_ref
) + pAS_Info
->f_out
;
519 pAS_Info
->f_if1_Center
+ pAS_Info
->f_if1_bw
/ 2 +
520 pAS_Info
->f_LO2_FracN_Avoid
) {
521 /* Exclude LO2 FracN */
522 MT2063_AddExclZone(pAS_Info
,
523 center
- pAS_Info
->f_LO2_FracN_Avoid
,
525 MT2063_AddExclZone(pAS_Info
, center
+ 1,
526 center
+ pAS_Info
->f_LO2_FracN_Avoid
);
527 center
+= pAS_Info
->f_ref
;
530 if (MT2063_EXCLUDE_US_DECT_FREQUENCIES(pAS_Info
->avoidDECT
)) {
531 /* Exclude LO1 values that conflict with DECT channels */
532 MT2063_AddExclZone(pAS_Info
, 1920836000 - pAS_Info
->f_in
, 1922236000 - pAS_Info
->f_in
); /* Ctr = 1921.536 */
533 MT2063_AddExclZone(pAS_Info
, 1922564000 - pAS_Info
->f_in
, 1923964000 - pAS_Info
->f_in
); /* Ctr = 1923.264 */
534 MT2063_AddExclZone(pAS_Info
, 1924292000 - pAS_Info
->f_in
, 1925692000 - pAS_Info
->f_in
); /* Ctr = 1924.992 */
535 MT2063_AddExclZone(pAS_Info
, 1926020000 - pAS_Info
->f_in
, 1927420000 - pAS_Info
->f_in
); /* Ctr = 1926.720 */
536 MT2063_AddExclZone(pAS_Info
, 1927748000 - pAS_Info
->f_in
, 1929148000 - pAS_Info
->f_in
); /* Ctr = 1928.448 */
539 if (MT2063_EXCLUDE_EURO_DECT_FREQUENCIES(pAS_Info
->avoidDECT
)) {
540 MT2063_AddExclZone(pAS_Info
, 1896644000 - pAS_Info
->f_in
, 1898044000 - pAS_Info
->f_in
); /* Ctr = 1897.344 */
541 MT2063_AddExclZone(pAS_Info
, 1894916000 - pAS_Info
->f_in
, 1896316000 - pAS_Info
->f_in
); /* Ctr = 1895.616 */
542 MT2063_AddExclZone(pAS_Info
, 1893188000 - pAS_Info
->f_in
, 1894588000 - pAS_Info
->f_in
); /* Ctr = 1893.888 */
543 MT2063_AddExclZone(pAS_Info
, 1891460000 - pAS_Info
->f_in
, 1892860000 - pAS_Info
->f_in
); /* Ctr = 1892.16 */
544 MT2063_AddExclZone(pAS_Info
, 1889732000 - pAS_Info
->f_in
, 1891132000 - pAS_Info
->f_in
); /* Ctr = 1890.432 */
545 MT2063_AddExclZone(pAS_Info
, 1888004000 - pAS_Info
->f_in
, 1889404000 - pAS_Info
->f_in
); /* Ctr = 1888.704 */
546 MT2063_AddExclZone(pAS_Info
, 1886276000 - pAS_Info
->f_in
, 1887676000 - pAS_Info
->f_in
); /* Ctr = 1886.976 */
547 MT2063_AddExclZone(pAS_Info
, 1884548000 - pAS_Info
->f_in
, 1885948000 - pAS_Info
->f_in
); /* Ctr = 1885.248 */
548 MT2063_AddExclZone(pAS_Info
, 1882820000 - pAS_Info
->f_in
, 1884220000 - pAS_Info
->f_in
); /* Ctr = 1883.52 */
549 MT2063_AddExclZone(pAS_Info
, 1881092000 - pAS_Info
->f_in
, 1882492000 - pAS_Info
->f_in
); /* Ctr = 1881.792 */
554 * MT_ChooseFirstIF - Choose the best available 1st IF
555 * If f_Desired is not excluded, choose that first.
556 * Otherwise, return the value closest to f_Center that is
559 static u32
MT2063_ChooseFirstIF(struct MT2063_AvoidSpursData_t
*pAS_Info
)
562 * Update "f_Desired" to be the nearest "combinational-multiple" of
564 * The resulting number, F_LO1 must be a multiple of f_LO1_Step.
565 * And F_LO1 is the arithmetic sum of f_in + f_Center.
566 * Neither f_in, nor f_Center must be a multiple of f_LO1_Step.
567 * However, the sum must be.
569 const u32 f_Desired
=
570 pAS_Info
->f_LO1_Step
*
571 ((pAS_Info
->f_if1_Request
+ pAS_Info
->f_in
+
572 pAS_Info
->f_LO1_Step
/ 2) / pAS_Info
->f_LO1_Step
) -
575 (pAS_Info
->f_LO1_Step
>
576 pAS_Info
->f_LO2_Step
) ? pAS_Info
->f_LO1_Step
: pAS_Info
->
581 u32 bDesiredExcluded
= 0;
582 u32 bZeroExcluded
= 0;
585 struct MT2063_ExclZone_t
*pNode
= pAS_Info
->usedZones
;
586 struct MT2063_FIFZone_t zones
[MT2063_MAX_ZONES
];
590 if (pAS_Info
->nZones
== 0)
594 * f_Center needs to be an integer multiple of f_Step away
597 if (pAS_Info
->f_if1_Center
> f_Desired
)
601 ((pAS_Info
->f_if1_Center
- f_Desired
+
602 f_Step
/ 2) / f_Step
);
607 ((f_Desired
- pAS_Info
->f_if1_Center
+
608 f_Step
/ 2) / f_Step
);
611 * Take MT_ExclZones, center around f_Center and change the
612 * resolution to f_Step
614 while (pNode
!= NULL
) {
617 floor((s32
) (pNode
->min_
- f_Center
), (s32
) f_Step
);
621 ceil((s32
) (pNode
->max_
- f_Center
), (s32
) f_Step
);
623 if ((pNode
->min_
< f_Desired
) && (pNode
->max_
> f_Desired
))
624 bDesiredExcluded
= 1;
626 if ((tmpMin
< 0) && (tmpMax
> 0))
629 /* See if this zone overlaps the previous */
630 if ((j
> 0) && (tmpMin
< zones
[j
- 1].max_
))
631 zones
[j
- 1].max_
= tmpMax
;
634 zones
[j
].min_
= tmpMin
;
635 zones
[j
].max_
= tmpMax
;
638 pNode
= pNode
->next_
;
642 * If the desired is okay, return with it
644 if (bDesiredExcluded
== 0)
648 * If the desired is excluded and the center is okay, return with it
650 if (bZeroExcluded
== 0)
653 /* Find the value closest to 0 (f_Center) */
654 bestDiff
= zones
[0].min_
;
655 for (i
= 0; i
< j
; i
++) {
656 if (abs(zones
[i
].min_
) < abs(bestDiff
))
657 bestDiff
= zones
[i
].min_
;
658 if (abs(zones
[i
].max_
) < abs(bestDiff
))
659 bestDiff
= zones
[i
].max_
;
663 return f_Center
- ((u32
) (-bestDiff
) * f_Step
);
665 return f_Center
+ (bestDiff
* f_Step
);
669 * gcd() - Uses Euclid's algorithm
671 * @u, @v: Unsigned values whose GCD is desired.
673 * Returns THE greatest common divisor of u and v, if either value is 0,
674 * the other value is returned as the result.
676 static u32
MT2063_gcd(u32 u
, u32 v
)
690 * IsSpurInBand() - Checks to see if a spur will be present within the IF's
691 * bandwidth. (fIFOut +/- fIFBW, -fIFOut +/- fIFBW)
694 * <--+-+-+-------------------+-------------------+-+-+-->
696 * ^ b=-fIFOut+fIFBW/2 -b=+fIFOut-fIFBW/2 ^
697 * a=-fIFOut-fIFBW/2 -a=+fIFOut+fIFBW/2
699 * Note that some equations are doubled to prevent round-off
700 * problems when calculating fIFBW/2
702 * @pAS_Info: Avoid Spurs information block
703 * @fm: If spur, amount f_IF1 has to move negative
704 * @fp: If spur, amount f_IF1 has to move positive
706 * Returns 1 if an LO spur would be present, otherwise 0.
708 static u32
IsSpurInBand(struct MT2063_AvoidSpursData_t
*pAS_Info
,
712 ** Calculate LO frequency settings.
715 const u32 f_LO1
= pAS_Info
->f_LO1
;
716 const u32 f_LO2
= pAS_Info
->f_LO2
;
717 const u32 d
= pAS_Info
->f_out
+ pAS_Info
->f_out_bw
/ 2;
718 const u32 c
= d
- pAS_Info
->f_out_bw
;
719 const u32 f
= pAS_Info
->f_zif_bw
/ 2;
720 const u32 f_Scale
= (f_LO1
/ (UINT_MAX
/ 2 / pAS_Info
->maxH1
)) + 1;
721 s32 f_nsLO1
, f_nsLO2
;
723 u32 ma
, mb
, mc
, md
, me
, mf
;
724 u32 lo_gcd
, gd_Scale
, gc_Scale
, gf_Scale
, hgds
, hgfs
, hgcs
;
731 ** For each edge (d, c & f), calculate a scale, based on the gcd
732 ** of f_LO1, f_LO2 and the edge value. Use the larger of this
733 ** gcd-based scale factor or f_Scale.
735 lo_gcd
= MT2063_gcd(f_LO1
, f_LO2
);
736 gd_Scale
= max((u32
) MT2063_gcd(lo_gcd
, d
), f_Scale
);
738 gc_Scale
= max((u32
) MT2063_gcd(lo_gcd
, c
), f_Scale
);
740 gf_Scale
= max((u32
) MT2063_gcd(lo_gcd
, f
), f_Scale
);
743 n0
= DIV_ROUND_UP(f_LO2
- d
, f_LO1
- f_LO2
);
745 /* Check out all multiples of LO1 from n0 to m_maxLOSpurHarmonic */
746 for (n
= n0
; n
<= pAS_Info
->maxH1
; ++n
) {
747 md
= (n
* ((f_LO1
+ hgds
) / gd_Scale
) -
748 ((d
+ hgds
) / gd_Scale
)) / ((f_LO2
+ hgds
) / gd_Scale
);
750 /* If # fLO2 harmonics > m_maxLOSpurHarmonic, then no spurs present */
751 if (md
>= pAS_Info
->maxH1
)
754 ma
= (n
* ((f_LO1
+ hgds
) / gd_Scale
) +
755 ((d
+ hgds
) / gd_Scale
)) / ((f_LO2
+ hgds
) / gd_Scale
);
757 /* If no spurs between +/- (f_out + f_IFBW/2), then try next harmonic */
761 mc
= (n
* ((f_LO1
+ hgcs
) / gc_Scale
) -
762 ((c
+ hgcs
) / gc_Scale
)) / ((f_LO2
+ hgcs
) / gc_Scale
);
764 f_nsLO1
= (s32
) (n
* (f_LO1
/ gc_Scale
));
765 f_nsLO2
= (s32
) (mc
* (f_LO2
/ gc_Scale
));
767 (gc_Scale
* (f_nsLO1
- f_nsLO2
)) +
768 n
* (f_LO1
% gc_Scale
) - mc
* (f_LO2
% gc_Scale
);
770 *fp
= ((f_Spur
- (s32
) c
) / (mc
- n
)) + 1;
771 *fm
= (((s32
) d
- f_Spur
) / (mc
- n
)) + 1;
775 /* Location of Zero-IF-spur to be checked */
776 me
= (n
* ((f_LO1
+ hgfs
) / gf_Scale
) +
777 ((f
+ hgfs
) / gf_Scale
)) / ((f_LO2
+ hgfs
) / gf_Scale
);
778 mf
= (n
* ((f_LO1
+ hgfs
) / gf_Scale
) -
779 ((f
+ hgfs
) / gf_Scale
)) / ((f_LO2
+ hgfs
) / gf_Scale
);
781 f_nsLO1
= n
* (f_LO1
/ gf_Scale
);
782 f_nsLO2
= me
* (f_LO2
/ gf_Scale
);
784 (gf_Scale
* (f_nsLO1
- f_nsLO2
)) +
785 n
* (f_LO1
% gf_Scale
) - me
* (f_LO2
% gf_Scale
);
787 *fp
= ((f_Spur
+ (s32
) f
) / (me
- n
)) + 1;
788 *fm
= (((s32
) f
- f_Spur
) / (me
- n
)) + 1;
792 mb
= (n
* ((f_LO1
+ hgcs
) / gc_Scale
) +
793 ((c
+ hgcs
) / gc_Scale
)) / ((f_LO2
+ hgcs
) / gc_Scale
);
795 f_nsLO1
= n
* (f_LO1
/ gc_Scale
);
796 f_nsLO2
= ma
* (f_LO2
/ gc_Scale
);
798 (gc_Scale
* (f_nsLO1
- f_nsLO2
)) +
799 n
* (f_LO1
% gc_Scale
) - ma
* (f_LO2
% gc_Scale
);
801 *fp
= (((s32
) d
+ f_Spur
) / (ma
- n
)) + 1;
802 *fm
= (-(f_Spur
+ (s32
) c
) / (ma
- n
)) + 1;
812 * MT_AvoidSpurs() - Main entry point to avoid spurs.
813 * Checks for existing spurs in present LO1, LO2 freqs
814 * and if present, chooses spur-free LO1, LO2 combination
815 * that tunes the same input/output frequencies.
817 static u32
MT2063_AvoidSpurs(struct MT2063_AvoidSpursData_t
*pAS_Info
)
820 u32 fm
, fp
; /* restricted range on LO's */
821 pAS_Info
->bSpurAvoided
= 0;
822 pAS_Info
->nSpursFound
= 0;
826 if (pAS_Info
->maxH1
== 0)
830 * Avoid LO Generated Spurs
832 * Make sure that have no LO-related spurs within the IF output
835 * If there is an LO spur in this band, start at the current IF1 frequency
836 * and work out until we find a spur-free frequency or run up against the
837 * 1st IF SAW band edge. Use temporary copies of fLO1 and fLO2 so that they
838 * will be unchanged if a spur-free setting is not found.
840 pAS_Info
->bSpurPresent
= IsSpurInBand(pAS_Info
, &fm
, &fp
);
841 if (pAS_Info
->bSpurPresent
) {
842 u32 zfIF1
= pAS_Info
->f_LO1
- pAS_Info
->f_in
; /* current attempt at a 1st IF */
843 u32 zfLO1
= pAS_Info
->f_LO1
; /* current attempt at an LO1 freq */
844 u32 zfLO2
= pAS_Info
->f_LO2
; /* current attempt at an LO2 freq */
849 ** Spur was found, attempt to find a spur-free 1st IF
852 pAS_Info
->nSpursFound
++;
854 /* Raise f_IF1_upper, if needed */
855 MT2063_AddExclZone(pAS_Info
, zfIF1
- fm
, zfIF1
+ fp
);
857 /* Choose next IF1 that is closest to f_IF1_CENTER */
858 new_IF1
= MT2063_ChooseFirstIF(pAS_Info
);
860 if (new_IF1
> zfIF1
) {
861 pAS_Info
->f_LO1
+= (new_IF1
- zfIF1
);
862 pAS_Info
->f_LO2
+= (new_IF1
- zfIF1
);
864 pAS_Info
->f_LO1
-= (zfIF1
- new_IF1
);
865 pAS_Info
->f_LO2
-= (zfIF1
- new_IF1
);
869 if (zfIF1
> pAS_Info
->f_if1_Center
)
870 delta_IF1
= zfIF1
- pAS_Info
->f_if1_Center
;
872 delta_IF1
= pAS_Info
->f_if1_Center
- zfIF1
;
874 pAS_Info
->bSpurPresent
= IsSpurInBand(pAS_Info
, &fm
, &fp
);
876 * Continue while the new 1st IF is still within the 1st IF bandwidth
877 * and there is a spur in the band (again)
879 } while ((2 * delta_IF1
+ pAS_Info
->f_out_bw
<= pAS_Info
->f_if1_bw
) && pAS_Info
->bSpurPresent
);
882 * Use the LO-spur free values found. If the search went all
883 * the way to the 1st IF band edge and always found spurs, just
884 * leave the original choice. It's as "good" as any other.
886 if (pAS_Info
->bSpurPresent
== 1) {
887 status
|= MT2063_SPUR_PRESENT_ERR
;
888 pAS_Info
->f_LO1
= zfLO1
;
889 pAS_Info
->f_LO2
= zfLO2
;
891 pAS_Info
->bSpurAvoided
= 1;
896 nSpursFound
<< MT2063_SPUR_SHIFT
) & MT2063_SPUR_CNT_MASK
);
902 * Constants used by the tuning algorithm
904 #define MT2063_REF_FREQ (16000000UL) /* Reference oscillator Frequency (in Hz) */
905 #define MT2063_IF1_BW (22000000UL) /* The IF1 filter bandwidth (in Hz) */
906 #define MT2063_TUNE_STEP_SIZE (50000UL) /* Tune in steps of 50 kHz */
907 #define MT2063_SPUR_STEP_HZ (250000UL) /* Step size (in Hz) to move IF1 when avoiding spurs */
908 #define MT2063_ZIF_BW (2000000UL) /* Zero-IF spur-free bandwidth (in Hz) */
909 #define MT2063_MAX_HARMONICS_1 (15UL) /* Highest intra-tuner LO Spur Harmonic to be avoided */
910 #define MT2063_MAX_HARMONICS_2 (5UL) /* Highest inter-tuner LO Spur Harmonic to be avoided */
911 #define MT2063_MIN_LO_SEP (1000000UL) /* Minimum inter-tuner LO frequency separation */
912 #define MT2063_LO1_FRACN_AVOID (0UL) /* LO1 FracN numerator avoid region (in Hz) */
913 #define MT2063_LO2_FRACN_AVOID (199999UL) /* LO2 FracN numerator avoid region (in Hz) */
914 #define MT2063_MIN_FIN_FREQ (44000000UL) /* Minimum input frequency (in Hz) */
915 #define MT2063_MAX_FIN_FREQ (1100000000UL) /* Maximum input frequency (in Hz) */
916 #define MT2063_MIN_FOUT_FREQ (36000000UL) /* Minimum output frequency (in Hz) */
917 #define MT2063_MAX_FOUT_FREQ (57000000UL) /* Maximum output frequency (in Hz) */
918 #define MT2063_MIN_DNC_FREQ (1293000000UL) /* Minimum LO2 frequency (in Hz) */
919 #define MT2063_MAX_DNC_FREQ (1614000000UL) /* Maximum LO2 frequency (in Hz) */
920 #define MT2063_MIN_UPC_FREQ (1396000000UL) /* Minimum LO1 frequency (in Hz) */
921 #define MT2063_MAX_UPC_FREQ (2750000000UL) /* Maximum LO1 frequency (in Hz) */
924 * Define the supported Part/Rev codes for the MT2063
926 #define MT2063_B0 (0x9B)
927 #define MT2063_B1 (0x9C)
928 #define MT2063_B2 (0x9D)
929 #define MT2063_B3 (0x9E)
932 * mt2063_lockStatus - Checks to see if LO1 and LO2 are locked
934 * @state: struct mt2063_state pointer
936 * This function returns 0, if no lock, 1 if locked and a value < 1 if error
938 static unsigned int mt2063_lockStatus(struct mt2063_state
*state
)
940 const u32 nMaxWait
= 100; /* wait a maximum of 100 msec */
941 const u32 nPollRate
= 2; /* poll status bits every 2 ms */
942 const u32 nMaxLoops
= nMaxWait
/ nPollRate
;
943 const u8 LO1LK
= 0x80;
950 /* LO2 Lock bit was in a different place for B0 version */
951 if (state
->tuner_id
== MT2063_B0
)
955 status
= mt2063_read(state
, MT2063_REG_LO_STATUS
,
956 &state
->reg
[MT2063_REG_LO_STATUS
], 1);
961 if ((state
->reg
[MT2063_REG_LO_STATUS
] & (LO1LK
| LO2LK
)) ==
963 return TUNER_STATUS_LOCKED
| TUNER_STATUS_STEREO
;
965 msleep(nPollRate
); /* Wait between retries */
966 } while (++nDelays
< nMaxLoops
);
969 * Got no lock or partial lock
975 * Constants for setting receiver modes.
976 * (6 modes defined at this time, enumerated by mt2063_delivery_sys)
977 * (DNC1GC & DNC2GC are the values, which are used, when the specific
978 * DNC Output is selected, the other is always off)
980 * enum mt2063_delivery_sys
981 * -------------+----------------------------------------------
982 * Mode 0 : | MT2063_CABLE_QAM
983 * Mode 1 : | MT2063_CABLE_ANALOG
984 * Mode 2 : | MT2063_OFFAIR_COFDM
985 * Mode 3 : | MT2063_OFFAIR_COFDM_SAWLESS
986 * Mode 4 : | MT2063_OFFAIR_ANALOG
987 * Mode 5 : | MT2063_OFFAIR_8VSB
988 * --------------+----------------------------------------------
990 * |<---------- Mode -------------->|
991 * Reg Field | 0 | 1 | 2 | 3 | 4 | 5 |
992 * ------------+-----+-----+-----+-----+-----+-----+
993 * RFAGCen | OFF | OFF | OFF | OFF | OFF | OFF
994 * LNARin | 0 | 0 | 3 | 3 | 3 | 3
995 * FIFFQen | 1 | 1 | 1 | 1 | 1 | 1
996 * FIFFq | 0 | 0 | 0 | 0 | 0 | 0
997 * DNC1gc | 0 | 0 | 0 | 0 | 0 | 0
998 * DNC2gc | 0 | 0 | 0 | 0 | 0 | 0
999 * GCU Auto | 1 | 1 | 1 | 1 | 1 | 1
1000 * LNA max Atn | 31 | 31 | 31 | 31 | 31 | 31
1001 * LNA Target | 44 | 43 | 43 | 43 | 43 | 43
1002 * ign RF Ovl | 0 | 0 | 0 | 0 | 0 | 0
1003 * RF max Atn | 31 | 31 | 31 | 31 | 31 | 31
1004 * PD1 Target | 36 | 36 | 38 | 38 | 36 | 38
1005 * ign FIF Ovl | 0 | 0 | 0 | 0 | 0 | 0
1006 * FIF max Atn | 5 | 5 | 5 | 5 | 5 | 5
1007 * PD2 Target | 40 | 33 | 42 | 42 | 33 | 42
1010 enum mt2063_delivery_sys
{
1011 MT2063_CABLE_QAM
= 0,
1012 MT2063_CABLE_ANALOG
,
1013 MT2063_OFFAIR_COFDM
,
1014 MT2063_OFFAIR_COFDM_SAWLESS
,
1015 MT2063_OFFAIR_ANALOG
,
1017 MT2063_NUM_RCVR_MODES
1020 static const char *mt2063_mode_name
[] = {
1021 [MT2063_CABLE_QAM
] = "digital cable",
1022 [MT2063_CABLE_ANALOG
] = "analog cable",
1023 [MT2063_OFFAIR_COFDM
] = "digital offair",
1024 [MT2063_OFFAIR_COFDM_SAWLESS
] = "digital offair without SAW",
1025 [MT2063_OFFAIR_ANALOG
] = "analog offair",
1026 [MT2063_OFFAIR_8VSB
] = "analog offair 8vsb",
1029 static const u8 RFAGCEN
[] = { 0, 0, 0, 0, 0, 0 };
1030 static const u8 LNARIN
[] = { 0, 0, 3, 3, 3, 3 };
1031 static const u8 FIFFQEN
[] = { 1, 1, 1, 1, 1, 1 };
1032 static const u8 FIFFQ
[] = { 0, 0, 0, 0, 0, 0 };
1033 static const u8 DNC1GC
[] = { 0, 0, 0, 0, 0, 0 };
1034 static const u8 DNC2GC
[] = { 0, 0, 0, 0, 0, 0 };
1035 static const u8 ACLNAMAX
[] = { 31, 31, 31, 31, 31, 31 };
1036 static const u8 LNATGT
[] = { 44, 43, 43, 43, 43, 43 };
1037 static const u8 RFOVDIS
[] = { 0, 0, 0, 0, 0, 0 };
1038 static const u8 ACRFMAX
[] = { 31, 31, 31, 31, 31, 31 };
1039 static const u8 PD1TGT
[] = { 36, 36, 38, 38, 36, 38 };
1040 static const u8 FIFOVDIS
[] = { 0, 0, 0, 0, 0, 0 };
1041 static const u8 ACFIFMAX
[] = { 29, 29, 29, 29, 29, 29 };
1042 static const u8 PD2TGT
[] = { 40, 33, 38, 42, 30, 38 };
1045 * mt2063_set_dnc_output_enable()
1047 static u32
mt2063_get_dnc_output_enable(struct mt2063_state
*state
,
1048 enum MT2063_DNC_Output_Enable
*pValue
)
1052 if ((state
->reg
[MT2063_REG_DNC_GAIN
] & 0x03) == 0x03) { /* if DNC1 is off */
1053 if ((state
->reg
[MT2063_REG_VGA_GAIN
] & 0x03) == 0x03) /* if DNC2 is off */
1054 *pValue
= MT2063_DNC_NONE
;
1056 *pValue
= MT2063_DNC_2
;
1057 } else { /* DNC1 is on */
1058 if ((state
->reg
[MT2063_REG_VGA_GAIN
] & 0x03) == 0x03) /* if DNC2 is off */
1059 *pValue
= MT2063_DNC_1
;
1061 *pValue
= MT2063_DNC_BOTH
;
1067 * mt2063_set_dnc_output_enable()
1069 static u32
mt2063_set_dnc_output_enable(struct mt2063_state
*state
,
1070 enum MT2063_DNC_Output_Enable nValue
)
1072 u32 status
= 0; /* Status to be returned */
1077 /* selects, which DNC output is used */
1079 case MT2063_DNC_NONE
:
1080 val
= (state
->reg
[MT2063_REG_DNC_GAIN
] & 0xFC) | 0x03; /* Set DNC1GC=3 */
1081 if (state
->reg
[MT2063_REG_DNC_GAIN
] !=
1084 mt2063_setreg(state
,
1085 MT2063_REG_DNC_GAIN
,
1088 val
= (state
->reg
[MT2063_REG_VGA_GAIN
] & 0xFC) | 0x03; /* Set DNC2GC=3 */
1089 if (state
->reg
[MT2063_REG_VGA_GAIN
] !=
1092 mt2063_setreg(state
,
1093 MT2063_REG_VGA_GAIN
,
1096 val
= (state
->reg
[MT2063_REG_RSVD_20
] & ~0x40); /* Set PD2MUX=0 */
1097 if (state
->reg
[MT2063_REG_RSVD_20
] !=
1100 mt2063_setreg(state
,
1106 val
= (state
->reg
[MT2063_REG_DNC_GAIN
] & 0xFC) | (DNC1GC
[state
->rcvr_mode
] & 0x03); /* Set DNC1GC=x */
1107 if (state
->reg
[MT2063_REG_DNC_GAIN
] !=
1110 mt2063_setreg(state
,
1111 MT2063_REG_DNC_GAIN
,
1114 val
= (state
->reg
[MT2063_REG_VGA_GAIN
] & 0xFC) | 0x03; /* Set DNC2GC=3 */
1115 if (state
->reg
[MT2063_REG_VGA_GAIN
] !=
1118 mt2063_setreg(state
,
1119 MT2063_REG_VGA_GAIN
,
1122 val
= (state
->reg
[MT2063_REG_RSVD_20
] & ~0x40); /* Set PD2MUX=0 */
1123 if (state
->reg
[MT2063_REG_RSVD_20
] !=
1126 mt2063_setreg(state
,
1132 val
= (state
->reg
[MT2063_REG_DNC_GAIN
] & 0xFC) | 0x03; /* Set DNC1GC=3 */
1133 if (state
->reg
[MT2063_REG_DNC_GAIN
] !=
1136 mt2063_setreg(state
,
1137 MT2063_REG_DNC_GAIN
,
1140 val
= (state
->reg
[MT2063_REG_VGA_GAIN
] & 0xFC) | (DNC2GC
[state
->rcvr_mode
] & 0x03); /* Set DNC2GC=x */
1141 if (state
->reg
[MT2063_REG_VGA_GAIN
] !=
1144 mt2063_setreg(state
,
1145 MT2063_REG_VGA_GAIN
,
1148 val
= (state
->reg
[MT2063_REG_RSVD_20
] | 0x40); /* Set PD2MUX=1 */
1149 if (state
->reg
[MT2063_REG_RSVD_20
] !=
1152 mt2063_setreg(state
,
1157 case MT2063_DNC_BOTH
:
1158 val
= (state
->reg
[MT2063_REG_DNC_GAIN
] & 0xFC) | (DNC1GC
[state
->rcvr_mode
] & 0x03); /* Set DNC1GC=x */
1159 if (state
->reg
[MT2063_REG_DNC_GAIN
] !=
1162 mt2063_setreg(state
,
1163 MT2063_REG_DNC_GAIN
,
1166 val
= (state
->reg
[MT2063_REG_VGA_GAIN
] & 0xFC) | (DNC2GC
[state
->rcvr_mode
] & 0x03); /* Set DNC2GC=x */
1167 if (state
->reg
[MT2063_REG_VGA_GAIN
] !=
1170 mt2063_setreg(state
,
1171 MT2063_REG_VGA_GAIN
,
1174 val
= (state
->reg
[MT2063_REG_RSVD_20
] | 0x40); /* Set PD2MUX=1 */
1175 if (state
->reg
[MT2063_REG_RSVD_20
] !=
1178 mt2063_setreg(state
,
1191 * MT2063_SetReceiverMode() - Set the MT2063 receiver mode, according with
1192 * the selected enum mt2063_delivery_sys type.
1194 * (DNC1GC & DNC2GC are the values, which are used, when the specific
1195 * DNC Output is selected, the other is always off)
1197 * @state: ptr to mt2063_state structure
1198 * @Mode: desired reciever delivery system
1200 * Note: Register cache must be valid for it to work
1203 static u32
MT2063_SetReceiverMode(struct mt2063_state
*state
,
1204 enum mt2063_delivery_sys Mode
)
1206 u32 status
= 0; /* Status to be returned */
1212 if (Mode
>= MT2063_NUM_RCVR_MODES
)
1219 reg
[MT2063_REG_PD1_TGT
] & (u8
) ~0x40) | (RFAGCEN
[Mode
]
1222 if (state
->reg
[MT2063_REG_PD1_TGT
] != val
)
1223 status
|= mt2063_setreg(state
, MT2063_REG_PD1_TGT
, val
);
1228 u8 val
= (state
->reg
[MT2063_REG_CTRL_2C
] & (u8
) ~0x03) |
1229 (LNARIN
[Mode
] & 0x03);
1230 if (state
->reg
[MT2063_REG_CTRL_2C
] != val
)
1231 status
|= mt2063_setreg(state
, MT2063_REG_CTRL_2C
, val
);
1234 /* FIFFQEN and FIFFQ */
1238 reg
[MT2063_REG_FIFF_CTRL2
] & (u8
) ~0xF0) |
1239 (FIFFQEN
[Mode
] << 7) | (FIFFQ
[Mode
] << 4);
1240 if (state
->reg
[MT2063_REG_FIFF_CTRL2
] != val
) {
1242 mt2063_setreg(state
, MT2063_REG_FIFF_CTRL2
, val
);
1243 /* trigger FIFF calibration, needed after changing FIFFQ */
1245 (state
->reg
[MT2063_REG_FIFF_CTRL
] | (u8
) 0x01);
1247 mt2063_setreg(state
, MT2063_REG_FIFF_CTRL
, val
);
1250 reg
[MT2063_REG_FIFF_CTRL
] & (u8
) ~0x01);
1252 mt2063_setreg(state
, MT2063_REG_FIFF_CTRL
, val
);
1256 /* DNC1GC & DNC2GC */
1257 status
|= mt2063_get_dnc_output_enable(state
, &longval
);
1258 status
|= mt2063_set_dnc_output_enable(state
, longval
);
1262 u8 val
= (state
->reg
[MT2063_REG_LNA_OV
] & (u8
) ~0x1F) |
1263 (ACLNAMAX
[Mode
] & 0x1F);
1264 if (state
->reg
[MT2063_REG_LNA_OV
] != val
)
1265 status
|= mt2063_setreg(state
, MT2063_REG_LNA_OV
, val
);
1270 u8 val
= (state
->reg
[MT2063_REG_LNA_TGT
] & (u8
) ~0x3F) |
1271 (LNATGT
[Mode
] & 0x3F);
1272 if (state
->reg
[MT2063_REG_LNA_TGT
] != val
)
1273 status
|= mt2063_setreg(state
, MT2063_REG_LNA_TGT
, val
);
1278 u8 val
= (state
->reg
[MT2063_REG_RF_OV
] & (u8
) ~0x1F) |
1279 (ACRFMAX
[Mode
] & 0x1F);
1280 if (state
->reg
[MT2063_REG_RF_OV
] != val
)
1281 status
|= mt2063_setreg(state
, MT2063_REG_RF_OV
, val
);
1286 u8 val
= (state
->reg
[MT2063_REG_PD1_TGT
] & (u8
) ~0x3F) |
1287 (PD1TGT
[Mode
] & 0x3F);
1288 if (state
->reg
[MT2063_REG_PD1_TGT
] != val
)
1289 status
|= mt2063_setreg(state
, MT2063_REG_PD1_TGT
, val
);
1294 u8 val
= ACFIFMAX
[Mode
];
1295 if (state
->reg
[MT2063_REG_PART_REV
] != MT2063_B3
&& val
> 5)
1297 val
= (state
->reg
[MT2063_REG_FIF_OV
] & (u8
) ~0x1F) |
1299 if (state
->reg
[MT2063_REG_FIF_OV
] != val
)
1300 status
|= mt2063_setreg(state
, MT2063_REG_FIF_OV
, val
);
1305 u8 val
= (state
->reg
[MT2063_REG_PD2_TGT
] & (u8
) ~0x3F) |
1306 (PD2TGT
[Mode
] & 0x3F);
1307 if (state
->reg
[MT2063_REG_PD2_TGT
] != val
)
1308 status
|= mt2063_setreg(state
, MT2063_REG_PD2_TGT
, val
);
1311 /* Ignore ATN Overload */
1313 val
= (state
->reg
[MT2063_REG_LNA_TGT
] & (u8
) ~0x80) |
1314 (RFOVDIS
[Mode
] ? 0x80 : 0x00);
1315 if (state
->reg
[MT2063_REG_LNA_TGT
] != val
)
1316 status
|= mt2063_setreg(state
, MT2063_REG_LNA_TGT
, val
);
1319 /* Ignore FIF Overload */
1321 val
= (state
->reg
[MT2063_REG_PD1_TGT
] & (u8
) ~0x80) |
1322 (FIFOVDIS
[Mode
] ? 0x80 : 0x00);
1323 if (state
->reg
[MT2063_REG_PD1_TGT
] != val
)
1324 status
|= mt2063_setreg(state
, MT2063_REG_PD1_TGT
, val
);
1328 state
->rcvr_mode
= Mode
;
1329 dprintk(1, "mt2063 mode changed to %s\n",
1330 mt2063_mode_name
[state
->rcvr_mode
]);
1337 * MT2063_ClearPowerMaskBits () - Clears the power-down mask bits for various
1338 * sections of the MT2063
1340 * @Bits: Mask bits to be cleared.
1342 * See definition of MT2063_Mask_Bits type for description
1343 * of each of the power bits.
1345 static u32
MT2063_ClearPowerMaskBits(struct mt2063_state
*state
,
1346 enum MT2063_Mask_Bits Bits
)
1351 Bits
= (enum MT2063_Mask_Bits
)(Bits
& MT2063_ALL_SD
); /* Only valid bits for this tuner */
1352 if ((Bits
& 0xFF00) != 0) {
1353 state
->reg
[MT2063_REG_PWR_2
] &= ~(u8
) (Bits
>> 8);
1357 &state
->reg
[MT2063_REG_PWR_2
], 1);
1359 if ((Bits
& 0xFF) != 0) {
1360 state
->reg
[MT2063_REG_PWR_1
] &= ~(u8
) (Bits
& 0xFF);
1364 &state
->reg
[MT2063_REG_PWR_1
], 1);
1371 * MT2063_SoftwareShutdown() - Enables or disables software shutdown function.
1372 * When Shutdown is 1, any section whose power
1373 * mask is set will be shutdown.
1375 static u32
MT2063_SoftwareShutdown(struct mt2063_state
*state
, u8 Shutdown
)
1381 state
->reg
[MT2063_REG_PWR_1
] |= 0x04;
1383 state
->reg
[MT2063_REG_PWR_1
] &= ~0x04;
1385 status
= mt2063_write(state
,
1387 &state
->reg
[MT2063_REG_PWR_1
], 1);
1389 if (Shutdown
!= 1) {
1390 state
->reg
[MT2063_REG_BYP_CTRL
] =
1391 (state
->reg
[MT2063_REG_BYP_CTRL
] & 0x9F) | 0x40;
1394 MT2063_REG_BYP_CTRL
,
1395 &state
->reg
[MT2063_REG_BYP_CTRL
],
1397 state
->reg
[MT2063_REG_BYP_CTRL
] =
1398 (state
->reg
[MT2063_REG_BYP_CTRL
] & 0x9F);
1401 MT2063_REG_BYP_CTRL
,
1402 &state
->reg
[MT2063_REG_BYP_CTRL
],
1409 static u32
MT2063_Round_fLO(u32 f_LO
, u32 f_LO_Step
, u32 f_ref
)
1411 return f_ref
* (f_LO
/ f_ref
)
1412 + f_LO_Step
* (((f_LO
% f_ref
) + (f_LO_Step
/ 2)) / f_LO_Step
);
1416 * fLO_FractionalTerm() - Calculates the portion contributed by FracN / denom.
1417 * This function preserves maximum precision without
1418 * risk of overflow. It accurately calculates
1419 * f_ref * num / denom to within 1 HZ with fixed math.
1421 * @num : Fractional portion of the multiplier
1422 * @denom: denominator portion of the ratio
1423 * @f_Ref: SRO frequency.
1425 * This calculation handles f_ref as two separate 14-bit fields.
1426 * Therefore, a maximum value of 2^28-1 may safely be used for f_ref.
1427 * This is the genesis of the magic number "14" and the magic mask value of
1430 * This routine successfully handles denom values up to and including 2^18.
1431 * Returns: f_ref * num / denom
1433 static u32
MT2063_fLO_FractionalTerm(u32 f_ref
, u32 num
, u32 denom
)
1435 u32 t1
= (f_ref
>> 14) * num
;
1436 u32 term1
= t1
/ denom
;
1437 u32 loss
= t1
% denom
;
1439 (((f_ref
& 0x00003FFF) * num
+ (loss
<< 14)) + (denom
/ 2)) / denom
;
1440 return (term1
<< 14) + term2
;
1444 * CalcLO1Mult()- Calculates Integer divider value and the numerator
1445 * value for a FracN PLL.
1447 * This function assumes that the f_LO and f_Ref are
1448 * evenly divisible by f_LO_Step.
1450 * @Div: OUTPUT: Whole number portion of the multiplier
1451 * @FracN: OUTPUT: Fractional portion of the multiplier
1452 * @f_LO: desired LO frequency.
1453 * @f_LO_Step: Minimum step size for the LO (in Hz).
1454 * @f_Ref: SRO frequency.
1455 * @f_Avoid: Range of PLL frequencies to avoid near integer multiples
1458 * Returns: Recalculated LO frequency.
1460 static u32
MT2063_CalcLO1Mult(u32
*Div
,
1463 u32 f_LO_Step
, u32 f_Ref
)
1465 /* Calculate the whole number portion of the divider */
1466 *Div
= f_LO
/ f_Ref
;
1468 /* Calculate the numerator value (round to nearest f_LO_Step) */
1470 (64 * (((f_LO
% f_Ref
) + (f_LO_Step
/ 2)) / f_LO_Step
) +
1471 (f_Ref
/ f_LO_Step
/ 2)) / (f_Ref
/ f_LO_Step
);
1473 return (f_Ref
* (*Div
)) + MT2063_fLO_FractionalTerm(f_Ref
, *FracN
, 64);
1477 * CalcLO2Mult() - Calculates Integer divider value and the numerator
1478 * value for a FracN PLL.
1480 * This function assumes that the f_LO and f_Ref are
1481 * evenly divisible by f_LO_Step.
1483 * @Div: OUTPUT: Whole number portion of the multiplier
1484 * @FracN: OUTPUT: Fractional portion of the multiplier
1485 * @f_LO: desired LO frequency.
1486 * @f_LO_Step: Minimum step size for the LO (in Hz).
1487 * @f_Ref: SRO frequency.
1488 * @f_Avoid: Range of PLL frequencies to avoid near
1489 * integer multiples of f_Ref (in Hz).
1491 * Returns: Recalculated LO frequency.
1493 static u32
MT2063_CalcLO2Mult(u32
*Div
,
1496 u32 f_LO_Step
, u32 f_Ref
)
1498 /* Calculate the whole number portion of the divider */
1499 *Div
= f_LO
/ f_Ref
;
1501 /* Calculate the numerator value (round to nearest f_LO_Step) */
1503 (8191 * (((f_LO
% f_Ref
) + (f_LO_Step
/ 2)) / f_LO_Step
) +
1504 (f_Ref
/ f_LO_Step
/ 2)) / (f_Ref
/ f_LO_Step
);
1506 return (f_Ref
* (*Div
)) + MT2063_fLO_FractionalTerm(f_Ref
, *FracN
,
1511 * FindClearTuneFilter() - Calculate the corrrect ClearTune filter to be
1512 * used for a given input frequency.
1514 * @state: ptr to tuner data structure
1515 * @f_in: RF input center frequency (in Hz).
1517 * Returns: ClearTune filter number (0-31)
1519 static u32
FindClearTuneFilter(struct mt2063_state
*state
, u32 f_in
)
1522 u32 idx
; /* index loop */
1525 ** Find RF Band setting
1527 RFBand
= 31; /* def when f_in > all */
1528 for (idx
= 0; idx
< 31; ++idx
) {
1529 if (state
->CTFiltMax
[idx
] >= f_in
) {
1538 * MT2063_Tune() - Change the tuner's tuned frequency to RFin.
1540 static u32
MT2063_Tune(struct mt2063_state
*state
, u32 f_in
)
1541 { /* RF input center frequency */
1544 u32 LO1
; /* 1st LO register value */
1545 u32 Num1
; /* Numerator for LO1 reg. value */
1546 u32 f_IF1
; /* 1st IF requested */
1547 u32 LO2
; /* 2nd LO register value */
1548 u32 Num2
; /* Numerator for LO2 reg. value */
1549 u32 ofLO1
, ofLO2
; /* last time's LO frequencies */
1550 u8 fiffc
= 0x80; /* FIFF center freq from tuner */
1551 u32 fiffof
; /* Offset from FIFF center freq */
1552 const u8 LO1LK
= 0x80; /* Mask for LO1 Lock bit */
1553 u8 LO2LK
= 0x08; /* Mask for LO2 Lock bit */
1558 /* Check the input and output frequency ranges */
1559 if ((f_in
< MT2063_MIN_FIN_FREQ
) || (f_in
> MT2063_MAX_FIN_FREQ
))
1562 if ((state
->AS_Data
.f_out
< MT2063_MIN_FOUT_FREQ
)
1563 || (state
->AS_Data
.f_out
> MT2063_MAX_FOUT_FREQ
))
1567 * Save original LO1 and LO2 register values
1569 ofLO1
= state
->AS_Data
.f_LO1
;
1570 ofLO2
= state
->AS_Data
.f_LO2
;
1573 * Find and set RF Band setting
1575 if (state
->ctfilt_sw
== 1) {
1576 val
= (state
->reg
[MT2063_REG_CTUNE_CTRL
] | 0x08);
1577 if (state
->reg
[MT2063_REG_CTUNE_CTRL
] != val
) {
1579 mt2063_setreg(state
, MT2063_REG_CTUNE_CTRL
, val
);
1581 val
= state
->reg
[MT2063_REG_CTUNE_OV
];
1582 RFBand
= FindClearTuneFilter(state
, f_in
);
1583 state
->reg
[MT2063_REG_CTUNE_OV
] =
1584 (u8
) ((state
->reg
[MT2063_REG_CTUNE_OV
] & ~0x1F)
1586 if (state
->reg
[MT2063_REG_CTUNE_OV
] != val
) {
1588 mt2063_setreg(state
, MT2063_REG_CTUNE_OV
, val
);
1593 * Read the FIFF Center Frequency from the tuner
1599 &state
->reg
[MT2063_REG_FIFFC
], 1);
1600 fiffc
= state
->reg
[MT2063_REG_FIFFC
];
1603 * Assign in the requested values
1605 state
->AS_Data
.f_in
= f_in
;
1606 /* Request a 1st IF such that LO1 is on a step size */
1607 state
->AS_Data
.f_if1_Request
=
1608 MT2063_Round_fLO(state
->AS_Data
.f_if1_Request
+ f_in
,
1609 state
->AS_Data
.f_LO1_Step
,
1610 state
->AS_Data
.f_ref
) - f_in
;
1613 * Calculate frequency settings. f_IF1_FREQ + f_in is the
1614 * desired LO1 frequency
1616 MT2063_ResetExclZones(&state
->AS_Data
);
1618 f_IF1
= MT2063_ChooseFirstIF(&state
->AS_Data
);
1620 state
->AS_Data
.f_LO1
=
1621 MT2063_Round_fLO(f_IF1
+ f_in
, state
->AS_Data
.f_LO1_Step
,
1622 state
->AS_Data
.f_ref
);
1624 state
->AS_Data
.f_LO2
=
1625 MT2063_Round_fLO(state
->AS_Data
.f_LO1
- state
->AS_Data
.f_out
- f_in
,
1626 state
->AS_Data
.f_LO2_Step
, state
->AS_Data
.f_ref
);
1629 * Check for any LO spurs in the output bandwidth and adjust
1630 * the LO settings to avoid them if needed
1632 status
|= MT2063_AvoidSpurs(&state
->AS_Data
);
1634 * MT_AvoidSpurs spurs may have changed the LO1 & LO2 values.
1635 * Recalculate the LO frequencies and the values to be placed
1636 * in the tuning registers.
1638 state
->AS_Data
.f_LO1
=
1639 MT2063_CalcLO1Mult(&LO1
, &Num1
, state
->AS_Data
.f_LO1
,
1640 state
->AS_Data
.f_LO1_Step
, state
->AS_Data
.f_ref
);
1641 state
->AS_Data
.f_LO2
=
1642 MT2063_Round_fLO(state
->AS_Data
.f_LO1
- state
->AS_Data
.f_out
- f_in
,
1643 state
->AS_Data
.f_LO2_Step
, state
->AS_Data
.f_ref
);
1644 state
->AS_Data
.f_LO2
=
1645 MT2063_CalcLO2Mult(&LO2
, &Num2
, state
->AS_Data
.f_LO2
,
1646 state
->AS_Data
.f_LO2_Step
, state
->AS_Data
.f_ref
);
1649 * Check the upconverter and downconverter frequency ranges
1651 if ((state
->AS_Data
.f_LO1
< MT2063_MIN_UPC_FREQ
)
1652 || (state
->AS_Data
.f_LO1
> MT2063_MAX_UPC_FREQ
))
1653 status
|= MT2063_UPC_RANGE
;
1654 if ((state
->AS_Data
.f_LO2
< MT2063_MIN_DNC_FREQ
)
1655 || (state
->AS_Data
.f_LO2
> MT2063_MAX_DNC_FREQ
))
1656 status
|= MT2063_DNC_RANGE
;
1657 /* LO2 Lock bit was in a different place for B0 version */
1658 if (state
->tuner_id
== MT2063_B0
)
1662 * If we have the same LO frequencies and we're already locked,
1663 * then skip re-programming the LO registers.
1665 if ((ofLO1
!= state
->AS_Data
.f_LO1
)
1666 || (ofLO2
!= state
->AS_Data
.f_LO2
)
1667 || ((state
->reg
[MT2063_REG_LO_STATUS
] & (LO1LK
| LO2LK
)) !=
1670 * Calculate the FIFFOF register value
1673 * FIFFOF = ------------ - 8 * FIFFC - 4992
1677 (state
->AS_Data
.f_LO1
-
1678 f_in
) / (state
->AS_Data
.f_ref
/ 64) - 8 * (u32
) fiffc
-
1684 * Place all of the calculated values into the local tuner
1688 state
->reg
[MT2063_REG_LO1CQ_1
] = (u8
) (LO1
& 0xFF); /* DIV1q */
1689 state
->reg
[MT2063_REG_LO1CQ_2
] = (u8
) (Num1
& 0x3F); /* NUM1q */
1690 state
->reg
[MT2063_REG_LO2CQ_1
] = (u8
) (((LO2
& 0x7F) << 1) /* DIV2q */
1691 |(Num2
>> 12)); /* NUM2q (hi) */
1692 state
->reg
[MT2063_REG_LO2CQ_2
] = (u8
) ((Num2
& 0x0FF0) >> 4); /* NUM2q (mid) */
1693 state
->reg
[MT2063_REG_LO2CQ_3
] = (u8
) (0xE0 | (Num2
& 0x000F)); /* NUM2q (lo) */
1696 * Now write out the computed register values
1697 * IMPORTANT: There is a required order for writing
1698 * (0x05 must follow all the others).
1700 status
|= mt2063_write(state
, MT2063_REG_LO1CQ_1
, &state
->reg
[MT2063_REG_LO1CQ_1
], 5); /* 0x01 - 0x05 */
1701 if (state
->tuner_id
== MT2063_B0
) {
1702 /* Re-write the one-shot bits to trigger the tune operation */
1703 status
|= mt2063_write(state
, MT2063_REG_LO2CQ_3
, &state
->reg
[MT2063_REG_LO2CQ_3
], 1); /* 0x05 */
1705 /* Write out the FIFF offset only if it's changing */
1706 if (state
->reg
[MT2063_REG_FIFF_OFFSET
] !=
1708 state
->reg
[MT2063_REG_FIFF_OFFSET
] =
1712 MT2063_REG_FIFF_OFFSET
,
1714 reg
[MT2063_REG_FIFF_OFFSET
],
1720 * Check for LO's locking
1726 status
= mt2063_lockStatus(state
);
1730 return -EINVAL
; /* Couldn't lock */
1733 * If we locked OK, assign calculated data to mt2063_state structure
1735 state
->f_IF1_actual
= state
->AS_Data
.f_LO1
- f_in
;
1741 static const u8 MT2063B0_defaults
[] = {
1755 0x2C, 0x27, /* bit at 0x20 is cleared below */
1757 0x2C, 0x07, /* bit at 0x20 is cleared here */
1760 0x28, 0xE1, /* Set the FIFCrst bit here */
1761 0x28, 0xE0, /* Clear the FIFCrst bit here */
1765 /* writing 0x05 0xf0 sw-resets all registers, so we write only needed changes */
1766 static const u8 MT2063B1_defaults
[] = {
1769 0x11, 0x10, /* New Enable AFCsd */
1778 0x22, 0x21, /* New - ver 1.03 */
1779 0x23, 0x3C, /* New - ver 1.10 */
1780 0x24, 0x20, /* New - ver 1.03 */
1781 0x2C, 0x24, /* bit at 0x20 is cleared below */
1782 0x2D, 0x87, /* FIFFQ=0 */
1784 0x30, 0x0C, /* New - ver 1.11 */
1785 0x31, 0x1B, /* New - ver 1.11 */
1786 0x2C, 0x04, /* bit at 0x20 is cleared here */
1787 0x28, 0xE1, /* Set the FIFCrst bit here */
1788 0x28, 0xE0, /* Clear the FIFCrst bit here */
1792 /* writing 0x05 0xf0 sw-resets all registers, so we write only needed changes */
1793 static const u8 MT2063B3_defaults
[] = {
1797 0x2C, 0x24, /* bit at 0x20 is cleared below */
1798 0x2C, 0x04, /* bit at 0x20 is cleared here */
1799 0x28, 0xE1, /* Set the FIFCrst bit here */
1800 0x28, 0xE0, /* Clear the FIFCrst bit here */
1804 static int mt2063_init(struct dvb_frontend
*fe
)
1807 struct mt2063_state
*state
= fe
->tuner_priv
;
1808 u8 all_resets
= 0xF0; /* reset/load bits */
1809 const u8
*def
= NULL
;
1818 state
->rcvr_mode
= MT2063_CABLE_QAM
;
1820 /* Read the Part/Rev code from the tuner */
1821 status
= mt2063_read(state
, MT2063_REG_PART_REV
,
1822 &state
->reg
[MT2063_REG_PART_REV
], 1);
1824 printk(KERN_ERR
"Can't read mt2063 part ID\n");
1828 /* Check the part/rev code */
1829 switch (state
->reg
[MT2063_REG_PART_REV
]) {
1843 printk(KERN_ERR
"mt2063: Unknown mt2063 device ID (0x%02x)\n",
1844 state
->reg
[MT2063_REG_PART_REV
]);
1845 return -ENODEV
; /* Wrong tuner Part/Rev code */
1848 /* Check the 2nd byte of the Part/Rev code from the tuner */
1849 status
= mt2063_read(state
, MT2063_REG_RSVD_3B
,
1850 &state
->reg
[MT2063_REG_RSVD_3B
], 1);
1852 /* b7 != 0 ==> NOT MT2063 */
1853 if (status
< 0 || ((state
->reg
[MT2063_REG_RSVD_3B
] & 0x80) != 0x00)) {
1854 printk(KERN_ERR
"mt2063: Unknown part ID (0x%02x%02x)\n",
1855 state
->reg
[MT2063_REG_PART_REV
],
1856 state
->reg
[MT2063_REG_RSVD_3B
]);
1857 return -ENODEV
; /* Wrong tuner Part/Rev code */
1860 printk(KERN_INFO
"mt2063: detected a mt2063 %s\n", step
);
1862 /* Reset the tuner */
1863 status
= mt2063_write(state
, MT2063_REG_LO2CQ_3
, &all_resets
, 1);
1867 /* change all of the default values that vary from the HW reset values */
1868 /* def = (state->reg[PART_REV] == MT2063_B0) ? MT2063B0_defaults : MT2063B1_defaults; */
1869 switch (state
->reg
[MT2063_REG_PART_REV
]) {
1871 def
= MT2063B3_defaults
;
1875 def
= MT2063B1_defaults
;
1879 def
= MT2063B0_defaults
;
1887 while (status
>= 0 && *def
) {
1890 status
= mt2063_write(state
, reg
, &val
, 1);
1895 /* Wait for FIFF location to complete. */
1898 while (status
>= 0 && (FCRUN
!= 0) && (maxReads
-- > 0)) {
1900 status
= mt2063_read(state
,
1901 MT2063_REG_XO_STATUS
,
1903 reg
[MT2063_REG_XO_STATUS
], 1);
1904 FCRUN
= (state
->reg
[MT2063_REG_XO_STATUS
] & 0x40) >> 6;
1907 if (FCRUN
!= 0 || status
< 0)
1910 status
= mt2063_read(state
,
1912 &state
->reg
[MT2063_REG_FIFFC
], 1);
1916 /* Read back all the registers from the tuner */
1917 status
= mt2063_read(state
,
1918 MT2063_REG_PART_REV
,
1919 state
->reg
, MT2063_REG_END_REGS
);
1923 /* Initialize the tuner state. */
1924 state
->tuner_id
= state
->reg
[MT2063_REG_PART_REV
];
1925 state
->AS_Data
.f_ref
= MT2063_REF_FREQ
;
1926 state
->AS_Data
.f_if1_Center
= (state
->AS_Data
.f_ref
/ 8) *
1927 ((u32
) state
->reg
[MT2063_REG_FIFFC
] + 640);
1928 state
->AS_Data
.f_if1_bw
= MT2063_IF1_BW
;
1929 state
->AS_Data
.f_out
= 43750000UL;
1930 state
->AS_Data
.f_out_bw
= 6750000UL;
1931 state
->AS_Data
.f_zif_bw
= MT2063_ZIF_BW
;
1932 state
->AS_Data
.f_LO1_Step
= state
->AS_Data
.f_ref
/ 64;
1933 state
->AS_Data
.f_LO2_Step
= MT2063_TUNE_STEP_SIZE
;
1934 state
->AS_Data
.maxH1
= MT2063_MAX_HARMONICS_1
;
1935 state
->AS_Data
.maxH2
= MT2063_MAX_HARMONICS_2
;
1936 state
->AS_Data
.f_min_LO_Separation
= MT2063_MIN_LO_SEP
;
1937 state
->AS_Data
.f_if1_Request
= state
->AS_Data
.f_if1_Center
;
1938 state
->AS_Data
.f_LO1
= 2181000000UL;
1939 state
->AS_Data
.f_LO2
= 1486249786UL;
1940 state
->f_IF1_actual
= state
->AS_Data
.f_if1_Center
;
1941 state
->AS_Data
.f_in
= state
->AS_Data
.f_LO1
- state
->f_IF1_actual
;
1942 state
->AS_Data
.f_LO1_FracN_Avoid
= MT2063_LO1_FRACN_AVOID
;
1943 state
->AS_Data
.f_LO2_FracN_Avoid
= MT2063_LO2_FRACN_AVOID
;
1944 state
->num_regs
= MT2063_REG_END_REGS
;
1945 state
->AS_Data
.avoidDECT
= MT2063_AVOID_BOTH
;
1946 state
->ctfilt_sw
= 0;
1948 state
->CTFiltMax
[0] = 69230000;
1949 state
->CTFiltMax
[1] = 105770000;
1950 state
->CTFiltMax
[2] = 140350000;
1951 state
->CTFiltMax
[3] = 177110000;
1952 state
->CTFiltMax
[4] = 212860000;
1953 state
->CTFiltMax
[5] = 241130000;
1954 state
->CTFiltMax
[6] = 274370000;
1955 state
->CTFiltMax
[7] = 309820000;
1956 state
->CTFiltMax
[8] = 342450000;
1957 state
->CTFiltMax
[9] = 378870000;
1958 state
->CTFiltMax
[10] = 416210000;
1959 state
->CTFiltMax
[11] = 456500000;
1960 state
->CTFiltMax
[12] = 495790000;
1961 state
->CTFiltMax
[13] = 534530000;
1962 state
->CTFiltMax
[14] = 572610000;
1963 state
->CTFiltMax
[15] = 598970000;
1964 state
->CTFiltMax
[16] = 635910000;
1965 state
->CTFiltMax
[17] = 672130000;
1966 state
->CTFiltMax
[18] = 714840000;
1967 state
->CTFiltMax
[19] = 739660000;
1968 state
->CTFiltMax
[20] = 770410000;
1969 state
->CTFiltMax
[21] = 814660000;
1970 state
->CTFiltMax
[22] = 846950000;
1971 state
->CTFiltMax
[23] = 867820000;
1972 state
->CTFiltMax
[24] = 915980000;
1973 state
->CTFiltMax
[25] = 947450000;
1974 state
->CTFiltMax
[26] = 983110000;
1975 state
->CTFiltMax
[27] = 1021630000;
1976 state
->CTFiltMax
[28] = 1061870000;
1977 state
->CTFiltMax
[29] = 1098330000;
1978 state
->CTFiltMax
[30] = 1138990000;
1981 ** Fetch the FCU osc value and use it and the fRef value to
1982 ** scale all of the Band Max values
1985 state
->reg
[MT2063_REG_CTUNE_CTRL
] = 0x0A;
1986 status
= mt2063_write(state
, MT2063_REG_CTUNE_CTRL
,
1987 &state
->reg
[MT2063_REG_CTUNE_CTRL
], 1);
1991 /* Read the ClearTune filter calibration value */
1992 status
= mt2063_read(state
, MT2063_REG_FIFFC
,
1993 &state
->reg
[MT2063_REG_FIFFC
], 1);
1997 fcu_osc
= state
->reg
[MT2063_REG_FIFFC
];
1999 state
->reg
[MT2063_REG_CTUNE_CTRL
] = 0x00;
2000 status
= mt2063_write(state
, MT2063_REG_CTUNE_CTRL
,
2001 &state
->reg
[MT2063_REG_CTUNE_CTRL
], 1);
2005 /* Adjust each of the values in the ClearTune filter cross-over table */
2006 for (i
= 0; i
< 31; i
++)
2007 state
->CTFiltMax
[i
] = (state
->CTFiltMax
[i
] / 768) * (fcu_osc
+ 640);
2009 status
= MT2063_SoftwareShutdown(state
, 1);
2012 status
= MT2063_ClearPowerMaskBits(state
, MT2063_ALL_SD
);
2021 static int mt2063_get_status(struct dvb_frontend
*fe
, u32
*tuner_status
)
2023 struct mt2063_state
*state
= fe
->tuner_priv
;
2032 status
= mt2063_lockStatus(state
);
2036 *tuner_status
= TUNER_STATUS_LOCKED
;
2038 dprintk(1, "Tuner status: %d", *tuner_status
);
2043 static int mt2063_release(struct dvb_frontend
*fe
)
2045 struct mt2063_state
*state
= fe
->tuner_priv
;
2049 fe
->tuner_priv
= NULL
;
2055 static int mt2063_set_analog_params(struct dvb_frontend
*fe
,
2056 struct analog_parameters
*params
)
2058 struct mt2063_state
*state
= fe
->tuner_priv
;
2069 status
= mt2063_init(fe
);
2074 switch (params
->mode
) {
2075 case V4L2_TUNER_RADIO
:
2076 pict_car
= 38900000;
2078 pict2chanb_vsb
= -(ch_bw
/ 2);
2079 rcvr_mode
= MT2063_OFFAIR_ANALOG
;
2081 case V4L2_TUNER_ANALOG_TV
:
2082 rcvr_mode
= MT2063_CABLE_ANALOG
;
2083 if (params
->std
& ~V4L2_STD_MN
) {
2084 pict_car
= 38900000;
2086 pict2chanb_vsb
= -1250000;
2087 } else if (params
->std
& V4L2_STD_PAL_G
) {
2088 pict_car
= 38900000;
2090 pict2chanb_vsb
= -1250000;
2091 } else { /* PAL/SECAM standards */
2092 pict_car
= 38900000;
2094 pict2chanb_vsb
= -1250000;
2100 if_mid
= pict_car
- (pict2chanb_vsb
+ (ch_bw
/ 2));
2102 state
->AS_Data
.f_LO2_Step
= 125000; /* FIXME: probably 5000 for FM */
2103 state
->AS_Data
.f_out
= if_mid
;
2104 state
->AS_Data
.f_out_bw
= ch_bw
+ 750000;
2105 status
= MT2063_SetReceiverMode(state
, rcvr_mode
);
2109 dprintk(1, "Tuning to frequency: %d, bandwidth %d, foffset %d\n",
2110 params
->frequency
, ch_bw
, pict2chanb_vsb
);
2112 status
= MT2063_Tune(state
, (params
->frequency
+ (pict2chanb_vsb
+ (ch_bw
/ 2))));
2116 state
->frequency
= params
->frequency
;
2121 * As defined on EN 300 429, the DVB-C roll-off factor is 0.15.
2122 * So, the amount of the needed bandwith is given by:
2123 * Bw = Symbol_rate * (1 + 0.15)
2124 * As such, the maximum symbol rate supported by 6 MHz is given by:
2125 * max_symbol_rate = 6 MHz / 1.15 = 5217391 Bauds
2127 #define MAX_SYMBOL_RATE_6MHz 5217391
2129 static int mt2063_set_params(struct dvb_frontend
*fe
)
2131 struct dtv_frontend_properties
*c
= &fe
->dtv_property_cache
;
2132 struct mt2063_state
*state
= fe
->tuner_priv
;
2141 status
= mt2063_init(fe
);
2148 if (c
->bandwidth_hz
== 0)
2150 if (c
->bandwidth_hz
<= 6000000)
2152 else if (c
->bandwidth_hz
<= 7000000)
2157 switch (c
->delivery_system
) {
2159 rcvr_mode
= MT2063_OFFAIR_COFDM
;
2160 pict_car
= 36125000;
2161 pict2chanb_vsb
= -(ch_bw
/ 2);
2163 case SYS_DVBC_ANNEX_A
:
2164 case SYS_DVBC_ANNEX_C
:
2165 rcvr_mode
= MT2063_CABLE_QAM
;
2166 pict_car
= 36125000;
2167 pict2chanb_vsb
= -(ch_bw
/ 2);
2172 if_mid
= pict_car
- (pict2chanb_vsb
+ (ch_bw
/ 2));
2174 state
->AS_Data
.f_LO2_Step
= 125000; /* FIXME: probably 5000 for FM */
2175 state
->AS_Data
.f_out
= if_mid
;
2176 state
->AS_Data
.f_out_bw
= ch_bw
+ 750000;
2177 status
= MT2063_SetReceiverMode(state
, rcvr_mode
);
2181 dprintk(1, "Tuning to frequency: %d, bandwidth %d, foffset %d\n",
2182 c
->frequency
, ch_bw
, pict2chanb_vsb
);
2184 status
= MT2063_Tune(state
, (c
->frequency
+ (pict2chanb_vsb
+ (ch_bw
/ 2))));
2189 state
->frequency
= c
->frequency
;
2193 static int mt2063_get_if_frequency(struct dvb_frontend
*fe
, u32
*freq
)
2195 struct mt2063_state
*state
= fe
->tuner_priv
;
2202 *freq
= state
->AS_Data
.f_out
;
2204 dprintk(1, "IF frequency: %d\n", *freq
);
2209 static int mt2063_get_bandwidth(struct dvb_frontend
*fe
, u32
*bw
)
2211 struct mt2063_state
*state
= fe
->tuner_priv
;
2218 *bw
= state
->AS_Data
.f_out_bw
- 750000;
2220 dprintk(1, "bandwidth: %d\n", *bw
);
2225 static struct dvb_tuner_ops mt2063_ops
= {
2227 .name
= "MT2063 Silicon Tuner",
2228 .frequency_min
= 45000000,
2229 .frequency_max
= 850000000,
2230 .frequency_step
= 0,
2233 .init
= mt2063_init
,
2234 .sleep
= MT2063_Sleep
,
2235 .get_status
= mt2063_get_status
,
2236 .set_analog_params
= mt2063_set_analog_params
,
2237 .set_params
= mt2063_set_params
,
2238 .get_if_frequency
= mt2063_get_if_frequency
,
2239 .get_bandwidth
= mt2063_get_bandwidth
,
2240 .release
= mt2063_release
,
2243 struct dvb_frontend
*mt2063_attach(struct dvb_frontend
*fe
,
2244 struct mt2063_config
*config
,
2245 struct i2c_adapter
*i2c
)
2247 struct mt2063_state
*state
= NULL
;
2251 state
= kzalloc(sizeof(struct mt2063_state
), GFP_KERNEL
);
2255 state
->config
= config
;
2257 state
->frontend
= fe
;
2258 state
->reference
= config
->refclock
/ 1000; /* kHz */
2259 fe
->tuner_priv
= state
;
2260 fe
->ops
.tuner_ops
= mt2063_ops
;
2262 printk(KERN_INFO
"%s: Attaching MT2063\n", __func__
);
2269 EXPORT_SYMBOL_GPL(mt2063_attach
);
2272 * Ancillary routines visible outside mt2063
2273 * FIXME: Remove them in favor of using standard tuner callbacks
2275 unsigned int tuner_MT2063_SoftwareShutdown(struct dvb_frontend
*fe
)
2277 struct mt2063_state
*state
= fe
->tuner_priv
;
2282 err
= MT2063_SoftwareShutdown(state
, 1);
2284 printk(KERN_ERR
"%s: Couldn't shutdown\n", __func__
);
2288 EXPORT_SYMBOL_GPL(tuner_MT2063_SoftwareShutdown
);
2290 unsigned int tuner_MT2063_ClearPowerMaskBits(struct dvb_frontend
*fe
)
2292 struct mt2063_state
*state
= fe
->tuner_priv
;
2297 err
= MT2063_ClearPowerMaskBits(state
, MT2063_ALL_SD
);
2299 printk(KERN_ERR
"%s: Invalid parameter\n", __func__
);
2303 EXPORT_SYMBOL_GPL(tuner_MT2063_ClearPowerMaskBits
);
2305 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
2306 MODULE_DESCRIPTION("MT2063 Silicon tuner");
2307 MODULE_LICENSE("GPL");