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Merge tag 'v3.3.7' into 3.3/master
[zen-stable.git] / drivers / media / dvb / frontends / drxk_hard.c
blob3cce362d0a60be951dbed6ae78f32701599b74be
1 /*
2 * drxk_hard: DRX-K DVB-C/T demodulator driver
3 *
4 * Copyright (C) 2010-2011 Digital Devices GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
9 *
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 * 02110-1301, USA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/init.h>
28 #include <linux/delay.h>
29 #include <linux/firmware.h>
30 #include <linux/i2c.h>
31 #include <linux/version.h>
32 #include <asm/div64.h>
33
34 #include "dvb_frontend.h"
35 #include "drxk.h"
36 #include "drxk_hard.h"
37
38 static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode);
39 static int PowerDownQAM(struct drxk_state *state);
40 static int SetDVBTStandard(struct drxk_state *state,
41 enum OperationMode oMode);
42 static int SetQAMStandard(struct drxk_state *state,
43 enum OperationMode oMode);
44 static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
45 s32 tunerFreqOffset);
46 static int SetDVBTStandard(struct drxk_state *state,
47 enum OperationMode oMode);
48 static int DVBTStart(struct drxk_state *state);
49 static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
50 s32 tunerFreqOffset);
51 static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus);
52 static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus);
53 static int SwitchAntennaToQAM(struct drxk_state *state);
54 static int SwitchAntennaToDVBT(struct drxk_state *state);
55
56 static bool IsDVBT(struct drxk_state *state)
57 {
58 return state->m_OperationMode == OM_DVBT;
59 }
60
61 static bool IsQAM(struct drxk_state *state)
62 {
63 return state->m_OperationMode == OM_QAM_ITU_A ||
64 state->m_OperationMode == OM_QAM_ITU_B ||
65 state->m_OperationMode == OM_QAM_ITU_C;
66 }
67
68 bool IsA1WithPatchCode(struct drxk_state *state)
69 {
70 return state->m_DRXK_A1_PATCH_CODE;
71 }
72
73 bool IsA1WithRomCode(struct drxk_state *state)
74 {
75 return state->m_DRXK_A1_ROM_CODE;
76 }
77
78 #define NOA1ROM 0
79
80 #define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
81 #define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0)
82
83 #define DEFAULT_MER_83 165
84 #define DEFAULT_MER_93 250
85
86 #ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
87 #define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02)
88 #endif
89
90 #ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
91 #define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03)
92 #endif
93
94 #ifndef DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH
95 #define DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH (0x06)
96 #endif
97
98 #define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700
99 #define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500
100
101 #ifndef DRXK_KI_RAGC_ATV
102 #define DRXK_KI_RAGC_ATV 4
103 #endif
104 #ifndef DRXK_KI_IAGC_ATV
105 #define DRXK_KI_IAGC_ATV 6
106 #endif
107 #ifndef DRXK_KI_DAGC_ATV
108 #define DRXK_KI_DAGC_ATV 7
109 #endif
110
111 #ifndef DRXK_KI_RAGC_QAM
112 #define DRXK_KI_RAGC_QAM 3
113 #endif
114 #ifndef DRXK_KI_IAGC_QAM
115 #define DRXK_KI_IAGC_QAM 4
116 #endif
117 #ifndef DRXK_KI_DAGC_QAM
118 #define DRXK_KI_DAGC_QAM 7
119 #endif
120 #ifndef DRXK_KI_RAGC_DVBT
121 #define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2)
122 #endif
123 #ifndef DRXK_KI_IAGC_DVBT
124 #define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2)
125 #endif
126 #ifndef DRXK_KI_DAGC_DVBT
127 #define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7)
128 #endif
129
130 #ifndef DRXK_AGC_DAC_OFFSET
131 #define DRXK_AGC_DAC_OFFSET (0x800)
132 #endif
133
134 #ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ
135 #define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L)
136 #endif
137
138 #ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ
139 #define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L)
140 #endif
141
142 #ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ
143 #define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L)
144 #endif
145
146 #ifndef DRXK_QAM_SYMBOLRATE_MAX
147 #define DRXK_QAM_SYMBOLRATE_MAX (7233000)
148 #endif
149
150 #define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56
151 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64
152 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0
153 #define DRXK_BL_ROM_OFFSET_TAPS_BG 24
154 #define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32
155 #define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40
156 #define DRXK_BL_ROM_OFFSET_TAPS_FM 48
157 #define DRXK_BL_ROM_OFFSET_UCODE 0
158
159 #define DRXK_BLC_TIMEOUT 100
160
161 #define DRXK_BLCC_NR_ELEMENTS_TAPS 2
162 #define DRXK_BLCC_NR_ELEMENTS_UCODE 6
163
164 #define DRXK_BLDC_NR_ELEMENTS_TAPS 28
165
166 #ifndef DRXK_OFDM_NE_NOTCH_WIDTH
167 #define DRXK_OFDM_NE_NOTCH_WIDTH (4)
168 #endif
169
170 #define DRXK_QAM_SL_SIG_POWER_QAM16 (40960)
171 #define DRXK_QAM_SL_SIG_POWER_QAM32 (20480)
172 #define DRXK_QAM_SL_SIG_POWER_QAM64 (43008)
173 #define DRXK_QAM_SL_SIG_POWER_QAM128 (20992)
174 #define DRXK_QAM_SL_SIG_POWER_QAM256 (43520)
175
176 static unsigned int debug;
177 module_param(debug, int, 0644);
178 MODULE_PARM_DESC(debug, "enable debug messages");
179
180 #define dprintk(level, fmt, arg...) do { \
181 if (debug >= level) \
182 printk(KERN_DEBUG "drxk: %s" fmt, __func__, ## arg); \
183 } while (0)
184
185
186 static inline u32 MulDiv32(u32 a, u32 b, u32 c)
187 {
188 u64 tmp64;
189
190 tmp64 = (u64) a * (u64) b;
191 do_div(tmp64, c);
192
193 return (u32) tmp64;
194 }
195
196 inline u32 Frac28a(u32 a, u32 c)
197 {
198 int i = 0;
199 u32 Q1 = 0;
200 u32 R0 = 0;
201
202 R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */
203 Q1 = a / c; /* integer part, only the 4 least significant bits
204 will be visible in the result */
205
206 /* division using radix 16, 7 nibbles in the result */
207 for (i = 0; i < 7; i++) {
208 Q1 = (Q1 << 4) | (R0 / c);
209 R0 = (R0 % c) << 4;
210 }
211 /* rounding */
212 if ((R0 >> 3) >= c)
213 Q1++;
214
215 return Q1;
216 }
217
218 static u32 Log10Times100(u32 x)
219 {
220 static const u8 scale = 15;
221 static const u8 indexWidth = 5;
222 u8 i = 0;
223 u32 y = 0;
224 u32 d = 0;
225 u32 k = 0;
226 u32 r = 0;
227 /*
228 log2lut[n] = (1<<scale) * 200 * log2(1.0 + ((1.0/(1<<INDEXWIDTH)) * n))
229 0 <= n < ((1<<INDEXWIDTH)+1)
230 */
231
232 static const u32 log2lut[] = {
233 0, /* 0.000000 */
234 290941, /* 290941.300628 */
235 573196, /* 573196.476418 */
236 847269, /* 847269.179851 */
237 1113620, /* 1113620.489452 */
238 1372674, /* 1372673.576986 */
239 1624818, /* 1624817.752104 */
240 1870412, /* 1870411.981536 */
241 2109788, /* 2109787.962654 */
242 2343253, /* 2343252.817465 */
243 2571091, /* 2571091.461923 */
244 2793569, /* 2793568.696416 */
245 3010931, /* 3010931.055901 */
246 3223408, /* 3223408.452106 */
247 3431216, /* 3431215.635215 */
248 3634553, /* 3634553.498355 */
249 3833610, /* 3833610.244726 */
250 4028562, /* 4028562.434393 */
251 4219576, /* 4219575.925308 */
252 4406807, /* 4406806.721144 */
253 4590402, /* 4590401.736809 */
254 4770499, /* 4770499.491025 */
255 4947231, /* 4947230.734179 */
256 5120719, /* 5120719.018555 */
257 5291081, /* 5291081.217197 */
258 5458428, /* 5458427.996830 */
259 5622864, /* 5622864.249668 */
260 5784489, /* 5784489.488298 */
261 5943398, /* 5943398.207380 */
262 6099680, /* 6099680.215452 */
263 6253421, /* 6253420.939751 */
264 6404702, /* 6404701.706649 */
265 6553600, /* 6553600.000000 */
266 };
267
268
269 if (x == 0)
270 return 0;
271
272 /* Scale x (normalize) */
273 /* computing y in log(x/y) = log(x) - log(y) */
274 if ((x & ((0xffffffff) << (scale + 1))) == 0) {
275 for (k = scale; k > 0; k--) {
276 if (x & (((u32) 1) << scale))
277 break;
278 x <<= 1;
279 }
280 } else {
281 for (k = scale; k < 31; k++) {
282 if ((x & (((u32) (-1)) << (scale + 1))) == 0)
283 break;
284 x >>= 1;
285 }
286 }
287 /*
288 Now x has binary point between bit[scale] and bit[scale-1]
289 and 1.0 <= x < 2.0 */
290
291 /* correction for divison: log(x) = log(x/y)+log(y) */
292 y = k * ((((u32) 1) << scale) * 200);
293
294 /* remove integer part */
295 x &= ((((u32) 1) << scale) - 1);
296 /* get index */
297 i = (u8) (x >> (scale - indexWidth));
298 /* compute delta (x - a) */
299 d = x & ((((u32) 1) << (scale - indexWidth)) - 1);
300 /* compute log, multiplication (d* (..)) must be within range ! */
301 y += log2lut[i] +
302 ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - indexWidth));
303 /* Conver to log10() */
304 y /= 108853; /* (log2(10) << scale) */
305 r = (y >> 1);
306 /* rounding */
307 if (y & ((u32) 1))
308 r++;
309 return r;
310 }
311
312 /****************************************************************************/
313 /* I2C **********************************************************************/
314 /****************************************************************************/
315
316 static int i2c_read1(struct i2c_adapter *adapter, u8 adr, u8 *val)
317 {
318 struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD,
319 .buf = val, .len = 1}
320 };
321
322 return i2c_transfer(adapter, msgs, 1);
323 }
324
325 static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)
326 {
327 int status;
328 struct i2c_msg msg = {
329 .addr = adr, .flags = 0, .buf = data, .len = len };
330
331 dprintk(3, ":");
332 if (debug > 2) {
333 int i;
334 for (i = 0; i < len; i++)
335 printk(KERN_CONT " %02x", data[i]);
336 printk(KERN_CONT "\n");
337 }
338 status = i2c_transfer(adap, &msg, 1);
339 if (status >= 0 && status != 1)
340 status = -EIO;
341
342 if (status < 0)
343 printk(KERN_ERR "drxk: i2c write error at addr 0x%02x\n", adr);
344
345 return status;
346 }
347
348 static int i2c_read(struct i2c_adapter *adap,
349 u8 adr, u8 *msg, int len, u8 *answ, int alen)
350 {
351 int status;
352 struct i2c_msg msgs[2] = {
353 {.addr = adr, .flags = 0,
354 .buf = msg, .len = len},
355 {.addr = adr, .flags = I2C_M_RD,
356 .buf = answ, .len = alen}
357 };
358
359 status = i2c_transfer(adap, msgs, 2);
360 if (status != 2) {
361 if (debug > 2)
362 printk(KERN_CONT ": ERROR!\n");
363 if (status >= 0)
364 status = -EIO;
365
366 printk(KERN_ERR "drxk: i2c read error at addr 0x%02x\n", adr);
367 return status;
368 }
369 if (debug > 2) {
370 int i;
371 dprintk(2, ": read from");
372 for (i = 0; i < len; i++)
373 printk(KERN_CONT " %02x", msg[i]);
374 printk(KERN_CONT ", value = ");
375 for (i = 0; i < alen; i++)
376 printk(KERN_CONT " %02x", answ[i]);
377 printk(KERN_CONT "\n");
378 }
379 return 0;
380 }
381
382 static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
383 {
384 int status;
385 u8 adr = state->demod_address, mm1[4], mm2[2], len;
386
387 if (state->single_master)
388 flags |= 0xC0;
389
390 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
391 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
392 mm1[1] = ((reg >> 16) & 0xFF);
393 mm1[2] = ((reg >> 24) & 0xFF) | flags;
394 mm1[3] = ((reg >> 7) & 0xFF);
395 len = 4;
396 } else {
397 mm1[0] = ((reg << 1) & 0xFF);
398 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
399 len = 2;
400 }
401 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
402 status = i2c_read(state->i2c, adr, mm1, len, mm2, 2);
403 if (status < 0)
404 return status;
405 if (data)
406 *data = mm2[0] | (mm2[1] << 8);
407
408 return 0;
409 }
410
411 static int read16(struct drxk_state *state, u32 reg, u16 *data)
412 {
413 return read16_flags(state, reg, data, 0);
414 }
415
416 static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
417 {
418 int status;
419 u8 adr = state->demod_address, mm1[4], mm2[4], len;
420
421 if (state->single_master)
422 flags |= 0xC0;
423
424 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
425 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
426 mm1[1] = ((reg >> 16) & 0xFF);
427 mm1[2] = ((reg >> 24) & 0xFF) | flags;
428 mm1[3] = ((reg >> 7) & 0xFF);
429 len = 4;
430 } else {
431 mm1[0] = ((reg << 1) & 0xFF);
432 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
433 len = 2;
434 }
435 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
436 status = i2c_read(state->i2c, adr, mm1, len, mm2, 4);
437 if (status < 0)
438 return status;
439 if (data)
440 *data = mm2[0] | (mm2[1] << 8) |
441 (mm2[2] << 16) | (mm2[3] << 24);
442
443 return 0;
444 }
445
446 static int read32(struct drxk_state *state, u32 reg, u32 *data)
447 {
448 return read32_flags(state, reg, data, 0);
449 }
450
451 static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
452 {
453 u8 adr = state->demod_address, mm[6], len;
454
455 if (state->single_master)
456 flags |= 0xC0;
457 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
458 mm[0] = (((reg << 1) & 0xFF) | 0x01);
459 mm[1] = ((reg >> 16) & 0xFF);
460 mm[2] = ((reg >> 24) & 0xFF) | flags;
461 mm[3] = ((reg >> 7) & 0xFF);
462 len = 4;
463 } else {
464 mm[0] = ((reg << 1) & 0xFF);
465 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
466 len = 2;
467 }
468 mm[len] = data & 0xff;
469 mm[len + 1] = (data >> 8) & 0xff;
470
471 dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags);
472 return i2c_write(state->i2c, adr, mm, len + 2);
473 }
474
475 static int write16(struct drxk_state *state, u32 reg, u16 data)
476 {
477 return write16_flags(state, reg, data, 0);
478 }
479
480 static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
481 {
482 u8 adr = state->demod_address, mm[8], len;
483
484 if (state->single_master)
485 flags |= 0xC0;
486 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
487 mm[0] = (((reg << 1) & 0xFF) | 0x01);
488 mm[1] = ((reg >> 16) & 0xFF);
489 mm[2] = ((reg >> 24) & 0xFF) | flags;
490 mm[3] = ((reg >> 7) & 0xFF);
491 len = 4;
492 } else {
493 mm[0] = ((reg << 1) & 0xFF);
494 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
495 len = 2;
496 }
497 mm[len] = data & 0xff;
498 mm[len + 1] = (data >> 8) & 0xff;
499 mm[len + 2] = (data >> 16) & 0xff;
500 mm[len + 3] = (data >> 24) & 0xff;
501 dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags);
502
503 return i2c_write(state->i2c, adr, mm, len + 4);
504 }
505
506 static int write32(struct drxk_state *state, u32 reg, u32 data)
507 {
508 return write32_flags(state, reg, data, 0);
509 }
510
511 static int write_block(struct drxk_state *state, u32 Address,
512 const int BlockSize, const u8 pBlock[])
513 {
514 int status = 0, BlkSize = BlockSize;
515 u8 Flags = 0;
516
517 if (state->single_master)
518 Flags |= 0xC0;
519
520 while (BlkSize > 0) {
521 int Chunk = BlkSize > state->m_ChunkSize ?
522 state->m_ChunkSize : BlkSize;
523 u8 *AdrBuf = &state->Chunk[0];
524 u32 AdrLength = 0;
525
526 if (DRXDAP_FASI_LONG_FORMAT(Address) || (Flags != 0)) {
527 AdrBuf[0] = (((Address << 1) & 0xFF) | 0x01);
528 AdrBuf[1] = ((Address >> 16) & 0xFF);
529 AdrBuf[2] = ((Address >> 24) & 0xFF);
530 AdrBuf[3] = ((Address >> 7) & 0xFF);
531 AdrBuf[2] |= Flags;
532 AdrLength = 4;
533 if (Chunk == state->m_ChunkSize)
534 Chunk -= 2;
535 } else {
536 AdrBuf[0] = ((Address << 1) & 0xFF);
537 AdrBuf[1] = (((Address >> 16) & 0x0F) |
538 ((Address >> 18) & 0xF0));
539 AdrLength = 2;
540 }
541 memcpy(&state->Chunk[AdrLength], pBlock, Chunk);
542 dprintk(2, "(0x%08x, 0x%02x)\n", Address, Flags);
543 if (debug > 1) {
544 int i;
545 if (pBlock)
546 for (i = 0; i < Chunk; i++)
547 printk(KERN_CONT " %02x", pBlock[i]);
548 printk(KERN_CONT "\n");
549 }
550 status = i2c_write(state->i2c, state->demod_address,
551 &state->Chunk[0], Chunk + AdrLength);
552 if (status < 0) {
553 printk(KERN_ERR "drxk: %s: i2c write error at addr 0x%02x\n",
554 __func__, Address);
555 break;
556 }
557 pBlock += Chunk;
558 Address += (Chunk >> 1);
559 BlkSize -= Chunk;
560 }
561 return status;
562 }
563
564 #ifndef DRXK_MAX_RETRIES_POWERUP
565 #define DRXK_MAX_RETRIES_POWERUP 20
566 #endif
567
568 int PowerUpDevice(struct drxk_state *state)
569 {
570 int status;
571 u8 data = 0;
572 u16 retryCount = 0;
573
574 dprintk(1, "\n");
575
576 status = i2c_read1(state->i2c, state->demod_address, &data);
577 if (status < 0) {
578 do {
579 data = 0;
580 status = i2c_write(state->i2c, state->demod_address,
581 &data, 1);
582 msleep(10);
583 retryCount++;
584 if (status < 0)
585 continue;
586 status = i2c_read1(state->i2c, state->demod_address,
587 &data);
588 } while (status < 0 &&
589 (retryCount < DRXK_MAX_RETRIES_POWERUP));
590 if (status < 0 && retryCount >= DRXK_MAX_RETRIES_POWERUP)
591 goto error;
592 }
593
594 /* Make sure all clk domains are active */
595 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
596 if (status < 0)
597 goto error;
598 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
599 if (status < 0)
600 goto error;
601 /* Enable pll lock tests */
602 status = write16(state, SIO_CC_PLL_LOCK__A, 1);
603 if (status < 0)
604 goto error;
605
606 state->m_currentPowerMode = DRX_POWER_UP;
607
608 error:
609 if (status < 0)
610 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
611
612 return status;
613 }
614
615
616 static int init_state(struct drxk_state *state)
617 {
618 /*
619 * FIXME: most (all?) of the values bellow should be moved into
620 * struct drxk_config, as they are probably board-specific
621 */
622 u32 ulVSBIfAgcMode = DRXK_AGC_CTRL_AUTO;
623 u32 ulVSBIfAgcOutputLevel = 0;
624 u32 ulVSBIfAgcMinLevel = 0;
625 u32 ulVSBIfAgcMaxLevel = 0x7FFF;
626 u32 ulVSBIfAgcSpeed = 3;
627
628 u32 ulVSBRfAgcMode = DRXK_AGC_CTRL_AUTO;
629 u32 ulVSBRfAgcOutputLevel = 0;
630 u32 ulVSBRfAgcMinLevel = 0;
631 u32 ulVSBRfAgcMaxLevel = 0x7FFF;
632 u32 ulVSBRfAgcSpeed = 3;
633 u32 ulVSBRfAgcTop = 9500;
634 u32 ulVSBRfAgcCutOffCurrent = 4000;
635
636 u32 ulATVIfAgcMode = DRXK_AGC_CTRL_AUTO;
637 u32 ulATVIfAgcOutputLevel = 0;
638 u32 ulATVIfAgcMinLevel = 0;
639 u32 ulATVIfAgcMaxLevel = 0;
640 u32 ulATVIfAgcSpeed = 3;
641
642 u32 ulATVRfAgcMode = DRXK_AGC_CTRL_OFF;
643 u32 ulATVRfAgcOutputLevel = 0;
644 u32 ulATVRfAgcMinLevel = 0;
645 u32 ulATVRfAgcMaxLevel = 0;
646 u32 ulATVRfAgcTop = 9500;
647 u32 ulATVRfAgcCutOffCurrent = 4000;
648 u32 ulATVRfAgcSpeed = 3;
649
650 u32 ulQual83 = DEFAULT_MER_83;
651 u32 ulQual93 = DEFAULT_MER_93;
652
653 u32 ulDVBTStaticTSClock = 1;
654 u32 ulDVBCStaticTSClock = 1;
655
656 u32 ulMpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
657 u32 ulDemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
658
659 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
660 /* io_pad_cfg_mode output mode is drive always */
661 /* io_pad_cfg_drive is set to power 2 (23 mA) */
662 u32 ulGPIOCfg = 0x0113;
663 u32 ulInvertTSClock = 0;
664 u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
665 u32 ulTSClockkStrength = DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH;
666 u32 ulDVBTBitrate = 50000000;
667 u32 ulDVBCBitrate = DRXK_QAM_SYMBOLRATE_MAX * 8;
668
669 u32 ulInsertRSByte = 0;
670
671 u32 ulRfMirror = 1;
672 u32 ulPowerDown = 0;
673
674 dprintk(1, "\n");
675
676 state->m_hasLNA = false;
677 state->m_hasDVBT = false;
678 state->m_hasDVBC = false;
679 state->m_hasATV = false;
680 state->m_hasOOB = false;
681 state->m_hasAudio = false;
682
683 if (!state->m_ChunkSize)
684 state->m_ChunkSize = 124;
685
686 state->m_oscClockFreq = 0;
687 state->m_smartAntInverted = false;
688 state->m_bPDownOpenBridge = false;
689
690 /* real system clock frequency in kHz */
691 state->m_sysClockFreq = 151875;
692 /* Timing div, 250ns/Psys */
693 /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */
694 state->m_HICfgTimingDiv = ((state->m_sysClockFreq / 1000) *
695 HI_I2C_DELAY) / 1000;
696 /* Clipping */
697 if (state->m_HICfgTimingDiv > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
698 state->m_HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
699 state->m_HICfgWakeUpKey = (state->demod_address << 1);
700 /* port/bridge/power down ctrl */
701 state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
702
703 state->m_bPowerDown = (ulPowerDown != 0);
704
705 state->m_DRXK_A1_PATCH_CODE = false;
706 state->m_DRXK_A1_ROM_CODE = false;
707 state->m_DRXK_A2_ROM_CODE = false;
708 state->m_DRXK_A3_ROM_CODE = false;
709 state->m_DRXK_A2_PATCH_CODE = false;
710 state->m_DRXK_A3_PATCH_CODE = false;
711
712 /* Init AGC and PGA parameters */
713 /* VSB IF */
714 state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode);
715 state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel);
716 state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel);
717 state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel);
718 state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed);
719 state->m_vsbPgaCfg = 140;
720
721 /* VSB RF */
722 state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode);
723 state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel);
724 state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel);
725 state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel);
726 state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed);
727 state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop);
728 state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent);
729 state->m_vsbPreSawCfg.reference = 0x07;
730 state->m_vsbPreSawCfg.usePreSaw = true;
731
732 state->m_Quality83percent = DEFAULT_MER_83;
733 state->m_Quality93percent = DEFAULT_MER_93;
734 if (ulQual93 <= 500 && ulQual83 < ulQual93) {
735 state->m_Quality83percent = ulQual83;
736 state->m_Quality93percent = ulQual93;
737 }
738
739 /* ATV IF */
740 state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode);
741 state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel);
742 state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel);
743 state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel);
744 state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed);
745
746 /* ATV RF */
747 state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode);
748 state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel);
749 state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel);
750 state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel);
751 state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed);
752 state->m_atvRfAgcCfg.top = (ulATVRfAgcTop);
753 state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent);
754 state->m_atvPreSawCfg.reference = 0x04;
755 state->m_atvPreSawCfg.usePreSaw = true;
756
757
758 /* DVBT RF */
759 state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
760 state->m_dvbtRfAgcCfg.outputLevel = 0;
761 state->m_dvbtRfAgcCfg.minOutputLevel = 0;
762 state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF;
763 state->m_dvbtRfAgcCfg.top = 0x2100;
764 state->m_dvbtRfAgcCfg.cutOffCurrent = 4000;
765 state->m_dvbtRfAgcCfg.speed = 1;
766
767
768 /* DVBT IF */
769 state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
770 state->m_dvbtIfAgcCfg.outputLevel = 0;
771 state->m_dvbtIfAgcCfg.minOutputLevel = 0;
772 state->m_dvbtIfAgcCfg.maxOutputLevel = 9000;
773 state->m_dvbtIfAgcCfg.top = 13424;
774 state->m_dvbtIfAgcCfg.cutOffCurrent = 0;
775 state->m_dvbtIfAgcCfg.speed = 3;
776 state->m_dvbtIfAgcCfg.FastClipCtrlDelay = 30;
777 state->m_dvbtIfAgcCfg.IngainTgtMax = 30000;
778 /* state->m_dvbtPgaCfg = 140; */
779
780 state->m_dvbtPreSawCfg.reference = 4;
781 state->m_dvbtPreSawCfg.usePreSaw = false;
782
783 /* QAM RF */
784 state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
785 state->m_qamRfAgcCfg.outputLevel = 0;
786 state->m_qamRfAgcCfg.minOutputLevel = 6023;
787 state->m_qamRfAgcCfg.maxOutputLevel = 27000;
788 state->m_qamRfAgcCfg.top = 0x2380;
789 state->m_qamRfAgcCfg.cutOffCurrent = 4000;
790 state->m_qamRfAgcCfg.speed = 3;
791
792 /* QAM IF */
793 state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
794 state->m_qamIfAgcCfg.outputLevel = 0;
795 state->m_qamIfAgcCfg.minOutputLevel = 0;
796 state->m_qamIfAgcCfg.maxOutputLevel = 9000;
797 state->m_qamIfAgcCfg.top = 0x0511;
798 state->m_qamIfAgcCfg.cutOffCurrent = 0;
799 state->m_qamIfAgcCfg.speed = 3;
800 state->m_qamIfAgcCfg.IngainTgtMax = 5119;
801 state->m_qamIfAgcCfg.FastClipCtrlDelay = 50;
802
803 state->m_qamPgaCfg = 140;
804 state->m_qamPreSawCfg.reference = 4;
805 state->m_qamPreSawCfg.usePreSaw = false;
806
807 state->m_OperationMode = OM_NONE;
808 state->m_DrxkState = DRXK_UNINITIALIZED;
809
810 /* MPEG output configuration */
811 state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */
812 state->m_insertRSByte = false; /* If TRUE; insert RS byte */
813 state->m_invertDATA = false; /* If TRUE; invert DATA signals */
814 state->m_invertERR = false; /* If TRUE; invert ERR signal */
815 state->m_invertSTR = false; /* If TRUE; invert STR signals */
816 state->m_invertVAL = false; /* If TRUE; invert VAL signals */
817 state->m_invertCLK = (ulInvertTSClock != 0); /* If TRUE; invert CLK signals */
818 state->m_DVBTStaticCLK = (ulDVBTStaticTSClock != 0);
819 state->m_DVBCStaticCLK = (ulDVBCStaticTSClock != 0);
820 /* If TRUE; static MPEG clockrate will be used;
821 otherwise clockrate will adapt to the bitrate of the TS */
822
823 state->m_DVBTBitrate = ulDVBTBitrate;
824 state->m_DVBCBitrate = ulDVBCBitrate;
825
826 state->m_TSDataStrength = (ulTSDataStrength & 0x07);
827 state->m_TSClockkStrength = (ulTSClockkStrength & 0x07);
828
829 /* Maximum bitrate in b/s in case static clockrate is selected */
830 state->m_mpegTsStaticBitrate = 19392658;
831 state->m_disableTEIhandling = false;
832
833 if (ulInsertRSByte)
834 state->m_insertRSByte = true;
835
836 state->m_MpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
837 if (ulMpegLockTimeOut < 10000)
838 state->m_MpegLockTimeOut = ulMpegLockTimeOut;
839 state->m_DemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
840 if (ulDemodLockTimeOut < 10000)
841 state->m_DemodLockTimeOut = ulDemodLockTimeOut;
842
843 /* QAM defaults */
844 state->m_Constellation = DRX_CONSTELLATION_AUTO;
845 state->m_qamInterleaveMode = DRXK_QAM_I12_J17;
846 state->m_fecRsPlen = 204 * 8; /* fecRsPlen annex A */
847 state->m_fecRsPrescale = 1;
848
849 state->m_sqiSpeed = DRXK_DVBT_SQI_SPEED_MEDIUM;
850 state->m_agcFastClipCtrlDelay = 0;
851
852 state->m_GPIOCfg = (ulGPIOCfg);
853
854 state->m_bPowerDown = false;
855 state->m_currentPowerMode = DRX_POWER_DOWN;
856
857 state->m_rfmirror = (ulRfMirror == 0);
858 state->m_IfAgcPol = false;
859 return 0;
860 }
861
862 static int DRXX_Open(struct drxk_state *state)
863 {
864 int status = 0;
865 u32 jtag = 0;
866 u16 bid = 0;
867 u16 key = 0;
868
869 dprintk(1, "\n");
870 /* stop lock indicator process */
871 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
872 if (status < 0)
873 goto error;
874 /* Check device id */
875 status = read16(state, SIO_TOP_COMM_KEY__A, &key);
876 if (status < 0)
877 goto error;
878 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
879 if (status < 0)
880 goto error;
881 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
882 if (status < 0)
883 goto error;
884 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
885 if (status < 0)
886 goto error;
887 status = write16(state, SIO_TOP_COMM_KEY__A, key);
888 error:
889 if (status < 0)
890 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
891 return status;
892 }
893
894 static int GetDeviceCapabilities(struct drxk_state *state)
895 {
896 u16 sioPdrOhwCfg = 0;
897 u32 sioTopJtagidLo = 0;
898 int status;
899 const char *spin = "";
900
901 dprintk(1, "\n");
902
903 /* driver 0.9.0 */
904 /* stop lock indicator process */
905 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
906 if (status < 0)
907 goto error;
908 status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA);
909 if (status < 0)
910 goto error;
911 status = read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg);
912 if (status < 0)
913 goto error;
914 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
915 if (status < 0)
916 goto error;
917
918 switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
919 case 0:
920 /* ignore (bypass ?) */
921 break;
922 case 1:
923 /* 27 MHz */
924 state->m_oscClockFreq = 27000;
925 break;
926 case 2:
927 /* 20.25 MHz */
928 state->m_oscClockFreq = 20250;
929 break;
930 case 3:
931 /* 4 MHz */
932 state->m_oscClockFreq = 20250;
933 break;
934 default:
935 printk(KERN_ERR "drxk: Clock Frequency is unkonwn\n");
936 return -EINVAL;
937 }
938 /*
939 Determine device capabilities
940 Based on pinning v14
941 */
942 status = read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo);
943 if (status < 0)
944 goto error;
945
946 printk(KERN_ERR "drxk: status = 0x%08x\n", sioTopJtagidLo);
947
948 /* driver 0.9.0 */
949 switch ((sioTopJtagidLo >> 29) & 0xF) {
950 case 0:
951 state->m_deviceSpin = DRXK_SPIN_A1;
952 spin = "A1";
953 break;
954 case 2:
955 state->m_deviceSpin = DRXK_SPIN_A2;
956 spin = "A2";
957 break;
958 case 3:
959 state->m_deviceSpin = DRXK_SPIN_A3;
960 spin = "A3";
961 break;
962 default:
963 state->m_deviceSpin = DRXK_SPIN_UNKNOWN;
964 status = -EINVAL;
965 printk(KERN_ERR "drxk: Spin %d unknown\n",
966 (sioTopJtagidLo >> 29) & 0xF);
967 goto error2;
968 }
969 switch ((sioTopJtagidLo >> 12) & 0xFF) {
970 case 0x13:
971 /* typeId = DRX3913K_TYPE_ID */
972 state->m_hasLNA = false;
973 state->m_hasOOB = false;
974 state->m_hasATV = false;
975 state->m_hasAudio = false;
976 state->m_hasDVBT = true;
977 state->m_hasDVBC = true;
978 state->m_hasSAWSW = true;
979 state->m_hasGPIO2 = false;
980 state->m_hasGPIO1 = false;
981 state->m_hasIRQN = false;
982 break;
983 case 0x15:
984 /* typeId = DRX3915K_TYPE_ID */
985 state->m_hasLNA = false;
986 state->m_hasOOB = false;
987 state->m_hasATV = true;
988 state->m_hasAudio = false;
989 state->m_hasDVBT = true;
990 state->m_hasDVBC = false;
991 state->m_hasSAWSW = true;
992 state->m_hasGPIO2 = true;
993 state->m_hasGPIO1 = true;
994 state->m_hasIRQN = false;
995 break;
996 case 0x16:
997 /* typeId = DRX3916K_TYPE_ID */
998 state->m_hasLNA = false;
999 state->m_hasOOB = false;
1000 state->m_hasATV = true;
1001 state->m_hasAudio = false;
1002 state->m_hasDVBT = true;
1003 state->m_hasDVBC = false;
1004 state->m_hasSAWSW = true;
1005 state->m_hasGPIO2 = true;
1006 state->m_hasGPIO1 = true;
1007 state->m_hasIRQN = false;
1008 break;
1009 case 0x18:
1010 /* typeId = DRX3918K_TYPE_ID */
1011 state->m_hasLNA = false;
1012 state->m_hasOOB = false;
1013 state->m_hasATV = true;
1014 state->m_hasAudio = true;
1015 state->m_hasDVBT = true;
1016 state->m_hasDVBC = false;
1017 state->m_hasSAWSW = true;
1018 state->m_hasGPIO2 = true;
1019 state->m_hasGPIO1 = true;
1020 state->m_hasIRQN = false;
1021 break;
1022 case 0x21:
1023 /* typeId = DRX3921K_TYPE_ID */
1024 state->m_hasLNA = false;
1025 state->m_hasOOB = false;
1026 state->m_hasATV = true;
1027 state->m_hasAudio = true;
1028 state->m_hasDVBT = true;
1029 state->m_hasDVBC = true;
1030 state->m_hasSAWSW = true;
1031 state->m_hasGPIO2 = true;
1032 state->m_hasGPIO1 = true;
1033 state->m_hasIRQN = false;
1034 break;
1035 case 0x23:
1036 /* typeId = DRX3923K_TYPE_ID */
1037 state->m_hasLNA = false;
1038 state->m_hasOOB = false;
1039 state->m_hasATV = true;
1040 state->m_hasAudio = true;
1041 state->m_hasDVBT = true;
1042 state->m_hasDVBC = true;
1043 state->m_hasSAWSW = true;
1044 state->m_hasGPIO2 = true;
1045 state->m_hasGPIO1 = true;
1046 state->m_hasIRQN = false;
1047 break;
1048 case 0x25:
1049 /* typeId = DRX3925K_TYPE_ID */
1050 state->m_hasLNA = false;
1051 state->m_hasOOB = false;
1052 state->m_hasATV = true;
1053 state->m_hasAudio = true;
1054 state->m_hasDVBT = true;
1055 state->m_hasDVBC = true;
1056 state->m_hasSAWSW = true;
1057 state->m_hasGPIO2 = true;
1058 state->m_hasGPIO1 = true;
1059 state->m_hasIRQN = false;
1060 break;
1061 case 0x26:
1062 /* typeId = DRX3926K_TYPE_ID */
1063 state->m_hasLNA = false;
1064 state->m_hasOOB = false;
1065 state->m_hasATV = true;
1066 state->m_hasAudio = false;
1067 state->m_hasDVBT = true;
1068 state->m_hasDVBC = true;
1069 state->m_hasSAWSW = true;
1070 state->m_hasGPIO2 = true;
1071 state->m_hasGPIO1 = true;
1072 state->m_hasIRQN = false;
1073 break;
1074 default:
1075 printk(KERN_ERR "drxk: DeviceID 0x%02x not supported\n",
1076 ((sioTopJtagidLo >> 12) & 0xFF));
1077 status = -EINVAL;
1078 goto error2;
1079 }
1080
1081 printk(KERN_INFO
1082 "drxk: detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n",
1083 ((sioTopJtagidLo >> 12) & 0xFF), spin,
1084 state->m_oscClockFreq / 1000,
1085 state->m_oscClockFreq % 1000);
1086
1087 error:
1088 if (status < 0)
1089 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1090
1091 error2:
1092 return status;
1093 }
1094
1095 static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult)
1096 {
1097 int status;
1098 bool powerdown_cmd;
1099
1100 dprintk(1, "\n");
1101
1102 /* Write command */
1103 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
1104 if (status < 0)
1105 goto error;
1106 if (cmd == SIO_HI_RA_RAM_CMD_RESET)
1107 msleep(1);
1108
1109 powerdown_cmd =
1110 (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
1111 ((state->m_HICfgCtrl) &
1112 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
1113 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
1114 if (powerdown_cmd == false) {
1115 /* Wait until command rdy */
1116 u32 retryCount = 0;
1117 u16 waitCmd;
1118
1119 do {
1120 msleep(1);
1121 retryCount += 1;
1122 status = read16(state, SIO_HI_RA_RAM_CMD__A,
1123 &waitCmd);
1124 } while ((status < 0) && (retryCount < DRXK_MAX_RETRIES)
1125 && (waitCmd != 0));
1126 if (status < 0)
1127 goto error;
1128 status = read16(state, SIO_HI_RA_RAM_RES__A, pResult);
1129 }
1130 error:
1131 if (status < 0)
1132 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1133
1134 return status;
1135 }
1136
1137 static int HI_CfgCommand(struct drxk_state *state)
1138 {
1139 int status;
1140
1141 dprintk(1, "\n");
1142
1143 mutex_lock(&state->mutex);
1144
1145 status = write16(state, SIO_HI_RA_RAM_PAR_6__A, state->m_HICfgTimeout);
1146 if (status < 0)
1147 goto error;
1148 status = write16(state, SIO_HI_RA_RAM_PAR_5__A, state->m_HICfgCtrl);
1149 if (status < 0)
1150 goto error;
1151 status = write16(state, SIO_HI_RA_RAM_PAR_4__A, state->m_HICfgWakeUpKey);
1152 if (status < 0)
1153 goto error;
1154 status = write16(state, SIO_HI_RA_RAM_PAR_3__A, state->m_HICfgBridgeDelay);
1155 if (status < 0)
1156 goto error;
1157 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, state->m_HICfgTimingDiv);
1158 if (status < 0)
1159 goto error;
1160 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
1161 if (status < 0)
1162 goto error;
1163 status = HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0);
1164 if (status < 0)
1165 goto error;
1166
1167 state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1168 error:
1169 mutex_unlock(&state->mutex);
1170 if (status < 0)
1171 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1172 return status;
1173 }
1174
1175 static int InitHI(struct drxk_state *state)
1176 {
1177 dprintk(1, "\n");
1178
1179 state->m_HICfgWakeUpKey = (state->demod_address << 1);
1180 state->m_HICfgTimeout = 0x96FF;
1181 /* port/bridge/power down ctrl */
1182 state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
1183
1184 return HI_CfgCommand(state);
1185 }
1186
1187 static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
1188 {
1189 int status = -1;
1190 u16 sioPdrMclkCfg = 0;
1191 u16 sioPdrMdxCfg = 0;
1192
1193 dprintk(1, ": mpeg %s, %s mode\n",
1194 mpegEnable ? "enable" : "disable",
1195 state->m_enableParallel ? "parallel" : "serial");
1196
1197 /* stop lock indicator process */
1198 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1199 if (status < 0)
1200 goto error;
1201
1202 /* MPEG TS pad configuration */
1203 status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA);
1204 if (status < 0)
1205 goto error;
1206
1207 if (mpegEnable == false) {
1208 /* Set MPEG TS pads to inputmode */
1209 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
1210 if (status < 0)
1211 goto error;
1212 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1213 if (status < 0)
1214 goto error;
1215 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1216 if (status < 0)
1217 goto error;
1218 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1219 if (status < 0)
1220 goto error;
1221 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1222 if (status < 0)
1223 goto error;
1224 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1225 if (status < 0)
1226 goto error;
1227 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1228 if (status < 0)
1229 goto error;
1230 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1231 if (status < 0)
1232 goto error;
1233 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1234 if (status < 0)
1235 goto error;
1236 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1237 if (status < 0)
1238 goto error;
1239 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1240 if (status < 0)
1241 goto error;
1242 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1243 if (status < 0)
1244 goto error;
1245 } else {
1246 /* Enable MPEG output */
1247 sioPdrMdxCfg =
1248 ((state->m_TSDataStrength <<
1249 SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
1250 sioPdrMclkCfg = ((state->m_TSClockkStrength <<
1251 SIO_PDR_MCLK_CFG_DRIVE__B) |
1252 0x0003);
1253
1254 status = write16(state, SIO_PDR_MSTRT_CFG__A, sioPdrMdxCfg);
1255 if (status < 0)
1256 goto error;
1257 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000); /* Disable */
1258 if (status < 0)
1259 goto error;
1260 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000); /* Disable */
1261 if (status < 0)
1262 goto error;
1263 if (state->m_enableParallel == true) {
1264 /* paralel -> enable MD1 to MD7 */
1265 status = write16(state, SIO_PDR_MD1_CFG__A, sioPdrMdxCfg);
1266 if (status < 0)
1267 goto error;
1268 status = write16(state, SIO_PDR_MD2_CFG__A, sioPdrMdxCfg);
1269 if (status < 0)
1270 goto error;
1271 status = write16(state, SIO_PDR_MD3_CFG__A, sioPdrMdxCfg);
1272 if (status < 0)
1273 goto error;
1274 status = write16(state, SIO_PDR_MD4_CFG__A, sioPdrMdxCfg);
1275 if (status < 0)
1276 goto error;
1277 status = write16(state, SIO_PDR_MD5_CFG__A, sioPdrMdxCfg);
1278 if (status < 0)
1279 goto error;
1280 status = write16(state, SIO_PDR_MD6_CFG__A, sioPdrMdxCfg);
1281 if (status < 0)
1282 goto error;
1283 status = write16(state, SIO_PDR_MD7_CFG__A, sioPdrMdxCfg);
1284 if (status < 0)
1285 goto error;
1286 } else {
1287 sioPdrMdxCfg = ((state->m_TSDataStrength <<
1288 SIO_PDR_MD0_CFG_DRIVE__B)
1289 | 0x0003);
1290 /* serial -> disable MD1 to MD7 */
1291 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1292 if (status < 0)
1293 goto error;
1294 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1295 if (status < 0)
1296 goto error;
1297 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1298 if (status < 0)
1299 goto error;
1300 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1301 if (status < 0)
1302 goto error;
1303 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1304 if (status < 0)
1305 goto error;
1306 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1307 if (status < 0)
1308 goto error;
1309 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1310 if (status < 0)
1311 goto error;
1312 }
1313 status = write16(state, SIO_PDR_MCLK_CFG__A, sioPdrMclkCfg);
1314 if (status < 0)
1315 goto error;
1316 status = write16(state, SIO_PDR_MD0_CFG__A, sioPdrMdxCfg);
1317 if (status < 0)
1318 goto error;
1319 }
1320 /* Enable MB output over MPEG pads and ctl input */
1321 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1322 if (status < 0)
1323 goto error;
1324 /* Write nomagic word to enable pdr reg write */
1325 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1326 error:
1327 if (status < 0)
1328 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1329 return status;
1330 }
1331
1332 static int MPEGTSDisable(struct drxk_state *state)
1333 {
1334 dprintk(1, "\n");
1335
1336 return MPEGTSConfigurePins(state, false);
1337 }
1338
1339 static int BLChainCmd(struct drxk_state *state,
1340 u16 romOffset, u16 nrOfElements, u32 timeOut)
1341 {
1342 u16 blStatus = 0;
1343 int status;
1344 unsigned long end;
1345
1346 dprintk(1, "\n");
1347 mutex_lock(&state->mutex);
1348 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1349 if (status < 0)
1350 goto error;
1351 status = write16(state, SIO_BL_CHAIN_ADDR__A, romOffset);
1352 if (status < 0)
1353 goto error;
1354 status = write16(state, SIO_BL_CHAIN_LEN__A, nrOfElements);
1355 if (status < 0)
1356 goto error;
1357 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1358 if (status < 0)
1359 goto error;
1360
1361 end = jiffies + msecs_to_jiffies(timeOut);
1362 do {
1363 msleep(1);
1364 status = read16(state, SIO_BL_STATUS__A, &blStatus);
1365 if (status < 0)
1366 goto error;
1367 } while ((blStatus == 0x1) &&
1368 ((time_is_after_jiffies(end))));
1369
1370 if (blStatus == 0x1) {
1371 printk(KERN_ERR "drxk: SIO not ready\n");
1372 status = -EINVAL;
1373 goto error2;
1374 }
1375 error:
1376 if (status < 0)
1377 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1378 error2:
1379 mutex_unlock(&state->mutex);
1380 return status;
1381 }
1382
1383
1384 static int DownloadMicrocode(struct drxk_state *state,
1385 const u8 pMCImage[], u32 Length)
1386 {
1387 const u8 *pSrc = pMCImage;
1388 u16 Flags;
1389 u16 Drain;
1390 u32 Address;
1391 u16 nBlocks;
1392 u16 BlockSize;
1393 u16 BlockCRC;
1394 u32 offset = 0;
1395 u32 i;
1396 int status = 0;
1397
1398 dprintk(1, "\n");
1399
1400 /* down the drain (we don care about MAGIC_WORD) */
1401 Drain = (pSrc[0] << 8) | pSrc[1];
1402 pSrc += sizeof(u16);
1403 offset += sizeof(u16);
1404 nBlocks = (pSrc[0] << 8) | pSrc[1];
1405 pSrc += sizeof(u16);
1406 offset += sizeof(u16);
1407
1408 for (i = 0; i < nBlocks; i += 1) {
1409 Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
1410 (pSrc[2] << 8) | pSrc[3];
1411 pSrc += sizeof(u32);
1412 offset += sizeof(u32);
1413
1414 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
1415 pSrc += sizeof(u16);
1416 offset += sizeof(u16);
1417
1418 Flags = (pSrc[0] << 8) | pSrc[1];
1419 pSrc += sizeof(u16);
1420 offset += sizeof(u16);
1421
1422 BlockCRC = (pSrc[0] << 8) | pSrc[1];
1423 pSrc += sizeof(u16);
1424 offset += sizeof(u16);
1425
1426 if (offset + BlockSize > Length) {
1427 printk(KERN_ERR "drxk: Firmware is corrupted.\n");
1428 return -EINVAL;
1429 }
1430
1431 status = write_block(state, Address, BlockSize, pSrc);
1432 if (status < 0) {
1433 printk(KERN_ERR "drxk: Error %d while loading firmware\n", status);
1434 break;
1435 }
1436 pSrc += BlockSize;
1437 offset += BlockSize;
1438 }
1439 return status;
1440 }
1441
1442 static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable)
1443 {
1444 int status;
1445 u16 data = 0;
1446 u16 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON;
1447 u16 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED;
1448 unsigned long end;
1449
1450 dprintk(1, "\n");
1451
1452 if (enable == false) {
1453 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
1454 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
1455 }
1456
1457 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1458 if (status >= 0 && data == desiredStatus) {
1459 /* tokenring already has correct status */
1460 return status;
1461 }
1462 /* Disable/enable dvbt tokenring bridge */
1463 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl);
1464
1465 end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
1466 do {
1467 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1468 if ((status >= 0 && data == desiredStatus) || time_is_after_jiffies(end))
1469 break;
1470 msleep(1);
1471 } while (1);
1472 if (data != desiredStatus) {
1473 printk(KERN_ERR "drxk: SIO not ready\n");
1474 return -EINVAL;
1475 }
1476 return status;
1477 }
1478
1479 static int MPEGTSStop(struct drxk_state *state)
1480 {
1481 int status = 0;
1482 u16 fecOcSncMode = 0;
1483 u16 fecOcIprMode = 0;
1484
1485 dprintk(1, "\n");
1486
1487 /* Gracefull shutdown (byte boundaries) */
1488 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1489 if (status < 0)
1490 goto error;
1491 fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
1492 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1493 if (status < 0)
1494 goto error;
1495
1496 /* Suppress MCLK during absence of data */
1497 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcIprMode);
1498 if (status < 0)
1499 goto error;
1500 fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
1501 status = write16(state, FEC_OC_IPR_MODE__A, fecOcIprMode);
1502
1503 error:
1504 if (status < 0)
1505 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1506
1507 return status;
1508 }
1509
1510 static int scu_command(struct drxk_state *state,
1511 u16 cmd, u8 parameterLen,
1512 u16 *parameter, u8 resultLen, u16 *result)
1513 {
1514 #if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15
1515 #error DRXK register mapping no longer compatible with this routine!
1516 #endif
1517 u16 curCmd = 0;
1518 int status = -EINVAL;
1519 unsigned long end;
1520 u8 buffer[34];
1521 int cnt = 0, ii;
1522 const char *p;
1523 char errname[30];
1524
1525 dprintk(1, "\n");
1526
1527 if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) ||
1528 ((resultLen > 0) && (result == NULL))) {
1529 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1530 return status;
1531 }
1532
1533 mutex_lock(&state->mutex);
1534
1535 /* assume that the command register is ready
1536 since it is checked afterwards */
1537 for (ii = parameterLen - 1; ii >= 0; ii -= 1) {
1538 buffer[cnt++] = (parameter[ii] & 0xFF);
1539 buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF);
1540 }
1541 buffer[cnt++] = (cmd & 0xFF);
1542 buffer[cnt++] = ((cmd >> 8) & 0xFF);
1543
1544 write_block(state, SCU_RAM_PARAM_0__A -
1545 (parameterLen - 1), cnt, buffer);
1546 /* Wait until SCU has processed command */
1547 end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
1548 do {
1549 msleep(1);
1550 status = read16(state, SCU_RAM_COMMAND__A, &curCmd);
1551 if (status < 0)
1552 goto error;
1553 } while (!(curCmd == DRX_SCU_READY) && (time_is_after_jiffies(end)));
1554 if (curCmd != DRX_SCU_READY) {
1555 printk(KERN_ERR "drxk: SCU not ready\n");
1556 status = -EIO;
1557 goto error2;
1558 }
1559 /* read results */
1560 if ((resultLen > 0) && (result != NULL)) {
1561 s16 err;
1562 int ii;
1563
1564 for (ii = resultLen - 1; ii >= 0; ii -= 1) {
1565 status = read16(state, SCU_RAM_PARAM_0__A - ii, &result[ii]);
1566 if (status < 0)
1567 goto error;
1568 }
1569
1570 /* Check if an error was reported by SCU */
1571 err = (s16)result[0];
1572 if (err >= 0)
1573 goto error;
1574
1575 /* check for the known error codes */
1576 switch (err) {
1577 case SCU_RESULT_UNKCMD:
1578 p = "SCU_RESULT_UNKCMD";
1579 break;
1580 case SCU_RESULT_UNKSTD:
1581 p = "SCU_RESULT_UNKSTD";
1582 break;
1583 case SCU_RESULT_SIZE:
1584 p = "SCU_RESULT_SIZE";
1585 break;
1586 case SCU_RESULT_INVPAR:
1587 p = "SCU_RESULT_INVPAR";
1588 break;
1589 default: /* Other negative values are errors */
1590 sprintf(errname, "ERROR: %d\n", err);
1591 p = errname;
1592 }
1593 printk(KERN_ERR "drxk: %s while sending cmd 0x%04x with params:", p, cmd);
1594 print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt);
1595 status = -EINVAL;
1596 goto error2;
1597 }
1598
1599 error:
1600 if (status < 0)
1601 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1602 error2:
1603 mutex_unlock(&state->mutex);
1604 return status;
1605 }
1606
1607 static int SetIqmAf(struct drxk_state *state, bool active)
1608 {
1609 u16 data = 0;
1610 int status;
1611
1612 dprintk(1, "\n");
1613
1614 /* Configure IQM */
1615 status = read16(state, IQM_AF_STDBY__A, &data);
1616 if (status < 0)
1617 goto error;
1618
1619 if (!active) {
1620 data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY
1621 | IQM_AF_STDBY_STDBY_AMP_STANDBY
1622 | IQM_AF_STDBY_STDBY_PD_STANDBY
1623 | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
1624 | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY);
1625 } else {
1626 data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY)
1627 & (~IQM_AF_STDBY_STDBY_AMP_STANDBY)
1628 & (~IQM_AF_STDBY_STDBY_PD_STANDBY)
1629 & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY)
1630 & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
1631 );
1632 }
1633 status = write16(state, IQM_AF_STDBY__A, data);
1634
1635 error:
1636 if (status < 0)
1637 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1638 return status;
1639 }
1640
1641 static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)
1642 {
1643 int status = 0;
1644 u16 sioCcPwdMode = 0;
1645
1646 dprintk(1, "\n");
1647
1648 /* Check arguments */
1649 if (mode == NULL)
1650 return -EINVAL;
1651
1652 switch (*mode) {
1653 case DRX_POWER_UP:
1654 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE;
1655 break;
1656 case DRXK_POWER_DOWN_OFDM:
1657 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OFDM;
1658 break;
1659 case DRXK_POWER_DOWN_CORE:
1660 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
1661 break;
1662 case DRXK_POWER_DOWN_PLL:
1663 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL;
1664 break;
1665 case DRX_POWER_DOWN:
1666 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC;
1667 break;
1668 default:
1669 /* Unknow sleep mode */
1670 return -EINVAL;
1671 }
1672
1673 /* If already in requested power mode, do nothing */
1674 if (state->m_currentPowerMode == *mode)
1675 return 0;
1676
1677 /* For next steps make sure to start from DRX_POWER_UP mode */
1678 if (state->m_currentPowerMode != DRX_POWER_UP) {
1679 status = PowerUpDevice(state);
1680 if (status < 0)
1681 goto error;
1682 status = DVBTEnableOFDMTokenRing(state, true);
1683 if (status < 0)
1684 goto error;
1685 }
1686
1687 if (*mode == DRX_POWER_UP) {
1688 /* Restore analog & pin configuartion */
1689 } else {
1690 /* Power down to requested mode */
1691 /* Backup some register settings */
1692 /* Set pins with possible pull-ups connected
1693 to them in input mode */
1694 /* Analog power down */
1695 /* ADC power down */
1696 /* Power down device */
1697 /* stop all comm_exec */
1698 /* Stop and power down previous standard */
1699 switch (state->m_OperationMode) {
1700 case OM_DVBT:
1701 status = MPEGTSStop(state);
1702 if (status < 0)
1703 goto error;
1704 status = PowerDownDVBT(state, false);
1705 if (status < 0)
1706 goto error;
1707 break;
1708 case OM_QAM_ITU_A:
1709 case OM_QAM_ITU_C:
1710 status = MPEGTSStop(state);
1711 if (status < 0)
1712 goto error;
1713 status = PowerDownQAM(state);
1714 if (status < 0)
1715 goto error;
1716 break;
1717 default:
1718 break;
1719 }
1720 status = DVBTEnableOFDMTokenRing(state, false);
1721 if (status < 0)
1722 goto error;
1723 status = write16(state, SIO_CC_PWD_MODE__A, sioCcPwdMode);
1724 if (status < 0)
1725 goto error;
1726 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1727 if (status < 0)
1728 goto error;
1729
1730 if (*mode != DRXK_POWER_DOWN_OFDM) {
1731 state->m_HICfgCtrl |=
1732 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1733 status = HI_CfgCommand(state);
1734 if (status < 0)
1735 goto error;
1736 }
1737 }
1738 state->m_currentPowerMode = *mode;
1739
1740 error:
1741 if (status < 0)
1742 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1743
1744 return status;
1745 }
1746
1747 static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode)
1748 {
1749 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
1750 u16 cmdResult = 0;
1751 u16 data = 0;
1752 int status;
1753
1754 dprintk(1, "\n");
1755
1756 status = read16(state, SCU_COMM_EXEC__A, &data);
1757 if (status < 0)
1758 goto error;
1759 if (data == SCU_COMM_EXEC_ACTIVE) {
1760 /* Send OFDM stop command */
1761 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
1762 if (status < 0)
1763 goto error;
1764 /* Send OFDM reset command */
1765 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
1766 if (status < 0)
1767 goto error;
1768 }
1769
1770 /* Reset datapath for OFDM, processors first */
1771 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1772 if (status < 0)
1773 goto error;
1774 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1775 if (status < 0)
1776 goto error;
1777 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1778 if (status < 0)
1779 goto error;
1780
1781 /* powerdown AFE */
1782 status = SetIqmAf(state, false);
1783 if (status < 0)
1784 goto error;
1785
1786 /* powerdown to OFDM mode */
1787 if (setPowerMode) {
1788 status = CtrlPowerMode(state, &powerMode);
1789 if (status < 0)
1790 goto error;
1791 }
1792 error:
1793 if (status < 0)
1794 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1795 return status;
1796 }
1797
1798 static int SetOperationMode(struct drxk_state *state,
1799 enum OperationMode oMode)
1800 {
1801 int status = 0;
1802
1803 dprintk(1, "\n");
1804 /*
1805 Stop and power down previous standard
1806 TODO investigate total power down instead of partial
1807 power down depending on "previous" standard.
1808 */
1809
1810 /* disable HW lock indicator */
1811 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1812 if (status < 0)
1813 goto error;
1814
1815 /* Device is already at the required mode */
1816 if (state->m_OperationMode == oMode)
1817 return 0;
1818
1819 switch (state->m_OperationMode) {
1820 /* OM_NONE was added for start up */
1821 case OM_NONE:
1822 break;
1823 case OM_DVBT:
1824 status = MPEGTSStop(state);
1825 if (status < 0)
1826 goto error;
1827 status = PowerDownDVBT(state, true);
1828 if (status < 0)
1829 goto error;
1830 state->m_OperationMode = OM_NONE;
1831 break;
1832 case OM_QAM_ITU_A: /* fallthrough */
1833 case OM_QAM_ITU_C:
1834 status = MPEGTSStop(state);
1835 if (status < 0)
1836 goto error;
1837 status = PowerDownQAM(state);
1838 if (status < 0)
1839 goto error;
1840 state->m_OperationMode = OM_NONE;
1841 break;
1842 case OM_QAM_ITU_B:
1843 default:
1844 status = -EINVAL;
1845 goto error;
1846 }
1847
1848 /*
1849 Power up new standard
1850 */
1851 switch (oMode) {
1852 case OM_DVBT:
1853 dprintk(1, ": DVB-T\n");
1854 state->m_OperationMode = oMode;
1855 status = SetDVBTStandard(state, oMode);
1856 if (status < 0)
1857 goto error;
1858 break;
1859 case OM_QAM_ITU_A: /* fallthrough */
1860 case OM_QAM_ITU_C:
1861 dprintk(1, ": DVB-C Annex %c\n",
1862 (state->m_OperationMode == OM_QAM_ITU_A) ? 'A' : 'C');
1863 state->m_OperationMode = oMode;
1864 status = SetQAMStandard(state, oMode);
1865 if (status < 0)
1866 goto error;
1867 break;
1868 case OM_QAM_ITU_B:
1869 default:
1870 status = -EINVAL;
1871 }
1872 error:
1873 if (status < 0)
1874 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1875 return status;
1876 }
1877
1878 static int Start(struct drxk_state *state, s32 offsetFreq,
1879 s32 IntermediateFrequency)
1880 {
1881 int status = -EINVAL;
1882
1883 u16 IFreqkHz;
1884 s32 OffsetkHz = offsetFreq / 1000;
1885
1886 dprintk(1, "\n");
1887 if (state->m_DrxkState != DRXK_STOPPED &&
1888 state->m_DrxkState != DRXK_DTV_STARTED)
1889 goto error;
1890
1891 state->m_bMirrorFreqSpect = (state->props.inversion == INVERSION_ON);
1892
1893 if (IntermediateFrequency < 0) {
1894 state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect;
1895 IntermediateFrequency = -IntermediateFrequency;
1896 }
1897
1898 switch (state->m_OperationMode) {
1899 case OM_QAM_ITU_A:
1900 case OM_QAM_ITU_C:
1901 IFreqkHz = (IntermediateFrequency / 1000);
1902 status = SetQAM(state, IFreqkHz, OffsetkHz);
1903 if (status < 0)
1904 goto error;
1905 state->m_DrxkState = DRXK_DTV_STARTED;
1906 break;
1907 case OM_DVBT:
1908 IFreqkHz = (IntermediateFrequency / 1000);
1909 status = MPEGTSStop(state);
1910 if (status < 0)
1911 goto error;
1912 status = SetDVBT(state, IFreqkHz, OffsetkHz);
1913 if (status < 0)
1914 goto error;
1915 status = DVBTStart(state);
1916 if (status < 0)
1917 goto error;
1918 state->m_DrxkState = DRXK_DTV_STARTED;
1919 break;
1920 default:
1921 break;
1922 }
1923 error:
1924 if (status < 0)
1925 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1926 return status;
1927 }
1928
1929 static int ShutDown(struct drxk_state *state)
1930 {
1931 dprintk(1, "\n");
1932
1933 MPEGTSStop(state);
1934 return 0;
1935 }
1936
1937 static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus,
1938 u32 Time)
1939 {
1940 int status = -EINVAL;
1941
1942 dprintk(1, "\n");
1943
1944 if (pLockStatus == NULL)
1945 goto error;
1946
1947 *pLockStatus = NOT_LOCKED;
1948
1949 /* define the SCU command code */
1950 switch (state->m_OperationMode) {
1951 case OM_QAM_ITU_A:
1952 case OM_QAM_ITU_B:
1953 case OM_QAM_ITU_C:
1954 status = GetQAMLockStatus(state, pLockStatus);
1955 break;
1956 case OM_DVBT:
1957 status = GetDVBTLockStatus(state, pLockStatus);
1958 break;
1959 default:
1960 break;
1961 }
1962 error:
1963 if (status < 0)
1964 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1965 return status;
1966 }
1967
1968 static int MPEGTSStart(struct drxk_state *state)
1969 {
1970 int status;
1971
1972 u16 fecOcSncMode = 0;
1973
1974 /* Allow OC to sync again */
1975 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1976 if (status < 0)
1977 goto error;
1978 fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
1979 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1980 if (status < 0)
1981 goto error;
1982 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
1983 error:
1984 if (status < 0)
1985 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1986 return status;
1987 }
1988
1989 static int MPEGTSDtoInit(struct drxk_state *state)
1990 {
1991 int status;
1992
1993 dprintk(1, "\n");
1994
1995 /* Rate integration settings */
1996 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
1997 if (status < 0)
1998 goto error;
1999 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
2000 if (status < 0)
2001 goto error;
2002 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
2003 if (status < 0)
2004 goto error;
2005 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
2006 if (status < 0)
2007 goto error;
2008 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
2009 if (status < 0)
2010 goto error;
2011 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
2012 if (status < 0)
2013 goto error;
2014 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
2015 if (status < 0)
2016 goto error;
2017 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
2018 if (status < 0)
2019 goto error;
2020
2021 /* Additional configuration */
2022 status = write16(state, FEC_OC_OCR_INVERT__A, 0);
2023 if (status < 0)
2024 goto error;
2025 status = write16(state, FEC_OC_SNC_LWM__A, 2);
2026 if (status < 0)
2027 goto error;
2028 status = write16(state, FEC_OC_SNC_HWM__A, 12);
2029 error:
2030 if (status < 0)
2031 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2032
2033 return status;
2034 }
2035
2036 static int MPEGTSDtoSetup(struct drxk_state *state,
2037 enum OperationMode oMode)
2038 {
2039 int status;
2040
2041 u16 fecOcRegMode = 0; /* FEC_OC_MODE register value */
2042 u16 fecOcRegIprMode = 0; /* FEC_OC_IPR_MODE register value */
2043 u16 fecOcDtoMode = 0; /* FEC_OC_IPR_INVERT register value */
2044 u16 fecOcFctMode = 0; /* FEC_OC_IPR_INVERT register value */
2045 u16 fecOcDtoPeriod = 2; /* FEC_OC_IPR_INVERT register value */
2046 u16 fecOcDtoBurstLen = 188; /* FEC_OC_IPR_INVERT register value */
2047 u32 fecOcRcnCtlRate = 0; /* FEC_OC_IPR_INVERT register value */
2048 u16 fecOcTmdMode = 0;
2049 u16 fecOcTmdIntUpdRate = 0;
2050 u32 maxBitRate = 0;
2051 bool staticCLK = false;
2052
2053 dprintk(1, "\n");
2054
2055 /* Check insertion of the Reed-Solomon parity bytes */
2056 status = read16(state, FEC_OC_MODE__A, &fecOcRegMode);
2057 if (status < 0)
2058 goto error;
2059 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcRegIprMode);
2060 if (status < 0)
2061 goto error;
2062 fecOcRegMode &= (~FEC_OC_MODE_PARITY__M);
2063 fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
2064 if (state->m_insertRSByte == true) {
2065 /* enable parity symbol forward */
2066 fecOcRegMode |= FEC_OC_MODE_PARITY__M;
2067 /* MVAL disable during parity bytes */
2068 fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
2069 /* TS burst length to 204 */
2070 fecOcDtoBurstLen = 204;
2071 }
2072
2073 /* Check serial or parrallel output */
2074 fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
2075 if (state->m_enableParallel == false) {
2076 /* MPEG data output is serial -> set ipr_mode[0] */
2077 fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M;
2078 }
2079
2080 switch (oMode) {
2081 case OM_DVBT:
2082 maxBitRate = state->m_DVBTBitrate;
2083 fecOcTmdMode = 3;
2084 fecOcRcnCtlRate = 0xC00000;
2085 staticCLK = state->m_DVBTStaticCLK;
2086 break;
2087 case OM_QAM_ITU_A: /* fallthrough */
2088 case OM_QAM_ITU_C:
2089 fecOcTmdMode = 0x0004;
2090 fecOcRcnCtlRate = 0xD2B4EE; /* good for >63 Mb/s */
2091 maxBitRate = state->m_DVBCBitrate;
2092 staticCLK = state->m_DVBCStaticCLK;
2093 break;
2094 default:
2095 status = -EINVAL;
2096 } /* switch (standard) */
2097 if (status < 0)
2098 goto error;
2099
2100 /* Configure DTO's */
2101 if (staticCLK) {
2102 u32 bitRate = 0;
2103
2104 /* Rational DTO for MCLK source (static MCLK rate),
2105 Dynamic DTO for optimal grouping
2106 (avoid intra-packet gaps),
2107 DTO offset enable to sync TS burst with MSTRT */
2108 fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M |
2109 FEC_OC_DTO_MODE_OFFSET_ENABLE__M);
2110 fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M |
2111 FEC_OC_FCT_MODE_VIRT_ENA__M);
2112
2113 /* Check user defined bitrate */
2114 bitRate = maxBitRate;
2115 if (bitRate > 75900000UL) { /* max is 75.9 Mb/s */
2116 bitRate = 75900000UL;
2117 }
2118 /* Rational DTO period:
2119 dto_period = (Fsys / bitrate) - 2
2120
2121 Result should be floored,
2122 to make sure >= requested bitrate
2123 */
2124 fecOcDtoPeriod = (u16) (((state->m_sysClockFreq)
2125 * 1000) / bitRate);
2126 if (fecOcDtoPeriod <= 2)
2127 fecOcDtoPeriod = 0;
2128 else
2129 fecOcDtoPeriod -= 2;
2130 fecOcTmdIntUpdRate = 8;
2131 } else {
2132 /* (commonAttr->staticCLK == false) => dynamic mode */
2133 fecOcDtoMode = FEC_OC_DTO_MODE_DYNAMIC__M;
2134 fecOcFctMode = FEC_OC_FCT_MODE__PRE;
2135 fecOcTmdIntUpdRate = 5;
2136 }
2137
2138 /* Write appropriate registers with requested configuration */
2139 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fecOcDtoBurstLen);
2140 if (status < 0)
2141 goto error;
2142 status = write16(state, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod);
2143 if (status < 0)
2144 goto error;
2145 status = write16(state, FEC_OC_DTO_MODE__A, fecOcDtoMode);
2146 if (status < 0)
2147 goto error;
2148 status = write16(state, FEC_OC_FCT_MODE__A, fecOcFctMode);
2149 if (status < 0)
2150 goto error;
2151 status = write16(state, FEC_OC_MODE__A, fecOcRegMode);
2152 if (status < 0)
2153 goto error;
2154 status = write16(state, FEC_OC_IPR_MODE__A, fecOcRegIprMode);
2155 if (status < 0)
2156 goto error;
2157
2158 /* Rate integration settings */
2159 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fecOcRcnCtlRate);
2160 if (status < 0)
2161 goto error;
2162 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, fecOcTmdIntUpdRate);
2163 if (status < 0)
2164 goto error;
2165 status = write16(state, FEC_OC_TMD_MODE__A, fecOcTmdMode);
2166 error:
2167 if (status < 0)
2168 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2169 return status;
2170 }
2171
2172 static int MPEGTSConfigurePolarity(struct drxk_state *state)
2173 {
2174 u16 fecOcRegIprInvert = 0;
2175
2176 /* Data mask for the output data byte */
2177 u16 InvertDataMask =
2178 FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2179 FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2180 FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2181 FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
2182
2183 dprintk(1, "\n");
2184
2185 /* Control selective inversion of output bits */
2186 fecOcRegIprInvert &= (~(InvertDataMask));
2187 if (state->m_invertDATA == true)
2188 fecOcRegIprInvert |= InvertDataMask;
2189 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2190 if (state->m_invertERR == true)
2191 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M;
2192 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
2193 if (state->m_invertSTR == true)
2194 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M;
2195 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
2196 if (state->m_invertVAL == true)
2197 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M;
2198 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
2199 if (state->m_invertCLK == true)
2200 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M;
2201
2202 return write16(state, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert);
2203 }
2204
2205 #define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
2206
2207 static int SetAgcRf(struct drxk_state *state,
2208 struct SCfgAgc *pAgcCfg, bool isDTV)
2209 {
2210 int status = -EINVAL;
2211 u16 data = 0;
2212 struct SCfgAgc *pIfAgcSettings;
2213
2214 dprintk(1, "\n");
2215
2216 if (pAgcCfg == NULL)
2217 goto error;
2218
2219 switch (pAgcCfg->ctrlMode) {
2220 case DRXK_AGC_CTRL_AUTO:
2221 /* Enable RF AGC DAC */
2222 status = read16(state, IQM_AF_STDBY__A, &data);
2223 if (status < 0)
2224 goto error;
2225 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2226 status = write16(state, IQM_AF_STDBY__A, data);
2227 if (status < 0)
2228 goto error;
2229 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2230 if (status < 0)
2231 goto error;
2232
2233 /* Enable SCU RF AGC loop */
2234 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2235
2236 /* Polarity */
2237 if (state->m_RfAgcPol)
2238 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2239 else
2240 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2241 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2242 if (status < 0)
2243 goto error;
2244
2245 /* Set speed (using complementary reduction value) */
2246 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2247 if (status < 0)
2248 goto error;
2249
2250 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
2251 data |= (~(pAgcCfg->speed <<
2252 SCU_RAM_AGC_KI_RED_RAGC_RED__B)
2253 & SCU_RAM_AGC_KI_RED_RAGC_RED__M);
2254
2255 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2256 if (status < 0)
2257 goto error;
2258
2259 if (IsDVBT(state))
2260 pIfAgcSettings = &state->m_dvbtIfAgcCfg;
2261 else if (IsQAM(state))
2262 pIfAgcSettings = &state->m_qamIfAgcCfg;
2263 else
2264 pIfAgcSettings = &state->m_atvIfAgcCfg;
2265 if (pIfAgcSettings == NULL) {
2266 status = -EINVAL;
2267 goto error;
2268 }
2269
2270 /* Set TOP, only if IF-AGC is in AUTO mode */
2271 if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO)
2272 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->top);
2273 if (status < 0)
2274 goto error;
2275
2276 /* Cut-Off current */
2277 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, pAgcCfg->cutOffCurrent);
2278 if (status < 0)
2279 goto error;
2280
2281 /* Max. output level */
2282 status = write16(state, SCU_RAM_AGC_RF_MAX__A, pAgcCfg->maxOutputLevel);
2283 if (status < 0)
2284 goto error;
2285
2286 break;
2287
2288 case DRXK_AGC_CTRL_USER:
2289 /* Enable RF AGC DAC */
2290 status = read16(state, IQM_AF_STDBY__A, &data);
2291 if (status < 0)
2292 goto error;
2293 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2294 status = write16(state, IQM_AF_STDBY__A, data);
2295 if (status < 0)
2296 goto error;
2297
2298 /* Disable SCU RF AGC loop */
2299 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2300 if (status < 0)
2301 goto error;
2302 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2303 if (state->m_RfAgcPol)
2304 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2305 else
2306 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2307 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2308 if (status < 0)
2309 goto error;
2310
2311 /* SCU c.o.c. to 0, enabling full control range */
2312 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2313 if (status < 0)
2314 goto error;
2315
2316 /* Write value to output pin */
2317 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, pAgcCfg->outputLevel);
2318 if (status < 0)
2319 goto error;
2320 break;
2321
2322 case DRXK_AGC_CTRL_OFF:
2323 /* Disable RF AGC DAC */
2324 status = read16(state, IQM_AF_STDBY__A, &data);
2325 if (status < 0)
2326 goto error;
2327 data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2328 status = write16(state, IQM_AF_STDBY__A, data);
2329 if (status < 0)
2330 goto error;
2331
2332 /* Disable SCU RF AGC loop */
2333 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2334 if (status < 0)
2335 goto error;
2336 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2337 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2338 if (status < 0)
2339 goto error;
2340 break;
2341
2342 default:
2343 status = -EINVAL;
2344
2345 }
2346 error:
2347 if (status < 0)
2348 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2349 return status;
2350 }
2351
2352 #define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000
2353
2354 static int SetAgcIf(struct drxk_state *state,
2355 struct SCfgAgc *pAgcCfg, bool isDTV)
2356 {
2357 u16 data = 0;
2358 int status = 0;
2359 struct SCfgAgc *pRfAgcSettings;
2360
2361 dprintk(1, "\n");
2362
2363 switch (pAgcCfg->ctrlMode) {
2364 case DRXK_AGC_CTRL_AUTO:
2365
2366 /* Enable IF AGC DAC */
2367 status = read16(state, IQM_AF_STDBY__A, &data);
2368 if (status < 0)
2369 goto error;
2370 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2371 status = write16(state, IQM_AF_STDBY__A, data);
2372 if (status < 0)
2373 goto error;
2374
2375 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2376 if (status < 0)
2377 goto error;
2378
2379 /* Enable SCU IF AGC loop */
2380 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2381
2382 /* Polarity */
2383 if (state->m_IfAgcPol)
2384 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2385 else
2386 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2387 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2388 if (status < 0)
2389 goto error;
2390
2391 /* Set speed (using complementary reduction value) */
2392 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2393 if (status < 0)
2394 goto error;
2395 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
2396 data |= (~(pAgcCfg->speed <<
2397 SCU_RAM_AGC_KI_RED_IAGC_RED__B)
2398 & SCU_RAM_AGC_KI_RED_IAGC_RED__M);
2399
2400 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2401 if (status < 0)
2402 goto error;
2403
2404 if (IsQAM(state))
2405 pRfAgcSettings = &state->m_qamRfAgcCfg;
2406 else
2407 pRfAgcSettings = &state->m_atvRfAgcCfg;
2408 if (pRfAgcSettings == NULL)
2409 return -1;
2410 /* Restore TOP */
2411 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pRfAgcSettings->top);
2412 if (status < 0)
2413 goto error;
2414 break;
2415
2416 case DRXK_AGC_CTRL_USER:
2417
2418 /* Enable IF AGC DAC */
2419 status = read16(state, IQM_AF_STDBY__A, &data);
2420 if (status < 0)
2421 goto error;
2422 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2423 status = write16(state, IQM_AF_STDBY__A, data);
2424 if (status < 0)
2425 goto error;
2426
2427 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2428 if (status < 0)
2429 goto error;
2430
2431 /* Disable SCU IF AGC loop */
2432 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2433
2434 /* Polarity */
2435 if (state->m_IfAgcPol)
2436 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2437 else
2438 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2439 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2440 if (status < 0)
2441 goto error;
2442
2443 /* Write value to output pin */
2444 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->outputLevel);
2445 if (status < 0)
2446 goto error;
2447 break;
2448
2449 case DRXK_AGC_CTRL_OFF:
2450
2451 /* Disable If AGC DAC */
2452 status = read16(state, IQM_AF_STDBY__A, &data);
2453 if (status < 0)
2454 goto error;
2455 data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2456 status = write16(state, IQM_AF_STDBY__A, data);
2457 if (status < 0)
2458 goto error;
2459
2460 /* Disable SCU IF AGC loop */
2461 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2462 if (status < 0)
2463 goto error;
2464 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2465 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2466 if (status < 0)
2467 goto error;
2468 break;
2469 } /* switch (agcSettingsIf->ctrlMode) */
2470
2471 /* always set the top to support
2472 configurations without if-loop */
2473 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcCfg->top);
2474 error:
2475 if (status < 0)
2476 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2477 return status;
2478 }
2479
2480 static int ReadIFAgc(struct drxk_state *state, u32 *pValue)
2481 {
2482 u16 agcDacLvl;
2483 int status;
2484 u16 Level = 0;
2485
2486 dprintk(1, "\n");
2487
2488 status = read16(state, IQM_AF_AGC_IF__A, &agcDacLvl);
2489 if (status < 0) {
2490 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2491 return status;
2492 }
2493
2494 *pValue = 0;
2495
2496 if (agcDacLvl > DRXK_AGC_DAC_OFFSET)
2497 Level = agcDacLvl - DRXK_AGC_DAC_OFFSET;
2498 if (Level < 14000)
2499 *pValue = (14000 - Level) / 4;
2500 else
2501 *pValue = 0;
2502
2503 return status;
2504 }
2505
2506 static int GetQAMSignalToNoise(struct drxk_state *state,
2507 s32 *pSignalToNoise)
2508 {
2509 int status = 0;
2510 u16 qamSlErrPower = 0; /* accum. error between
2511 raw and sliced symbols */
2512 u32 qamSlSigPower = 0; /* used for MER, depends of
2513 QAM modulation */
2514 u32 qamSlMer = 0; /* QAM MER */
2515
2516 dprintk(1, "\n");
2517
2518 /* MER calculation */
2519
2520 /* get the register value needed for MER */
2521 status = read16(state, QAM_SL_ERR_POWER__A, &qamSlErrPower);
2522 if (status < 0) {
2523 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2524 return -EINVAL;
2525 }
2526
2527 switch (state->props.modulation) {
2528 case QAM_16:
2529 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
2530 break;
2531 case QAM_32:
2532 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM32 << 2;
2533 break;
2534 case QAM_64:
2535 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM64 << 2;
2536 break;
2537 case QAM_128:
2538 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM128 << 2;
2539 break;
2540 default:
2541 case QAM_256:
2542 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM256 << 2;
2543 break;
2544 }
2545
2546 if (qamSlErrPower > 0) {
2547 qamSlMer = Log10Times100(qamSlSigPower) -
2548 Log10Times100((u32) qamSlErrPower);
2549 }
2550 *pSignalToNoise = qamSlMer;
2551
2552 return status;
2553 }
2554
2555 static int GetDVBTSignalToNoise(struct drxk_state *state,
2556 s32 *pSignalToNoise)
2557 {
2558 int status;
2559 u16 regData = 0;
2560 u32 EqRegTdSqrErrI = 0;
2561 u32 EqRegTdSqrErrQ = 0;
2562 u16 EqRegTdSqrErrExp = 0;
2563 u16 EqRegTdTpsPwrOfs = 0;
2564 u16 EqRegTdReqSmbCnt = 0;
2565 u32 tpsCnt = 0;
2566 u32 SqrErrIQ = 0;
2567 u32 a = 0;
2568 u32 b = 0;
2569 u32 c = 0;
2570 u32 iMER = 0;
2571 u16 transmissionParams = 0;
2572
2573 dprintk(1, "\n");
2574
2575 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &EqRegTdTpsPwrOfs);
2576 if (status < 0)
2577 goto error;
2578 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &EqRegTdReqSmbCnt);
2579 if (status < 0)
2580 goto error;
2581 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &EqRegTdSqrErrExp);
2582 if (status < 0)
2583 goto error;
2584 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, &regData);
2585 if (status < 0)
2586 goto error;
2587 /* Extend SQR_ERR_I operational range */
2588 EqRegTdSqrErrI = (u32) regData;
2589 if ((EqRegTdSqrErrExp > 11) &&
2590 (EqRegTdSqrErrI < 0x00000FFFUL)) {
2591 EqRegTdSqrErrI += 0x00010000UL;
2592 }
2593 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, &regData);
2594 if (status < 0)
2595 goto error;
2596 /* Extend SQR_ERR_Q operational range */
2597 EqRegTdSqrErrQ = (u32) regData;
2598 if ((EqRegTdSqrErrExp > 11) &&
2599 (EqRegTdSqrErrQ < 0x00000FFFUL))
2600 EqRegTdSqrErrQ += 0x00010000UL;
2601
2602 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmissionParams);
2603 if (status < 0)
2604 goto error;
2605
2606 /* Check input data for MER */
2607
2608 /* MER calculation (in 0.1 dB) without math.h */
2609 if ((EqRegTdTpsPwrOfs == 0) || (EqRegTdReqSmbCnt == 0))
2610 iMER = 0;
2611 else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) == 0) {
2612 /* No error at all, this must be the HW reset value
2613 * Apparently no first measurement yet
2614 * Set MER to 0.0 */
2615 iMER = 0;
2616 } else {
2617 SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) <<
2618 EqRegTdSqrErrExp;
2619 if ((transmissionParams &
2620 OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
2621 == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
2622 tpsCnt = 17;
2623 else
2624 tpsCnt = 68;
2625
2626 /* IMER = 100 * log10 (x)
2627 where x = (EqRegTdTpsPwrOfs^2 *
2628 EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ
2629
2630 => IMER = a + b -c
2631 where a = 100 * log10 (EqRegTdTpsPwrOfs^2)
2632 b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt)
2633 c = 100 * log10 (SqrErrIQ)
2634 */
2635
2636 /* log(x) x = 9bits * 9bits->18 bits */
2637 a = Log10Times100(EqRegTdTpsPwrOfs *
2638 EqRegTdTpsPwrOfs);
2639 /* log(x) x = 16bits * 7bits->23 bits */
2640 b = Log10Times100(EqRegTdReqSmbCnt * tpsCnt);
2641 /* log(x) x = (16bits + 16bits) << 15 ->32 bits */
2642 c = Log10Times100(SqrErrIQ);
2643
2644 iMER = a + b;
2645 /* No negative MER, clip to zero */
2646 if (iMER > c)
2647 iMER -= c;
2648 else
2649 iMER = 0;
2650 }
2651 *pSignalToNoise = iMER;
2652
2653 error:
2654 if (status < 0)
2655 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2656 return status;
2657 }
2658
2659 static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise)
2660 {
2661 dprintk(1, "\n");
2662
2663 *pSignalToNoise = 0;
2664 switch (state->m_OperationMode) {
2665 case OM_DVBT:
2666 return GetDVBTSignalToNoise(state, pSignalToNoise);
2667 case OM_QAM_ITU_A:
2668 case OM_QAM_ITU_C:
2669 return GetQAMSignalToNoise(state, pSignalToNoise);
2670 default:
2671 break;
2672 }
2673 return 0;
2674 }
2675
2676 #if 0
2677 static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality)
2678 {
2679 /* SNR Values for quasi errorfree reception rom Nordig 2.2 */
2680 int status = 0;
2681
2682 dprintk(1, "\n");
2683
2684 static s32 QE_SN[] = {
2685 51, /* QPSK 1/2 */
2686 69, /* QPSK 2/3 */
2687 79, /* QPSK 3/4 */
2688 89, /* QPSK 5/6 */
2689 97, /* QPSK 7/8 */
2690 108, /* 16-QAM 1/2 */
2691 131, /* 16-QAM 2/3 */
2692 146, /* 16-QAM 3/4 */
2693 156, /* 16-QAM 5/6 */
2694 160, /* 16-QAM 7/8 */
2695 165, /* 64-QAM 1/2 */
2696 187, /* 64-QAM 2/3 */
2697 202, /* 64-QAM 3/4 */
2698 216, /* 64-QAM 5/6 */
2699 225, /* 64-QAM 7/8 */
2700 };
2701
2702 *pQuality = 0;
2703
2704 do {
2705 s32 SignalToNoise = 0;
2706 u16 Constellation = 0;
2707 u16 CodeRate = 0;
2708 u32 SignalToNoiseRel;
2709 u32 BERQuality;
2710
2711 status = GetDVBTSignalToNoise(state, &SignalToNoise);
2712 if (status < 0)
2713 break;
2714 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, &Constellation);
2715 if (status < 0)
2716 break;
2717 Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
2718
2719 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, &CodeRate);
2720 if (status < 0)
2721 break;
2722 CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
2723
2724 if (Constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM ||
2725 CodeRate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8)
2726 break;
2727 SignalToNoiseRel = SignalToNoise -
2728 QE_SN[Constellation * 5 + CodeRate];
2729 BERQuality = 100;
2730
2731 if (SignalToNoiseRel < -70)
2732 *pQuality = 0;
2733 else if (SignalToNoiseRel < 30)
2734 *pQuality = ((SignalToNoiseRel + 70) *
2735 BERQuality) / 100;
2736 else
2737 *pQuality = BERQuality;
2738 } while (0);
2739 return 0;
2740 };
2741
2742 static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality)
2743 {
2744 int status = 0;
2745 *pQuality = 0;
2746
2747 dprintk(1, "\n");
2748
2749 do {
2750 u32 SignalToNoise = 0;
2751 u32 BERQuality = 100;
2752 u32 SignalToNoiseRel = 0;
2753
2754 status = GetQAMSignalToNoise(state, &SignalToNoise);
2755 if (status < 0)
2756 break;
2757
2758 switch (state->props.modulation) {
2759 case QAM_16:
2760 SignalToNoiseRel = SignalToNoise - 200;
2761 break;
2762 case QAM_32:
2763 SignalToNoiseRel = SignalToNoise - 230;
2764 break; /* Not in NorDig */
2765 case QAM_64:
2766 SignalToNoiseRel = SignalToNoise - 260;
2767 break;
2768 case QAM_128:
2769 SignalToNoiseRel = SignalToNoise - 290;
2770 break;
2771 default:
2772 case QAM_256:
2773 SignalToNoiseRel = SignalToNoise - 320;
2774 break;
2775 }
2776
2777 if (SignalToNoiseRel < -70)
2778 *pQuality = 0;
2779 else if (SignalToNoiseRel < 30)
2780 *pQuality = ((SignalToNoiseRel + 70) *
2781 BERQuality) / 100;
2782 else
2783 *pQuality = BERQuality;
2784 } while (0);
2785
2786 return status;
2787 }
2788
2789 static int GetQuality(struct drxk_state *state, s32 *pQuality)
2790 {
2791 dprintk(1, "\n");
2792
2793 switch (state->m_OperationMode) {
2794 case OM_DVBT:
2795 return GetDVBTQuality(state, pQuality);
2796 case OM_QAM_ITU_A:
2797 return GetDVBCQuality(state, pQuality);
2798 default:
2799 break;
2800 }
2801
2802 return 0;
2803 }
2804 #endif
2805
2806 /* Free data ram in SIO HI */
2807 #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2808 #define SIO_HI_RA_RAM_USR_END__A 0x420060
2809
2810 #define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2811 #define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2812 #define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2813 #define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2814
2815 #define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F)
2816 #define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F)
2817 #define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF)
2818
2819 static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge)
2820 {
2821 int status = -EINVAL;
2822
2823 dprintk(1, "\n");
2824
2825 if (state->m_DrxkState == DRXK_UNINITIALIZED)
2826 goto error;
2827 if (state->m_DrxkState == DRXK_POWERED_DOWN)
2828 goto error;
2829
2830 if (state->no_i2c_bridge)
2831 return 0;
2832
2833 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
2834 if (status < 0)
2835 goto error;
2836 if (bEnableBridge) {
2837 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
2838 if (status < 0)
2839 goto error;
2840 } else {
2841 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
2842 if (status < 0)
2843 goto error;
2844 }
2845
2846 status = HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, 0);
2847
2848 error:
2849 if (status < 0)
2850 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2851 return status;
2852 }
2853
2854 static int SetPreSaw(struct drxk_state *state,
2855 struct SCfgPreSaw *pPreSawCfg)
2856 {
2857 int status = -EINVAL;
2858
2859 dprintk(1, "\n");
2860
2861 if ((pPreSawCfg == NULL)
2862 || (pPreSawCfg->reference > IQM_AF_PDREF__M))
2863 goto error;
2864
2865 status = write16(state, IQM_AF_PDREF__A, pPreSawCfg->reference);
2866 error:
2867 if (status < 0)
2868 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2869 return status;
2870 }
2871
2872 static int BLDirectCmd(struct drxk_state *state, u32 targetAddr,
2873 u16 romOffset, u16 nrOfElements, u32 timeOut)
2874 {
2875 u16 blStatus = 0;
2876 u16 offset = (u16) ((targetAddr >> 0) & 0x00FFFF);
2877 u16 blockbank = (u16) ((targetAddr >> 16) & 0x000FFF);
2878 int status;
2879 unsigned long end;
2880
2881 dprintk(1, "\n");
2882
2883 mutex_lock(&state->mutex);
2884 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2885 if (status < 0)
2886 goto error;
2887 status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2888 if (status < 0)
2889 goto error;
2890 status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2891 if (status < 0)
2892 goto error;
2893 status = write16(state, SIO_BL_SRC_ADDR__A, romOffset);
2894 if (status < 0)
2895 goto error;
2896 status = write16(state, SIO_BL_SRC_LEN__A, nrOfElements);
2897 if (status < 0)
2898 goto error;
2899 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2900 if (status < 0)
2901 goto error;
2902
2903 end = jiffies + msecs_to_jiffies(timeOut);
2904 do {
2905 status = read16(state, SIO_BL_STATUS__A, &blStatus);
2906 if (status < 0)
2907 goto error;
2908 } while ((blStatus == 0x1) && time_is_after_jiffies(end));
2909 if (blStatus == 0x1) {
2910 printk(KERN_ERR "drxk: SIO not ready\n");
2911 status = -EINVAL;
2912 goto error2;
2913 }
2914 error:
2915 if (status < 0)
2916 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2917 error2:
2918 mutex_unlock(&state->mutex);
2919 return status;
2920
2921 }
2922
2923 static int ADCSyncMeasurement(struct drxk_state *state, u16 *count)
2924 {
2925 u16 data = 0;
2926 int status;
2927
2928 dprintk(1, "\n");
2929
2930 /* Start measurement */
2931 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2932 if (status < 0)
2933 goto error;
2934 status = write16(state, IQM_AF_START_LOCK__A, 1);
2935 if (status < 0)
2936 goto error;
2937
2938 *count = 0;
2939 status = read16(state, IQM_AF_PHASE0__A, &data);
2940 if (status < 0)
2941 goto error;
2942 if (data == 127)
2943 *count = *count + 1;
2944 status = read16(state, IQM_AF_PHASE1__A, &data);
2945 if (status < 0)
2946 goto error;
2947 if (data == 127)
2948 *count = *count + 1;
2949 status = read16(state, IQM_AF_PHASE2__A, &data);
2950 if (status < 0)
2951 goto error;
2952 if (data == 127)
2953 *count = *count + 1;
2954
2955 error:
2956 if (status < 0)
2957 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2958 return status;
2959 }
2960
2961 static int ADCSynchronization(struct drxk_state *state)
2962 {
2963 u16 count = 0;
2964 int status;
2965
2966 dprintk(1, "\n");
2967
2968 status = ADCSyncMeasurement(state, &count);
2969 if (status < 0)
2970 goto error;
2971
2972 if (count == 1) {
2973 /* Try sampling on a diffrent edge */
2974 u16 clkNeg = 0;
2975
2976 status = read16(state, IQM_AF_CLKNEG__A, &clkNeg);
2977 if (status < 0)
2978 goto error;
2979 if ((clkNeg | IQM_AF_CLKNEG_CLKNEGDATA__M) ==
2980 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) {
2981 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2982 clkNeg |=
2983 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG;
2984 } else {
2985 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2986 clkNeg |=
2987 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
2988 }
2989 status = write16(state, IQM_AF_CLKNEG__A, clkNeg);
2990 if (status < 0)
2991 goto error;
2992 status = ADCSyncMeasurement(state, &count);
2993 if (status < 0)
2994 goto error;
2995 }
2996
2997 if (count < 2)
2998 status = -EINVAL;
2999 error:
3000 if (status < 0)
3001 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3002 return status;
3003 }
3004
3005 static int SetFrequencyShifter(struct drxk_state *state,
3006 u16 intermediateFreqkHz,
3007 s32 tunerFreqOffset, bool isDTV)
3008 {
3009 bool selectPosImage = false;
3010 u32 rfFreqResidual = tunerFreqOffset;
3011 u32 fmFrequencyShift = 0;
3012 bool tunerMirror = !state->m_bMirrorFreqSpect;
3013 u32 adcFreq;
3014 bool adcFlip;
3015 int status;
3016 u32 ifFreqActual;
3017 u32 samplingFrequency = (u32) (state->m_sysClockFreq / 3);
3018 u32 frequencyShift;
3019 bool imageToSelect;
3020
3021 dprintk(1, "\n");
3022
3023 /*
3024 Program frequency shifter
3025 No need to account for mirroring on RF
3026 */
3027 if (isDTV) {
3028 if ((state->m_OperationMode == OM_QAM_ITU_A) ||
3029 (state->m_OperationMode == OM_QAM_ITU_C) ||
3030 (state->m_OperationMode == OM_DVBT))
3031 selectPosImage = true;
3032 else
3033 selectPosImage = false;
3034 }
3035 if (tunerMirror)
3036 /* tuner doesn't mirror */
3037 ifFreqActual = intermediateFreqkHz +
3038 rfFreqResidual + fmFrequencyShift;
3039 else
3040 /* tuner mirrors */
3041 ifFreqActual = intermediateFreqkHz -
3042 rfFreqResidual - fmFrequencyShift;
3043 if (ifFreqActual > samplingFrequency / 2) {
3044 /* adc mirrors */
3045 adcFreq = samplingFrequency - ifFreqActual;
3046 adcFlip = true;
3047 } else {
3048 /* adc doesn't mirror */
3049 adcFreq = ifFreqActual;
3050 adcFlip = false;
3051 }
3052
3053 frequencyShift = adcFreq;
3054 imageToSelect = state->m_rfmirror ^ tunerMirror ^
3055 adcFlip ^ selectPosImage;
3056 state->m_IqmFsRateOfs =
3057 Frac28a((frequencyShift), samplingFrequency);
3058
3059 if (imageToSelect)
3060 state->m_IqmFsRateOfs = ~state->m_IqmFsRateOfs + 1;
3061
3062 /* Program frequency shifter with tuner offset compensation */
3063 /* frequencyShift += tunerFreqOffset; TODO */
3064 status = write32(state, IQM_FS_RATE_OFS_LO__A,
3065 state->m_IqmFsRateOfs);
3066 if (status < 0)
3067 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3068 return status;
3069 }
3070
3071 static int InitAGC(struct drxk_state *state, bool isDTV)
3072 {
3073 u16 ingainTgt = 0;
3074 u16 ingainTgtMin = 0;
3075 u16 ingainTgtMax = 0;
3076 u16 clpCyclen = 0;
3077 u16 clpSumMin = 0;
3078 u16 clpDirTo = 0;
3079 u16 snsSumMin = 0;
3080 u16 snsSumMax = 0;
3081 u16 clpSumMax = 0;
3082 u16 snsDirTo = 0;
3083 u16 kiInnergainMin = 0;
3084 u16 ifIaccuHiTgt = 0;
3085 u16 ifIaccuHiTgtMin = 0;
3086 u16 ifIaccuHiTgtMax = 0;
3087 u16 data = 0;
3088 u16 fastClpCtrlDelay = 0;
3089 u16 clpCtrlMode = 0;
3090 int status = 0;
3091
3092 dprintk(1, "\n");
3093
3094 /* Common settings */
3095 snsSumMax = 1023;
3096 ifIaccuHiTgtMin = 2047;
3097 clpCyclen = 500;
3098 clpSumMax = 1023;
3099
3100 /* AGCInit() not available for DVBT; init done in microcode */
3101 if (!IsQAM(state)) {
3102 printk(KERN_ERR "drxk: %s: mode %d is not DVB-C\n", __func__, state->m_OperationMode);
3103 return -EINVAL;
3104 }
3105
3106 /* FIXME: Analog TV AGC require different settings */
3107
3108 /* Standard specific settings */
3109 clpSumMin = 8;
3110 clpDirTo = (u16) -9;
3111 clpCtrlMode = 0;
3112 snsSumMin = 8;
3113 snsDirTo = (u16) -9;
3114 kiInnergainMin = (u16) -1030;
3115 ifIaccuHiTgtMax = 0x2380;
3116 ifIaccuHiTgt = 0x2380;
3117 ingainTgtMin = 0x0511;
3118 ingainTgt = 0x0511;
3119 ingainTgtMax = 5119;
3120 fastClpCtrlDelay = state->m_qamIfAgcCfg.FastClipCtrlDelay;
3121
3122 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, fastClpCtrlDelay);
3123 if (status < 0)
3124 goto error;
3125
3126 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode);
3127 if (status < 0)
3128 goto error;
3129 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingainTgt);
3130 if (status < 0)
3131 goto error;
3132 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingainTgtMin);
3133 if (status < 0)
3134 goto error;
3135 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingainTgtMax);
3136 if (status < 0)
3137 goto error;
3138 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin);
3139 if (status < 0)
3140 goto error;
3141 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, ifIaccuHiTgtMax);
3142 if (status < 0)
3143 goto error;
3144 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
3145 if (status < 0)
3146 goto error;
3147 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
3148 if (status < 0)
3149 goto error;
3150 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
3151 if (status < 0)
3152 goto error;
3153 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3154 if (status < 0)
3155 goto error;
3156 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax);
3157 if (status < 0)
3158 goto error;
3159 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax);
3160 if (status < 0)
3161 goto error;
3162
3163 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin);
3164 if (status < 0)
3165 goto error;
3166 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, ifIaccuHiTgt);
3167 if (status < 0)
3168 goto error;
3169 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clpCyclen);
3170 if (status < 0)
3171 goto error;
3172
3173 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
3174 if (status < 0)
3175 goto error;
3176 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
3177 if (status < 0)
3178 goto error;
3179 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
3180 if (status < 0)
3181 goto error;
3182
3183 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3184 if (status < 0)
3185 goto error;
3186 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clpSumMin);
3187 if (status < 0)
3188 goto error;
3189 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, snsSumMin);
3190 if (status < 0)
3191 goto error;
3192 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo);
3193 if (status < 0)
3194 goto error;
3195 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo);
3196 if (status < 0)
3197 goto error;
3198 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3199 if (status < 0)
3200 goto error;
3201 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3202 if (status < 0)
3203 goto error;
3204 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3205 if (status < 0)
3206 goto error;
3207 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3208 if (status < 0)
3209 goto error;
3210 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3211 if (status < 0)
3212 goto error;
3213 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3214 if (status < 0)
3215 goto error;
3216 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3217 if (status < 0)
3218 goto error;
3219 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3220 if (status < 0)
3221 goto error;
3222 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3223 if (status < 0)
3224 goto error;
3225 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3226 if (status < 0)
3227 goto error;
3228 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3229 if (status < 0)
3230 goto error;
3231 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3232 if (status < 0)
3233 goto error;
3234 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3235 if (status < 0)
3236 goto error;
3237 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3238 if (status < 0)
3239 goto error;
3240
3241 /* Initialize inner-loop KI gain factors */
3242 status = read16(state, SCU_RAM_AGC_KI__A, &data);
3243 if (status < 0)
3244 goto error;
3245
3246 data = 0x0657;
3247 data &= ~SCU_RAM_AGC_KI_RF__M;
3248 data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B);
3249 data &= ~SCU_RAM_AGC_KI_IF__M;
3250 data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);
3251
3252 status = write16(state, SCU_RAM_AGC_KI__A, data);
3253 error:
3254 if (status < 0)
3255 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3256 return status;
3257 }
3258
3259 static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 *packetErr)
3260 {
3261 int status;
3262
3263 dprintk(1, "\n");
3264 if (packetErr == NULL)
3265 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3266 else
3267 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packetErr);
3268 if (status < 0)
3269 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3270 return status;
3271 }
3272
3273 static int DVBTScCommand(struct drxk_state *state,
3274 u16 cmd, u16 subcmd,
3275 u16 param0, u16 param1, u16 param2,
3276 u16 param3, u16 param4)
3277 {
3278 u16 curCmd = 0;
3279 u16 errCode = 0;
3280 u16 retryCnt = 0;
3281 u16 scExec = 0;
3282 int status;
3283
3284 dprintk(1, "\n");
3285 status = read16(state, OFDM_SC_COMM_EXEC__A, &scExec);
3286 if (scExec != 1) {
3287 /* SC is not running */
3288 status = -EINVAL;
3289 }
3290 if (status < 0)
3291 goto error;
3292
3293 /* Wait until sc is ready to receive command */
3294 retryCnt = 0;
3295 do {
3296 msleep(1);
3297 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
3298 retryCnt++;
3299 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
3300 if (retryCnt >= DRXK_MAX_RETRIES && (status < 0))
3301 goto error;
3302
3303 /* Write sub-command */
3304 switch (cmd) {
3305 /* All commands using sub-cmd */
3306 case OFDM_SC_RA_RAM_CMD_PROC_START:
3307 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3308 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3309 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
3310 if (status < 0)
3311 goto error;
3312 break;
3313 default:
3314 /* Do nothing */
3315 break;
3316 }
3317
3318 /* Write needed parameters and the command */
3319 switch (cmd) {
3320 /* All commands using 5 parameters */
3321 /* All commands using 4 parameters */
3322 /* All commands using 3 parameters */
3323 /* All commands using 2 parameters */
3324 case OFDM_SC_RA_RAM_CMD_PROC_START:
3325 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3326 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3327 status = write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
3328 /* All commands using 1 parameters */
3329 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3330 case OFDM_SC_RA_RAM_CMD_USER_IO:
3331 status = write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
3332 /* All commands using 0 parameters */
3333 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3334 case OFDM_SC_RA_RAM_CMD_NULL:
3335 /* Write command */
3336 status = write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
3337 break;
3338 default:
3339 /* Unknown command */
3340 status = -EINVAL;
3341 }
3342 if (status < 0)
3343 goto error;
3344
3345 /* Wait until sc is ready processing command */
3346 retryCnt = 0;
3347 do {
3348 msleep(1);
3349 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
3350 retryCnt++;
3351 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
3352 if (retryCnt >= DRXK_MAX_RETRIES && (status < 0))
3353 goto error;
3354
3355 /* Check for illegal cmd */
3356 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode);
3357 if (errCode == 0xFFFF) {
3358 /* illegal command */
3359 status = -EINVAL;
3360 }
3361 if (status < 0)
3362 goto error;
3363
3364 /* Retreive results parameters from SC */
3365 switch (cmd) {
3366 /* All commands yielding 5 results */
3367 /* All commands yielding 4 results */
3368 /* All commands yielding 3 results */
3369 /* All commands yielding 2 results */
3370 /* All commands yielding 1 result */
3371 case OFDM_SC_RA_RAM_CMD_USER_IO:
3372 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3373 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
3374 /* All commands yielding 0 results */
3375 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3376 case OFDM_SC_RA_RAM_CMD_SET_TIMER:
3377 case OFDM_SC_RA_RAM_CMD_PROC_START:
3378 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3379 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3380 case OFDM_SC_RA_RAM_CMD_NULL:
3381 break;
3382 default:
3383 /* Unknown command */
3384 status = -EINVAL;
3385 break;
3386 } /* switch (cmd->cmd) */
3387 error:
3388 if (status < 0)
3389 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3390 return status;
3391 }
3392
3393 static int PowerUpDVBT(struct drxk_state *state)
3394 {
3395 enum DRXPowerMode powerMode = DRX_POWER_UP;
3396 int status;
3397
3398 dprintk(1, "\n");
3399 status = CtrlPowerMode(state, &powerMode);
3400 if (status < 0)
3401 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3402 return status;
3403 }
3404
3405 static int DVBTCtrlSetIncEnable(struct drxk_state *state, bool *enabled)
3406 {
3407 int status;
3408
3409 dprintk(1, "\n");
3410 if (*enabled == true)
3411 status = write16(state, IQM_CF_BYPASSDET__A, 0);
3412 else
3413 status = write16(state, IQM_CF_BYPASSDET__A, 1);
3414 if (status < 0)
3415 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3416 return status;
3417 }
3418
3419 #define DEFAULT_FR_THRES_8K 4000
3420 static int DVBTCtrlSetFrEnable(struct drxk_state *state, bool *enabled)
3421 {
3422
3423 int status;
3424
3425 dprintk(1, "\n");
3426 if (*enabled == true) {
3427 /* write mask to 1 */
3428 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
3429 DEFAULT_FR_THRES_8K);
3430 } else {
3431 /* write mask to 0 */
3432 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
3433 }
3434 if (status < 0)
3435 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3436
3437 return status;
3438 }
3439
3440 static int DVBTCtrlSetEchoThreshold(struct drxk_state *state,
3441 struct DRXKCfgDvbtEchoThres_t *echoThres)
3442 {
3443 u16 data = 0;
3444 int status;
3445
3446 dprintk(1, "\n");
3447 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
3448 if (status < 0)
3449 goto error;
3450
3451 switch (echoThres->fftMode) {
3452 case DRX_FFTMODE_2K:
3453 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
3454 data |= ((echoThres->threshold <<
3455 OFDM_SC_RA_RAM_ECHO_THRES_2K__B)
3456 & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
3457 break;
3458 case DRX_FFTMODE_8K:
3459 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
3460 data |= ((echoThres->threshold <<
3461 OFDM_SC_RA_RAM_ECHO_THRES_8K__B)
3462 & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
3463 break;
3464 default:
3465 return -EINVAL;
3466 }
3467
3468 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3469 error:
3470 if (status < 0)
3471 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3472 return status;
3473 }
3474
3475 static int DVBTCtrlSetSqiSpeed(struct drxk_state *state,
3476 enum DRXKCfgDvbtSqiSpeed *speed)
3477 {
3478 int status = -EINVAL;
3479
3480 dprintk(1, "\n");
3481
3482 switch (*speed) {
3483 case DRXK_DVBT_SQI_SPEED_FAST:
3484 case DRXK_DVBT_SQI_SPEED_MEDIUM:
3485 case DRXK_DVBT_SQI_SPEED_SLOW:
3486 break;
3487 default:
3488 goto error;
3489 }
3490 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
3491 (u16) *speed);
3492 error:
3493 if (status < 0)
3494 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3495 return status;
3496 }
3497
3498 /*============================================================================*/
3499
3500 /**
3501 * \brief Activate DVBT specific presets
3502 * \param demod instance of demodulator.
3503 * \return DRXStatus_t.
3504 *
3505 * Called in DVBTSetStandard
3506 *
3507 */
3508 static int DVBTActivatePresets(struct drxk_state *state)
3509 {
3510 int status;
3511 bool setincenable = false;
3512 bool setfrenable = true;
3513
3514 struct DRXKCfgDvbtEchoThres_t echoThres2k = { 0, DRX_FFTMODE_2K };
3515 struct DRXKCfgDvbtEchoThres_t echoThres8k = { 0, DRX_FFTMODE_8K };
3516
3517 dprintk(1, "\n");
3518 status = DVBTCtrlSetIncEnable(state, &setincenable);
3519 if (status < 0)
3520 goto error;
3521 status = DVBTCtrlSetFrEnable(state, &setfrenable);
3522 if (status < 0)
3523 goto error;
3524 status = DVBTCtrlSetEchoThreshold(state, &echoThres2k);
3525 if (status < 0)
3526 goto error;
3527 status = DVBTCtrlSetEchoThreshold(state, &echoThres8k);
3528 if (status < 0)
3529 goto error;
3530 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, state->m_dvbtIfAgcCfg.IngainTgtMax);
3531 error:
3532 if (status < 0)
3533 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3534 return status;
3535 }
3536
3537 /*============================================================================*/
3538
3539 /**
3540 * \brief Initialize channelswitch-independent settings for DVBT.
3541 * \param demod instance of demodulator.
3542 * \return DRXStatus_t.
3543 *
3544 * For ROM code channel filter taps are loaded from the bootloader. For microcode
3545 * the DVB-T taps from the drxk_filters.h are used.
3546 */
3547 static int SetDVBTStandard(struct drxk_state *state,
3548 enum OperationMode oMode)
3549 {
3550 u16 cmdResult = 0;
3551 u16 data = 0;
3552 int status;
3553
3554 dprintk(1, "\n");
3555
3556 PowerUpDVBT(state);
3557 /* added antenna switch */
3558 SwitchAntennaToDVBT(state);
3559 /* send OFDM reset command */
3560 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
3561 if (status < 0)
3562 goto error;
3563
3564 /* send OFDM setenv command */
3565 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 0, NULL, 1, &cmdResult);
3566 if (status < 0)
3567 goto error;
3568
3569 /* reset datapath for OFDM, processors first */
3570 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3571 if (status < 0)
3572 goto error;
3573 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3574 if (status < 0)
3575 goto error;
3576 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3577 if (status < 0)
3578 goto error;
3579
3580 /* IQM setup */
3581 /* synchronize on ofdstate->m_festart */
3582 status = write16(state, IQM_AF_UPD_SEL__A, 1);
3583 if (status < 0)
3584 goto error;
3585 /* window size for clipping ADC detection */
3586 status = write16(state, IQM_AF_CLP_LEN__A, 0);
3587 if (status < 0)
3588 goto error;
3589 /* window size for for sense pre-SAW detection */
3590 status = write16(state, IQM_AF_SNS_LEN__A, 0);
3591 if (status < 0)
3592 goto error;
3593 /* sense threshold for sense pre-SAW detection */
3594 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3595 if (status < 0)
3596 goto error;
3597 status = SetIqmAf(state, true);
3598 if (status < 0)
3599 goto error;
3600
3601 status = write16(state, IQM_AF_AGC_RF__A, 0);
3602 if (status < 0)
3603 goto error;
3604
3605 /* Impulse noise cruncher setup */
3606 status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */
3607 if (status < 0)
3608 goto error;
3609 status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */
3610 if (status < 0)
3611 goto error;
3612 status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */
3613 if (status < 0)
3614 goto error;
3615
3616 status = write16(state, IQM_RC_STRETCH__A, 16);
3617 if (status < 0)
3618 goto error;
3619 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
3620 if (status < 0)
3621 goto error;
3622 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
3623 if (status < 0)
3624 goto error;
3625 status = write16(state, IQM_CF_SCALE__A, 1600);
3626 if (status < 0)
3627 goto error;
3628 status = write16(state, IQM_CF_SCALE_SH__A, 0);
3629 if (status < 0)
3630 goto error;
3631
3632 /* virtual clipping threshold for clipping ADC detection */
3633 status = write16(state, IQM_AF_CLP_TH__A, 448);
3634 if (status < 0)
3635 goto error;
3636 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */
3637 if (status < 0)
3638 goto error;
3639
3640 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
3641 if (status < 0)
3642 goto error;
3643
3644 status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */
3645 if (status < 0)
3646 goto error;
3647 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
3648 if (status < 0)
3649 goto error;
3650 /* enable power measurement interrupt */
3651 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
3652 if (status < 0)
3653 goto error;
3654 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3655 if (status < 0)
3656 goto error;
3657
3658 /* IQM will not be reset from here, sync ADC and update/init AGC */
3659 status = ADCSynchronization(state);
3660 if (status < 0)
3661 goto error;
3662 status = SetPreSaw(state, &state->m_dvbtPreSawCfg);
3663 if (status < 0)
3664 goto error;
3665
3666 /* Halt SCU to enable safe non-atomic accesses */
3667 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3668 if (status < 0)
3669 goto error;
3670
3671 status = SetAgcRf(state, &state->m_dvbtRfAgcCfg, true);
3672 if (status < 0)
3673 goto error;
3674 status = SetAgcIf(state, &state->m_dvbtIfAgcCfg, true);
3675 if (status < 0)
3676 goto error;
3677
3678 /* Set Noise Estimation notch width and enable DC fix */
3679 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3680 if (status < 0)
3681 goto error;
3682 data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M;
3683 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3684 if (status < 0)
3685 goto error;
3686
3687 /* Activate SCU to enable SCU commands */
3688 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3689 if (status < 0)
3690 goto error;
3691
3692 if (!state->m_DRXK_A3_ROM_CODE) {
3693 /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */
3694 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, state->m_dvbtIfAgcCfg.FastClipCtrlDelay);
3695 if (status < 0)
3696 goto error;
3697 }
3698
3699 /* OFDM_SC setup */
3700 #ifdef COMPILE_FOR_NONRT
3701 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3702 if (status < 0)
3703 goto error;
3704 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3705 if (status < 0)
3706 goto error;
3707 #endif
3708
3709 /* FEC setup */
3710 status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */
3711 if (status < 0)
3712 goto error;
3713
3714
3715 #ifdef COMPILE_FOR_NONRT
3716 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3717 if (status < 0)
3718 goto error;
3719 #else
3720 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3721 if (status < 0)
3722 goto error;
3723 #endif
3724 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3725 if (status < 0)
3726 goto error;
3727
3728 /* Setup MPEG bus */
3729 status = MPEGTSDtoSetup(state, OM_DVBT);
3730 if (status < 0)
3731 goto error;
3732 /* Set DVBT Presets */
3733 status = DVBTActivatePresets(state);
3734 if (status < 0)
3735 goto error;
3736
3737 error:
3738 if (status < 0)
3739 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3740 return status;
3741 }
3742
3743 /*============================================================================*/
3744 /**
3745 * \brief Start dvbt demodulating for channel.
3746 * \param demod instance of demodulator.
3747 * \return DRXStatus_t.
3748 */
3749 static int DVBTStart(struct drxk_state *state)
3750 {
3751 u16 param1;
3752 int status;
3753 /* DRXKOfdmScCmd_t scCmd; */
3754
3755 dprintk(1, "\n");
3756 /* Start correct processes to get in lock */
3757 /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
3758 param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
3759 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 0, 0, 0);
3760 if (status < 0)
3761 goto error;
3762 /* Start FEC OC */
3763 status = MPEGTSStart(state);
3764 if (status < 0)
3765 goto error;
3766 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3767 if (status < 0)
3768 goto error;
3769 error:
3770 if (status < 0)
3771 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3772 return status;
3773 }
3774
3775
3776 /*============================================================================*/
3777
3778 /**
3779 * \brief Set up dvbt demodulator for channel.
3780 * \param demod instance of demodulator.
3781 * \return DRXStatus_t.
3782 * // original DVBTSetChannel()
3783 */
3784 static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3785 s32 tunerFreqOffset)
3786 {
3787 u16 cmdResult = 0;
3788 u16 transmissionParams = 0;
3789 u16 operationMode = 0;
3790 u32 iqmRcRateOfs = 0;
3791 u32 bandwidth = 0;
3792 u16 param1;
3793 int status;
3794
3795 dprintk(1, "IF =%d, TFO = %d\n", IntermediateFreqkHz, tunerFreqOffset);
3796
3797 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
3798 if (status < 0)
3799 goto error;
3800
3801 /* Halt SCU to enable safe non-atomic accesses */
3802 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3803 if (status < 0)
3804 goto error;
3805
3806 /* Stop processors */
3807 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3808 if (status < 0)
3809 goto error;
3810 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3811 if (status < 0)
3812 goto error;
3813
3814 /* Mandatory fix, always stop CP, required to set spl offset back to
3815 hardware default (is set to 0 by ucode during pilot detection */
3816 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3817 if (status < 0)
3818 goto error;
3819
3820 /*== Write channel settings to device =====================================*/
3821
3822 /* mode */
3823 switch (state->props.transmission_mode) {
3824 case TRANSMISSION_MODE_AUTO:
3825 default:
3826 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M;
3827 /* fall through , try first guess DRX_FFTMODE_8K */
3828 case TRANSMISSION_MODE_8K:
3829 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
3830 break;
3831 case TRANSMISSION_MODE_2K:
3832 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
3833 break;
3834 }
3835
3836 /* guard */
3837 switch (state->props.guard_interval) {
3838 default:
3839 case GUARD_INTERVAL_AUTO:
3840 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M;
3841 /* fall through , try first guess DRX_GUARD_1DIV4 */
3842 case GUARD_INTERVAL_1_4:
3843 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4;
3844 break;
3845 case GUARD_INTERVAL_1_32:
3846 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32;
3847 break;
3848 case GUARD_INTERVAL_1_16:
3849 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
3850 break;
3851 case GUARD_INTERVAL_1_8:
3852 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
3853 break;
3854 }
3855
3856 /* hierarchy */
3857 switch (state->props.hierarchy) {
3858 case HIERARCHY_AUTO:
3859 case HIERARCHY_NONE:
3860 default:
3861 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M;
3862 /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */
3863 /* transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */
3864 /* break; */
3865 case HIERARCHY_1:
3866 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1;
3867 break;
3868 case HIERARCHY_2:
3869 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2;
3870 break;
3871 case HIERARCHY_4:
3872 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
3873 break;
3874 }
3875
3876
3877 /* modulation */
3878 switch (state->props.modulation) {
3879 case QAM_AUTO:
3880 default:
3881 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M;
3882 /* fall through , try first guess DRX_CONSTELLATION_QAM64 */
3883 case QAM_64:
3884 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64;
3885 break;
3886 case QPSK:
3887 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK;
3888 break;
3889 case QAM_16:
3890 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16;
3891 break;
3892 }
3893 #if 0
3894 /* No hierachical channels support in BDA */
3895 /* Priority (only for hierarchical channels) */
3896 switch (channel->priority) {
3897 case DRX_PRIORITY_LOW:
3898 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO;
3899 WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3900 OFDM_EC_SB_PRIOR_LO);
3901 break;
3902 case DRX_PRIORITY_HIGH:
3903 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3904 WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3905 OFDM_EC_SB_PRIOR_HI));
3906 break;
3907 case DRX_PRIORITY_UNKNOWN: /* fall through */
3908 default:
3909 status = -EINVAL;
3910 goto error;
3911 }
3912 #else
3913 /* Set Priorty high */
3914 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3915 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3916 if (status < 0)
3917 goto error;
3918 #endif
3919
3920 /* coderate */
3921 switch (state->props.code_rate_HP) {
3922 case FEC_AUTO:
3923 default:
3924 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M;
3925 /* fall through , try first guess DRX_CODERATE_2DIV3 */
3926 case FEC_2_3:
3927 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3;
3928 break;
3929 case FEC_1_2:
3930 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2;
3931 break;
3932 case FEC_3_4:
3933 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4;
3934 break;
3935 case FEC_5_6:
3936 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6;
3937 break;
3938 case FEC_7_8:
3939 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
3940 break;
3941 }
3942
3943 /* SAW filter selection: normaly not necesarry, but if wanted
3944 the application can select a SAW filter via the driver by using UIOs */
3945 /* First determine real bandwidth (Hz) */
3946 /* Also set delay for impulse noise cruncher */
3947 /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed
3948 by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC
3949 functions */
3950 switch (state->props.bandwidth_hz) {
3951 case 0:
3952 state->props.bandwidth_hz = 8000000;
3953 /* fall though */
3954 case 8000000:
3955 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
3956 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052);
3957 if (status < 0)
3958 goto error;
3959 /* cochannel protection for PAL 8 MHz */
3960 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7);
3961 if (status < 0)
3962 goto error;
3963 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7);
3964 if (status < 0)
3965 goto error;
3966 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7);
3967 if (status < 0)
3968 goto error;
3969 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3970 if (status < 0)
3971 goto error;
3972 break;
3973 case 7000000:
3974 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
3975 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491);
3976 if (status < 0)
3977 goto error;
3978 /* cochannel protection for PAL 7 MHz */
3979 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8);
3980 if (status < 0)
3981 goto error;
3982 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8);
3983 if (status < 0)
3984 goto error;
3985 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4);
3986 if (status < 0)
3987 goto error;
3988 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3989 if (status < 0)
3990 goto error;
3991 break;
3992 case 6000000:
3993 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
3994 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073);
3995 if (status < 0)
3996 goto error;
3997 /* cochannel protection for NTSC 6 MHz */
3998 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19);
3999 if (status < 0)
4000 goto error;
4001 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19);
4002 if (status < 0)
4003 goto error;
4004 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14);
4005 if (status < 0)
4006 goto error;
4007 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
4008 if (status < 0)
4009 goto error;
4010 break;
4011 default:
4012 status = -EINVAL;
4013 goto error;
4014 }
4015
4016 if (iqmRcRateOfs == 0) {
4017 /* Now compute IQM_RC_RATE_OFS
4018 (((SysFreq/BandWidth)/2)/2) -1) * 2^23)
4019 =>
4020 ((SysFreq / BandWidth) * (2^21)) - (2^23)
4021 */
4022 /* (SysFreq / BandWidth) * (2^28) */
4023 /* assert (MAX(sysClk)/MIN(bandwidth) < 16)
4024 => assert(MAX(sysClk) < 16*MIN(bandwidth))
4025 => assert(109714272 > 48000000) = true so Frac 28 can be used */
4026 iqmRcRateOfs = Frac28a((u32)
4027 ((state->m_sysClockFreq *
4028 1000) / 3), bandwidth);
4029 /* (SysFreq / BandWidth) * (2^21), rounding before truncating */
4030 if ((iqmRcRateOfs & 0x7fL) >= 0x40)
4031 iqmRcRateOfs += 0x80L;
4032 iqmRcRateOfs = iqmRcRateOfs >> 7;
4033 /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */
4034 iqmRcRateOfs = iqmRcRateOfs - (1 << 23);
4035 }
4036
4037 iqmRcRateOfs &=
4038 ((((u32) IQM_RC_RATE_OFS_HI__M) <<
4039 IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
4040 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRateOfs);
4041 if (status < 0)
4042 goto error;
4043
4044 /* Bandwidth setting done */
4045
4046 #if 0
4047 status = DVBTSetFrequencyShift(demod, channel, tunerOffset);
4048 if (status < 0)
4049 goto error;
4050 #endif
4051 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
4052 if (status < 0)
4053 goto error;
4054
4055 /*== Start SC, write channel settings to SC ===============================*/
4056
4057 /* Activate SCU to enable SCU commands */
4058 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
4059 if (status < 0)
4060 goto error;
4061
4062 /* Enable SC after setting all other parameters */
4063 status = write16(state, OFDM_SC_COMM_STATE__A, 0);
4064 if (status < 0)
4065 goto error;
4066 status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
4067 if (status < 0)
4068 goto error;
4069
4070
4071 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
4072 if (status < 0)
4073 goto error;
4074
4075 /* Write SC parameter registers, set all AUTO flags in operation mode */
4076 param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M |
4077 OFDM_SC_RA_RAM_OP_AUTO_GUARD__M |
4078 OFDM_SC_RA_RAM_OP_AUTO_CONST__M |
4079 OFDM_SC_RA_RAM_OP_AUTO_HIER__M |
4080 OFDM_SC_RA_RAM_OP_AUTO_RATE__M);
4081 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
4082 0, transmissionParams, param1, 0, 0, 0);
4083 if (status < 0)
4084 goto error;
4085
4086 if (!state->m_DRXK_A3_ROM_CODE)
4087 status = DVBTCtrlSetSqiSpeed(state, &state->m_sqiSpeed);
4088 error:
4089 if (status < 0)
4090 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4091
4092 return status;
4093 }
4094
4095
4096 /*============================================================================*/
4097
4098 /**
4099 * \brief Retreive lock status .
4100 * \param demod Pointer to demodulator instance.
4101 * \param lockStat Pointer to lock status structure.
4102 * \return DRXStatus_t.
4103 *
4104 */
4105 static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus)
4106 {
4107 int status;
4108 const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M |
4109 OFDM_SC_RA_RAM_LOCK_FEC__M);
4110 const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M);
4111 const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M;
4112
4113 u16 ScRaRamLock = 0;
4114 u16 ScCommExec = 0;
4115
4116 dprintk(1, "\n");
4117
4118 *pLockStatus = NOT_LOCKED;
4119 /* driver 0.9.0 */
4120 /* Check if SC is running */
4121 status = read16(state, OFDM_SC_COMM_EXEC__A, &ScCommExec);
4122 if (status < 0)
4123 goto end;
4124 if (ScCommExec == OFDM_SC_COMM_EXEC_STOP)
4125 goto end;
4126
4127 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock);
4128 if (status < 0)
4129 goto end;
4130
4131 if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask)
4132 *pLockStatus = MPEG_LOCK;
4133 else if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
4134 *pLockStatus = FEC_LOCK;
4135 else if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
4136 *pLockStatus = DEMOD_LOCK;
4137 else if (ScRaRamLock & OFDM_SC_RA_RAM_LOCK_NODVBT__M)
4138 *pLockStatus = NEVER_LOCK;
4139 end:
4140 if (status < 0)
4141 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4142
4143 return status;
4144 }
4145
4146 static int PowerUpQAM(struct drxk_state *state)
4147 {
4148 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
4149 int status;
4150
4151 dprintk(1, "\n");
4152 status = CtrlPowerMode(state, &powerMode);
4153 if (status < 0)
4154 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4155
4156 return status;
4157 }
4158
4159
4160 /** Power Down QAM */
4161 static int PowerDownQAM(struct drxk_state *state)
4162 {
4163 u16 data = 0;
4164 u16 cmdResult;
4165 int status = 0;
4166
4167 dprintk(1, "\n");
4168 status = read16(state, SCU_COMM_EXEC__A, &data);
4169 if (status < 0)
4170 goto error;
4171 if (data == SCU_COMM_EXEC_ACTIVE) {
4172 /*
4173 STOP demodulator
4174 QAM and HW blocks
4175 */
4176 /* stop all comstate->m_exec */
4177 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4178 if (status < 0)
4179 goto error;
4180 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
4181 if (status < 0)
4182 goto error;
4183 }
4184 /* powerdown AFE */
4185 status = SetIqmAf(state, false);
4186
4187 error:
4188 if (status < 0)
4189 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4190
4191 return status;
4192 }
4193
4194 /*============================================================================*/
4195
4196 /**
4197 * \brief Setup of the QAM Measurement intervals for signal quality
4198 * \param demod instance of demod.
4199 * \param modulation current modulation.
4200 * \return DRXStatus_t.
4201 *
4202 * NOTE:
4203 * Take into account that for certain settings the errorcounters can overflow.
4204 * The implementation does not check this.
4205 *
4206 */
4207 static int SetQAMMeasurement(struct drxk_state *state,
4208 enum EDrxkConstellation modulation,
4209 u32 symbolRate)
4210 {
4211 u32 fecBitsDesired = 0; /* BER accounting period */
4212 u32 fecRsPeriodTotal = 0; /* Total period */
4213 u16 fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */
4214 u16 fecRsPeriod = 0; /* Value for corresponding I2C register */
4215 int status = 0;
4216
4217 dprintk(1, "\n");
4218
4219 fecRsPrescale = 1;
4220 /* fecBitsDesired = symbolRate [kHz] *
4221 FrameLenght [ms] *
4222 (modulation + 1) *
4223 SyncLoss (== 1) *
4224 ViterbiLoss (==1)
4225 */
4226 switch (modulation) {
4227 case DRX_CONSTELLATION_QAM16:
4228 fecBitsDesired = 4 * symbolRate;
4229 break;
4230 case DRX_CONSTELLATION_QAM32:
4231 fecBitsDesired = 5 * symbolRate;
4232 break;
4233 case DRX_CONSTELLATION_QAM64:
4234 fecBitsDesired = 6 * symbolRate;
4235 break;
4236 case DRX_CONSTELLATION_QAM128:
4237 fecBitsDesired = 7 * symbolRate;
4238 break;
4239 case DRX_CONSTELLATION_QAM256:
4240 fecBitsDesired = 8 * symbolRate;
4241 break;
4242 default:
4243 status = -EINVAL;
4244 }
4245 if (status < 0)
4246 goto error;
4247
4248 fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */
4249 fecBitsDesired *= 500; /* meas. period [ms] */
4250
4251 /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */
4252 /* fecRsPeriodTotal = fecBitsDesired / 1632 */
4253 fecRsPeriodTotal = (fecBitsDesired / 1632UL) + 1; /* roughly ceil */
4254
4255 /* fecRsPeriodTotal = fecRsPrescale * fecRsPeriod */
4256 fecRsPrescale = 1 + (u16) (fecRsPeriodTotal >> 16);
4257 if (fecRsPrescale == 0) {
4258 /* Divide by zero (though impossible) */
4259 status = -EINVAL;
4260 if (status < 0)
4261 goto error;
4262 }
4263 fecRsPeriod =
4264 ((u16) fecRsPeriodTotal +
4265 (fecRsPrescale >> 1)) / fecRsPrescale;
4266
4267 /* write corresponding registers */
4268 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod);
4269 if (status < 0)
4270 goto error;
4271 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale);
4272 if (status < 0)
4273 goto error;
4274 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod);
4275 error:
4276 if (status < 0)
4277 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4278 return status;
4279 }
4280
4281 static int SetQAM16(struct drxk_state *state)
4282 {
4283 int status = 0;
4284
4285 dprintk(1, "\n");
4286 /* QAM Equalizer Setup */
4287 /* Equalizer */
4288 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
4289 if (status < 0)
4290 goto error;
4291 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
4292 if (status < 0)
4293 goto error;
4294 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
4295 if (status < 0)
4296 goto error;
4297 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
4298 if (status < 0)
4299 goto error;
4300 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4301 if (status < 0)
4302 goto error;
4303 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4304 if (status < 0)
4305 goto error;
4306 /* Decision Feedback Equalizer */
4307 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
4308 if (status < 0)
4309 goto error;
4310 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
4311 if (status < 0)
4312 goto error;
4313 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
4314 if (status < 0)
4315 goto error;
4316 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
4317 if (status < 0)
4318 goto error;
4319 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
4320 if (status < 0)
4321 goto error;
4322 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4323 if (status < 0)
4324 goto error;
4325
4326 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4327 if (status < 0)
4328 goto error;
4329 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4330 if (status < 0)
4331 goto error;
4332 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4333 if (status < 0)
4334 goto error;
4335
4336 /* QAM Slicer Settings */
4337 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16);
4338 if (status < 0)
4339 goto error;
4340
4341 /* QAM Loop Controller Coeficients */
4342 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4343 if (status < 0)
4344 goto error;
4345 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4346 if (status < 0)
4347 goto error;
4348 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4349 if (status < 0)
4350 goto error;
4351 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4352 if (status < 0)
4353 goto error;
4354 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4355 if (status < 0)
4356 goto error;
4357 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4358 if (status < 0)
4359 goto error;
4360 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4361 if (status < 0)
4362 goto error;
4363 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4364 if (status < 0)
4365 goto error;
4366
4367 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4368 if (status < 0)
4369 goto error;
4370 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4371 if (status < 0)
4372 goto error;
4373 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4374 if (status < 0)
4375 goto error;
4376 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4377 if (status < 0)
4378 goto error;
4379 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4380 if (status < 0)
4381 goto error;
4382 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4383 if (status < 0)
4384 goto error;
4385 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4386 if (status < 0)
4387 goto error;
4388 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4389 if (status < 0)
4390 goto error;
4391 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4392 if (status < 0)
4393 goto error;
4394 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4395 if (status < 0)
4396 goto error;
4397 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4398 if (status < 0)
4399 goto error;
4400 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4401 if (status < 0)
4402 goto error;
4403
4404
4405 /* QAM State Machine (FSM) Thresholds */
4406
4407 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
4408 if (status < 0)
4409 goto error;
4410 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4411 if (status < 0)
4412 goto error;
4413 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4414 if (status < 0)
4415 goto error;
4416 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4417 if (status < 0)
4418 goto error;
4419 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4420 if (status < 0)
4421 goto error;
4422 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4423 if (status < 0)
4424 goto error;
4425
4426 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4427 if (status < 0)
4428 goto error;
4429 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4430 if (status < 0)
4431 goto error;
4432 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4433 if (status < 0)
4434 goto error;
4435
4436
4437 /* QAM FSM Tracking Parameters */
4438
4439 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
4440 if (status < 0)
4441 goto error;
4442 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
4443 if (status < 0)
4444 goto error;
4445 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
4446 if (status < 0)
4447 goto error;
4448 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
4449 if (status < 0)
4450 goto error;
4451 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
4452 if (status < 0)
4453 goto error;
4454 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
4455 if (status < 0)
4456 goto error;
4457 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
4458 if (status < 0)
4459 goto error;
4460
4461 error:
4462 if (status < 0)
4463 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4464 return status;
4465 }
4466
4467 /*============================================================================*/
4468
4469 /**
4470 * \brief QAM32 specific setup
4471 * \param demod instance of demod.
4472 * \return DRXStatus_t.
4473 */
4474 static int SetQAM32(struct drxk_state *state)
4475 {
4476 int status = 0;
4477
4478 dprintk(1, "\n");
4479
4480 /* QAM Equalizer Setup */
4481 /* Equalizer */
4482 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4483 if (status < 0)
4484 goto error;
4485 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4486 if (status < 0)
4487 goto error;
4488 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4489 if (status < 0)
4490 goto error;
4491 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4492 if (status < 0)
4493 goto error;
4494 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4495 if (status < 0)
4496 goto error;
4497 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4498 if (status < 0)
4499 goto error;
4500
4501 /* Decision Feedback Equalizer */
4502 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
4503 if (status < 0)
4504 goto error;
4505 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
4506 if (status < 0)
4507 goto error;
4508 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
4509 if (status < 0)
4510 goto error;
4511 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
4512 if (status < 0)
4513 goto error;
4514 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4515 if (status < 0)
4516 goto error;
4517 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4518 if (status < 0)
4519 goto error;
4520
4521 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4522 if (status < 0)
4523 goto error;
4524 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4525 if (status < 0)
4526 goto error;
4527 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4528 if (status < 0)
4529 goto error;
4530
4531 /* QAM Slicer Settings */
4532
4533 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32);
4534 if (status < 0)
4535 goto error;
4536
4537
4538 /* QAM Loop Controller Coeficients */
4539
4540 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4541 if (status < 0)
4542 goto error;
4543 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4544 if (status < 0)
4545 goto error;
4546 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4547 if (status < 0)
4548 goto error;
4549 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4550 if (status < 0)
4551 goto error;
4552 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4553 if (status < 0)
4554 goto error;
4555 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4556 if (status < 0)
4557 goto error;
4558 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4559 if (status < 0)
4560 goto error;
4561 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4562 if (status < 0)
4563 goto error;
4564
4565 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4566 if (status < 0)
4567 goto error;
4568 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4569 if (status < 0)
4570 goto error;
4571 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4572 if (status < 0)
4573 goto error;
4574 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4575 if (status < 0)
4576 goto error;
4577 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4578 if (status < 0)
4579 goto error;
4580 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4581 if (status < 0)
4582 goto error;
4583 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4584 if (status < 0)
4585 goto error;
4586 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4587 if (status < 0)
4588 goto error;
4589 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4590 if (status < 0)
4591 goto error;
4592 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4593 if (status < 0)
4594 goto error;
4595 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4596 if (status < 0)
4597 goto error;
4598 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4599 if (status < 0)
4600 goto error;
4601
4602
4603 /* QAM State Machine (FSM) Thresholds */
4604
4605 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
4606 if (status < 0)
4607 goto error;
4608 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4609 if (status < 0)
4610 goto error;
4611 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4612 if (status < 0)
4613 goto error;
4614 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4615 if (status < 0)
4616 goto error;
4617 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4618 if (status < 0)
4619 goto error;
4620 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4621 if (status < 0)
4622 goto error;
4623
4624 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4625 if (status < 0)
4626 goto error;
4627 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4628 if (status < 0)
4629 goto error;
4630 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4631 if (status < 0)
4632 goto error;
4633
4634
4635 /* QAM FSM Tracking Parameters */
4636
4637 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4638 if (status < 0)
4639 goto error;
4640 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4641 if (status < 0)
4642 goto error;
4643 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4644 if (status < 0)
4645 goto error;
4646 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4647 if (status < 0)
4648 goto error;
4649 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4650 if (status < 0)
4651 goto error;
4652 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4653 if (status < 0)
4654 goto error;
4655 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4656 error:
4657 if (status < 0)
4658 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4659 return status;
4660 }
4661
4662 /*============================================================================*/
4663
4664 /**
4665 * \brief QAM64 specific setup
4666 * \param demod instance of demod.
4667 * \return DRXStatus_t.
4668 */
4669 static int SetQAM64(struct drxk_state *state)
4670 {
4671 int status = 0;
4672
4673 dprintk(1, "\n");
4674 /* QAM Equalizer Setup */
4675 /* Equalizer */
4676 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
4677 if (status < 0)
4678 goto error;
4679 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
4680 if (status < 0)
4681 goto error;
4682 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4683 if (status < 0)
4684 goto error;
4685 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4686 if (status < 0)
4687 goto error;
4688 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4689 if (status < 0)
4690 goto error;
4691 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4692 if (status < 0)
4693 goto error;
4694
4695 /* Decision Feedback Equalizer */
4696 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
4697 if (status < 0)
4698 goto error;
4699 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
4700 if (status < 0)
4701 goto error;
4702 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
4703 if (status < 0)
4704 goto error;
4705 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
4706 if (status < 0)
4707 goto error;
4708 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4709 if (status < 0)
4710 goto error;
4711 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4712 if (status < 0)
4713 goto error;
4714
4715 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4716 if (status < 0)
4717 goto error;
4718 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4719 if (status < 0)
4720 goto error;
4721 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4722 if (status < 0)
4723 goto error;
4724
4725 /* QAM Slicer Settings */
4726 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64);
4727 if (status < 0)
4728 goto error;
4729
4730
4731 /* QAM Loop Controller Coeficients */
4732
4733 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4734 if (status < 0)
4735 goto error;
4736 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4737 if (status < 0)
4738 goto error;
4739 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4740 if (status < 0)
4741 goto error;
4742 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4743 if (status < 0)
4744 goto error;
4745 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4746 if (status < 0)
4747 goto error;
4748 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4749 if (status < 0)
4750 goto error;
4751 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4752 if (status < 0)
4753 goto error;
4754 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4755 if (status < 0)
4756 goto error;
4757
4758 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4759 if (status < 0)
4760 goto error;
4761 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4762 if (status < 0)
4763 goto error;
4764 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4765 if (status < 0)
4766 goto error;
4767 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4768 if (status < 0)
4769 goto error;
4770 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4771 if (status < 0)
4772 goto error;
4773 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4774 if (status < 0)
4775 goto error;
4776 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4777 if (status < 0)
4778 goto error;
4779 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4780 if (status < 0)
4781 goto error;
4782 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4783 if (status < 0)
4784 goto error;
4785 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4786 if (status < 0)
4787 goto error;
4788 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4789 if (status < 0)
4790 goto error;
4791 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4792 if (status < 0)
4793 goto error;
4794
4795
4796 /* QAM State Machine (FSM) Thresholds */
4797
4798 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4799 if (status < 0)
4800 goto error;
4801 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4802 if (status < 0)
4803 goto error;
4804 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4805 if (status < 0)
4806 goto error;
4807 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4808 if (status < 0)
4809 goto error;
4810 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4811 if (status < 0)
4812 goto error;
4813 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4814 if (status < 0)
4815 goto error;
4816
4817 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4818 if (status < 0)
4819 goto error;
4820 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4821 if (status < 0)
4822 goto error;
4823 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4824 if (status < 0)
4825 goto error;
4826
4827
4828 /* QAM FSM Tracking Parameters */
4829
4830 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4831 if (status < 0)
4832 goto error;
4833 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4834 if (status < 0)
4835 goto error;
4836 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4837 if (status < 0)
4838 goto error;
4839 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4840 if (status < 0)
4841 goto error;
4842 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4843 if (status < 0)
4844 goto error;
4845 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4846 if (status < 0)
4847 goto error;
4848 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4849 error:
4850 if (status < 0)
4851 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4852
4853 return status;
4854 }
4855
4856 /*============================================================================*/
4857
4858 /**
4859 * \brief QAM128 specific setup
4860 * \param demod: instance of demod.
4861 * \return DRXStatus_t.
4862 */
4863 static int SetQAM128(struct drxk_state *state)
4864 {
4865 int status = 0;
4866
4867 dprintk(1, "\n");
4868 /* QAM Equalizer Setup */
4869 /* Equalizer */
4870 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4871 if (status < 0)
4872 goto error;
4873 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4874 if (status < 0)
4875 goto error;
4876 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4877 if (status < 0)
4878 goto error;
4879 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4880 if (status < 0)
4881 goto error;
4882 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4883 if (status < 0)
4884 goto error;
4885 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4886 if (status < 0)
4887 goto error;
4888
4889 /* Decision Feedback Equalizer */
4890 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
4891 if (status < 0)
4892 goto error;
4893 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
4894 if (status < 0)
4895 goto error;
4896 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
4897 if (status < 0)
4898 goto error;
4899 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
4900 if (status < 0)
4901 goto error;
4902 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
4903 if (status < 0)
4904 goto error;
4905 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4906 if (status < 0)
4907 goto error;
4908
4909 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4910 if (status < 0)
4911 goto error;
4912 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4913 if (status < 0)
4914 goto error;
4915 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4916 if (status < 0)
4917 goto error;
4918
4919
4920 /* QAM Slicer Settings */
4921
4922 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM128);
4923 if (status < 0)
4924 goto error;
4925
4926
4927 /* QAM Loop Controller Coeficients */
4928
4929 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4930 if (status < 0)
4931 goto error;
4932 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4933 if (status < 0)
4934 goto error;
4935 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4936 if (status < 0)
4937 goto error;
4938 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4939 if (status < 0)
4940 goto error;
4941 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4942 if (status < 0)
4943 goto error;
4944 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4945 if (status < 0)
4946 goto error;
4947 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4948 if (status < 0)
4949 goto error;
4950 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4951 if (status < 0)
4952 goto error;
4953
4954 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4955 if (status < 0)
4956 goto error;
4957 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4958 if (status < 0)
4959 goto error;
4960 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4961 if (status < 0)
4962 goto error;
4963 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4964 if (status < 0)
4965 goto error;
4966 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4967 if (status < 0)
4968 goto error;
4969 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4970 if (status < 0)
4971 goto error;
4972 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4973 if (status < 0)
4974 goto error;
4975 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4976 if (status < 0)
4977 goto error;
4978 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
4979 if (status < 0)
4980 goto error;
4981 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4982 if (status < 0)
4983 goto error;
4984 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4985 if (status < 0)
4986 goto error;
4987 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4988 if (status < 0)
4989 goto error;
4990
4991
4992 /* QAM State Machine (FSM) Thresholds */
4993
4994 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
4995 if (status < 0)
4996 goto error;
4997 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4998 if (status < 0)
4999 goto error;
5000 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5001 if (status < 0)
5002 goto error;
5003 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5004 if (status < 0)
5005 goto error;
5006 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
5007 if (status < 0)
5008 goto error;
5009 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
5010 if (status < 0)
5011 goto error;
5012
5013 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5014 if (status < 0)
5015 goto error;
5016 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
5017 if (status < 0)
5018 goto error;
5019
5020 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5021 if (status < 0)
5022 goto error;
5023
5024 /* QAM FSM Tracking Parameters */
5025
5026 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5027 if (status < 0)
5028 goto error;
5029 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
5030 if (status < 0)
5031 goto error;
5032 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
5033 if (status < 0)
5034 goto error;
5035 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
5036 if (status < 0)
5037 goto error;
5038 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
5039 if (status < 0)
5040 goto error;
5041 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
5042 if (status < 0)
5043 goto error;
5044 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
5045 error:
5046 if (status < 0)
5047 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5048
5049 return status;
5050 }
5051
5052 /*============================================================================*/
5053
5054 /**
5055 * \brief QAM256 specific setup
5056 * \param demod: instance of demod.
5057 * \return DRXStatus_t.
5058 */
5059 static int SetQAM256(struct drxk_state *state)
5060 {
5061 int status = 0;
5062
5063 dprintk(1, "\n");
5064 /* QAM Equalizer Setup */
5065 /* Equalizer */
5066 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
5067 if (status < 0)
5068 goto error;
5069 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
5070 if (status < 0)
5071 goto error;
5072 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
5073 if (status < 0)
5074 goto error;
5075 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
5076 if (status < 0)
5077 goto error;
5078 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
5079 if (status < 0)
5080 goto error;
5081 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
5082 if (status < 0)
5083 goto error;
5084
5085 /* Decision Feedback Equalizer */
5086 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
5087 if (status < 0)
5088 goto error;
5089 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
5090 if (status < 0)
5091 goto error;
5092 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
5093 if (status < 0)
5094 goto error;
5095 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
5096 if (status < 0)
5097 goto error;
5098 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
5099 if (status < 0)
5100 goto error;
5101 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
5102 if (status < 0)
5103 goto error;
5104
5105 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
5106 if (status < 0)
5107 goto error;
5108 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
5109 if (status < 0)
5110 goto error;
5111 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
5112 if (status < 0)
5113 goto error;
5114
5115 /* QAM Slicer Settings */
5116
5117 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM256);
5118 if (status < 0)
5119 goto error;
5120
5121
5122 /* QAM Loop Controller Coeficients */
5123
5124 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
5125 if (status < 0)
5126 goto error;
5127 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5128 if (status < 0)
5129 goto error;
5130 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5131 if (status < 0)
5132 goto error;
5133 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5134 if (status < 0)
5135 goto error;
5136 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5137 if (status < 0)
5138 goto error;
5139 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5140 if (status < 0)
5141 goto error;
5142 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5143 if (status < 0)
5144 goto error;
5145 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5146 if (status < 0)
5147 goto error;
5148
5149 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
5150 if (status < 0)
5151 goto error;
5152 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
5153 if (status < 0)
5154 goto error;
5155 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
5156 if (status < 0)
5157 goto error;
5158 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
5159 if (status < 0)
5160 goto error;
5161 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
5162 if (status < 0)
5163 goto error;
5164 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
5165 if (status < 0)
5166 goto error;
5167 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5168 if (status < 0)
5169 goto error;
5170 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5171 if (status < 0)
5172 goto error;
5173 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5174 if (status < 0)
5175 goto error;
5176 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5177 if (status < 0)
5178 goto error;
5179 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5180 if (status < 0)
5181 goto error;
5182 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5183 if (status < 0)
5184 goto error;
5185
5186
5187 /* QAM State Machine (FSM) Thresholds */
5188
5189 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5190 if (status < 0)
5191 goto error;
5192 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5193 if (status < 0)
5194 goto error;
5195 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5196 if (status < 0)
5197 goto error;
5198 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5199 if (status < 0)
5200 goto error;
5201 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5202 if (status < 0)
5203 goto error;
5204 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5205 if (status < 0)
5206 goto error;
5207
5208 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5209 if (status < 0)
5210 goto error;
5211 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
5212 if (status < 0)
5213 goto error;
5214 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5215 if (status < 0)
5216 goto error;
5217
5218
5219 /* QAM FSM Tracking Parameters */
5220
5221 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5222 if (status < 0)
5223 goto error;
5224 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5225 if (status < 0)
5226 goto error;
5227 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5228 if (status < 0)
5229 goto error;
5230 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5231 if (status < 0)
5232 goto error;
5233 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5234 if (status < 0)
5235 goto error;
5236 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5237 if (status < 0)
5238 goto error;
5239 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5240 error:
5241 if (status < 0)
5242 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5243 return status;
5244 }
5245
5246
5247 /*============================================================================*/
5248 /**
5249 * \brief Reset QAM block.
5250 * \param demod: instance of demod.
5251 * \param channel: pointer to channel data.
5252 * \return DRXStatus_t.
5253 */
5254 static int QAMResetQAM(struct drxk_state *state)
5255 {
5256 int status;
5257 u16 cmdResult;
5258
5259 dprintk(1, "\n");
5260 /* Stop QAM comstate->m_exec */
5261 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5262 if (status < 0)
5263 goto error;
5264
5265 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
5266 error:
5267 if (status < 0)
5268 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5269 return status;
5270 }
5271
5272 /*============================================================================*/
5273
5274 /**
5275 * \brief Set QAM symbolrate.
5276 * \param demod: instance of demod.
5277 * \param channel: pointer to channel data.
5278 * \return DRXStatus_t.
5279 */
5280 static int QAMSetSymbolrate(struct drxk_state *state)
5281 {
5282 u32 adcFrequency = 0;
5283 u32 symbFreq = 0;
5284 u32 iqmRcRate = 0;
5285 u16 ratesel = 0;
5286 u32 lcSymbRate = 0;
5287 int status;
5288
5289 dprintk(1, "\n");
5290 /* Select & calculate correct IQM rate */
5291 adcFrequency = (state->m_sysClockFreq * 1000) / 3;
5292 ratesel = 0;
5293 /* printk(KERN_DEBUG "drxk: SR %d\n", state->props.symbol_rate); */
5294 if (state->props.symbol_rate <= 1188750)
5295 ratesel = 3;
5296 else if (state->props.symbol_rate <= 2377500)
5297 ratesel = 2;
5298 else if (state->props.symbol_rate <= 4755000)
5299 ratesel = 1;
5300 status = write16(state, IQM_FD_RATESEL__A, ratesel);
5301 if (status < 0)
5302 goto error;
5303
5304 /*
5305 IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
5306 */
5307 symbFreq = state->props.symbol_rate * (1 << ratesel);
5308 if (symbFreq == 0) {
5309 /* Divide by zero */
5310 status = -EINVAL;
5311 goto error;
5312 }
5313 iqmRcRate = (adcFrequency / symbFreq) * (1 << 21) +
5314 (Frac28a((adcFrequency % symbFreq), symbFreq) >> 7) -
5315 (1 << 23);
5316 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate);
5317 if (status < 0)
5318 goto error;
5319 state->m_iqmRcRate = iqmRcRate;
5320 /*
5321 LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15))
5322 */
5323 symbFreq = state->props.symbol_rate;
5324 if (adcFrequency == 0) {
5325 /* Divide by zero */
5326 status = -EINVAL;
5327 goto error;
5328 }
5329 lcSymbRate = (symbFreq / adcFrequency) * (1 << 12) +
5330 (Frac28a((symbFreq % adcFrequency), adcFrequency) >>
5331 16);
5332 if (lcSymbRate > 511)
5333 lcSymbRate = 511;
5334 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate);
5335
5336 error:
5337 if (status < 0)
5338 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5339 return status;
5340 }
5341
5342 /*============================================================================*/
5343
5344 /**
5345 * \brief Get QAM lock status.
5346 * \param demod: instance of demod.
5347 * \param channel: pointer to channel data.
5348 * \return DRXStatus_t.
5349 */
5350
5351 static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus)
5352 {
5353 int status;
5354 u16 Result[2] = { 0, 0 };
5355
5356 dprintk(1, "\n");
5357 *pLockStatus = NOT_LOCKED;
5358 status = scu_command(state,
5359 SCU_RAM_COMMAND_STANDARD_QAM |
5360 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2,
5361 Result);
5362 if (status < 0)
5363 printk(KERN_ERR "drxk: %s status = %08x\n", __func__, status);
5364
5365 if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) {
5366 /* 0x0000 NOT LOCKED */
5367 } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) {
5368 /* 0x4000 DEMOD LOCKED */
5369 *pLockStatus = DEMOD_LOCK;
5370 } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) {
5371 /* 0x8000 DEMOD + FEC LOCKED (system lock) */
5372 *pLockStatus = MPEG_LOCK;
5373 } else {
5374 /* 0xC000 NEVER LOCKED */
5375 /* (system will never be able to lock to the signal) */
5376 /* TODO: check this, intermediate & standard specific lock states are not
5377 taken into account here */
5378 *pLockStatus = NEVER_LOCK;
5379 }
5380 return status;
5381 }
5382
5383 #define QAM_MIRROR__M 0x03
5384 #define QAM_MIRROR_NORMAL 0x00
5385 #define QAM_MIRRORED 0x01
5386 #define QAM_MIRROR_AUTO_ON 0x02
5387 #define QAM_LOCKRANGE__M 0x10
5388 #define QAM_LOCKRANGE_NORMAL 0x10
5389
5390 static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5391 s32 tunerFreqOffset)
5392 {
5393 int status;
5394 u16 setParamParameters[4] = { 0, 0, 0, 0 };
5395 u16 cmdResult;
5396
5397 dprintk(1, "\n");
5398 /*
5399 * STEP 1: reset demodulator
5400 * resets FEC DI and FEC RS
5401 * resets QAM block
5402 * resets SCU variables
5403 */
5404 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5405 if (status < 0)
5406 goto error;
5407 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5408 if (status < 0)
5409 goto error;
5410 status = QAMResetQAM(state);
5411 if (status < 0)
5412 goto error;
5413
5414 /*
5415 * STEP 2: configure demodulator
5416 * -set params; resets IQM,QAM,FEC HW; initializes some
5417 * SCU variables
5418 */
5419 status = QAMSetSymbolrate(state);
5420 if (status < 0)
5421 goto error;
5422
5423 /* Set params */
5424 switch (state->props.modulation) {
5425 case QAM_256:
5426 state->m_Constellation = DRX_CONSTELLATION_QAM256;
5427 break;
5428 case QAM_AUTO:
5429 case QAM_64:
5430 state->m_Constellation = DRX_CONSTELLATION_QAM64;
5431 break;
5432 case QAM_16:
5433 state->m_Constellation = DRX_CONSTELLATION_QAM16;
5434 break;
5435 case QAM_32:
5436 state->m_Constellation = DRX_CONSTELLATION_QAM32;
5437 break;
5438 case QAM_128:
5439 state->m_Constellation = DRX_CONSTELLATION_QAM128;
5440 break;
5441 default:
5442 status = -EINVAL;
5443 break;
5444 }
5445 if (status < 0)
5446 goto error;
5447 setParamParameters[0] = state->m_Constellation; /* modulation */
5448 setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
5449 if (state->m_OperationMode == OM_QAM_ITU_C)
5450 setParamParameters[2] = QAM_TOP_ANNEX_C;
5451 else
5452 setParamParameters[2] = QAM_TOP_ANNEX_A;
5453 setParamParameters[3] |= (QAM_MIRROR_AUTO_ON);
5454 /* Env parameters */
5455 /* check for LOCKRANGE Extented */
5456 /* setParamParameters[3] |= QAM_LOCKRANGE_NORMAL; */
5457
5458 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 4, setParamParameters, 1, &cmdResult);
5459 if (status < 0) {
5460 /* Fall-back to the simpler call */
5461 if (state->m_OperationMode == OM_QAM_ITU_C)
5462 setParamParameters[0] = QAM_TOP_ANNEX_C;
5463 else
5464 setParamParameters[0] = QAM_TOP_ANNEX_A;
5465 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 1, setParamParameters, 1, &cmdResult);
5466 if (status < 0)
5467 goto error;
5468
5469 setParamParameters[0] = state->m_Constellation; /* modulation */
5470 setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
5471 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 2, setParamParameters, 1, &cmdResult);
5472 }
5473 if (status < 0)
5474 goto error;
5475
5476 /*
5477 * STEP 3: enable the system in a mode where the ADC provides valid
5478 * signal setup modulation independent registers
5479 */
5480 #if 0
5481 status = SetFrequency(channel, tunerFreqOffset));
5482 if (status < 0)
5483 goto error;
5484 #endif
5485 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
5486 if (status < 0)
5487 goto error;
5488
5489 /* Setup BER measurement */
5490 status = SetQAMMeasurement(state, state->m_Constellation, state->props.symbol_rate);
5491 if (status < 0)
5492 goto error;
5493
5494 /* Reset default values */
5495 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5496 if (status < 0)
5497 goto error;
5498 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5499 if (status < 0)
5500 goto error;
5501
5502 /* Reset default LC values */
5503 status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
5504 if (status < 0)
5505 goto error;
5506 status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
5507 if (status < 0)
5508 goto error;
5509 status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5510 if (status < 0)
5511 goto error;
5512 status = write16(state, QAM_LC_MODE__A, 7);
5513 if (status < 0)
5514 goto error;
5515
5516 status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
5517 if (status < 0)
5518 goto error;
5519 status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
5520 if (status < 0)
5521 goto error;
5522 status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
5523 if (status < 0)
5524 goto error;
5525 status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
5526 if (status < 0)
5527 goto error;
5528 status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
5529 if (status < 0)
5530 goto error;
5531 status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
5532 if (status < 0)
5533 goto error;
5534 status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
5535 if (status < 0)
5536 goto error;
5537 status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
5538 if (status < 0)
5539 goto error;
5540 status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
5541 if (status < 0)
5542 goto error;
5543 status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
5544 if (status < 0)
5545 goto error;
5546 status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
5547 if (status < 0)
5548 goto error;
5549 status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
5550 if (status < 0)
5551 goto error;
5552 status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
5553 if (status < 0)
5554 goto error;
5555 status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
5556 if (status < 0)
5557 goto error;
5558 status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
5559 if (status < 0)
5560 goto error;
5561
5562 /* Mirroring, QAM-block starting point not inverted */
5563 status = write16(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS);
5564 if (status < 0)
5565 goto error;
5566
5567 /* Halt SCU to enable safe non-atomic accesses */
5568 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5569 if (status < 0)
5570 goto error;
5571
5572 /* STEP 4: modulation specific setup */
5573 switch (state->props.modulation) {
5574 case QAM_16:
5575 status = SetQAM16(state);
5576 break;
5577 case QAM_32:
5578 status = SetQAM32(state);
5579 break;
5580 case QAM_AUTO:
5581 case QAM_64:
5582 status = SetQAM64(state);
5583 break;
5584 case QAM_128:
5585 status = SetQAM128(state);
5586 break;
5587 case QAM_256:
5588 status = SetQAM256(state);
5589 break;
5590 default:
5591 status = -EINVAL;
5592 break;
5593 }
5594 if (status < 0)
5595 goto error;
5596
5597 /* Activate SCU to enable SCU commands */
5598 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5599 if (status < 0)
5600 goto error;
5601
5602 /* Re-configure MPEG output, requires knowledge of channel bitrate */
5603 /* extAttr->currentChannel.modulation = channel->modulation; */
5604 /* extAttr->currentChannel.symbolrate = channel->symbolrate; */
5605 status = MPEGTSDtoSetup(state, state->m_OperationMode);
5606 if (status < 0)
5607 goto error;
5608
5609 /* Start processes */
5610 status = MPEGTSStart(state);
5611 if (status < 0)
5612 goto error;
5613 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
5614 if (status < 0)
5615 goto error;
5616 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5617 if (status < 0)
5618 goto error;
5619 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5620 if (status < 0)
5621 goto error;
5622
5623 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
5624 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
5625 if (status < 0)
5626 goto error;
5627
5628 /* update global DRXK data container */
5629 /*? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */
5630
5631 error:
5632 if (status < 0)
5633 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5634 return status;
5635 }
5636
5637 static int SetQAMStandard(struct drxk_state *state,
5638 enum OperationMode oMode)
5639 {
5640 int status;
5641 #ifdef DRXK_QAM_TAPS
5642 #define DRXK_QAMA_TAPS_SELECT
5643 #include "drxk_filters.h"
5644 #undef DRXK_QAMA_TAPS_SELECT
5645 #endif
5646
5647 dprintk(1, "\n");
5648
5649 /* added antenna switch */
5650 SwitchAntennaToQAM(state);
5651
5652 /* Ensure correct power-up mode */
5653 status = PowerUpQAM(state);
5654 if (status < 0)
5655 goto error;
5656 /* Reset QAM block */
5657 status = QAMResetQAM(state);
5658 if (status < 0)
5659 goto error;
5660
5661 /* Setup IQM */
5662
5663 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
5664 if (status < 0)
5665 goto error;
5666 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5667 if (status < 0)
5668 goto error;
5669
5670 /* Upload IQM Channel Filter settings by
5671 boot loader from ROM table */
5672 switch (oMode) {
5673 case OM_QAM_ITU_A:
5674 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5675 break;
5676 case OM_QAM_ITU_C:
5677 status = BLDirectCmd(state, IQM_CF_TAP_RE0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5678 if (status < 0)
5679 goto error;
5680 status = BLDirectCmd(state, IQM_CF_TAP_IM0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5681 break;
5682 default:
5683 status = -EINVAL;
5684 }
5685 if (status < 0)
5686 goto error;
5687
5688 status = write16(state, IQM_CF_OUT_ENA__A, (1 << IQM_CF_OUT_ENA_QAM__B));
5689 if (status < 0)
5690 goto error;
5691 status = write16(state, IQM_CF_SYMMETRIC__A, 0);
5692 if (status < 0)
5693 goto error;
5694 status = write16(state, IQM_CF_MIDTAP__A, ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
5695 if (status < 0)
5696 goto error;
5697
5698 status = write16(state, IQM_RC_STRETCH__A, 21);
5699 if (status < 0)
5700 goto error;
5701 status = write16(state, IQM_AF_CLP_LEN__A, 0);
5702 if (status < 0)
5703 goto error;
5704 status = write16(state, IQM_AF_CLP_TH__A, 448);
5705 if (status < 0)
5706 goto error;
5707 status = write16(state, IQM_AF_SNS_LEN__A, 0);
5708 if (status < 0)
5709 goto error;
5710 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
5711 if (status < 0)
5712 goto error;
5713
5714 status = write16(state, IQM_FS_ADJ_SEL__A, 1);
5715 if (status < 0)
5716 goto error;
5717 status = write16(state, IQM_RC_ADJ_SEL__A, 1);
5718 if (status < 0)
5719 goto error;
5720 status = write16(state, IQM_CF_ADJ_SEL__A, 1);
5721 if (status < 0)
5722 goto error;
5723 status = write16(state, IQM_AF_UPD_SEL__A, 0);
5724 if (status < 0)
5725 goto error;
5726
5727 /* IQM Impulse Noise Processing Unit */
5728 status = write16(state, IQM_CF_CLP_VAL__A, 500);
5729 if (status < 0)
5730 goto error;
5731 status = write16(state, IQM_CF_DATATH__A, 1000);
5732 if (status < 0)
5733 goto error;
5734 status = write16(state, IQM_CF_BYPASSDET__A, 1);
5735 if (status < 0)
5736 goto error;
5737 status = write16(state, IQM_CF_DET_LCT__A, 0);
5738 if (status < 0)
5739 goto error;
5740 status = write16(state, IQM_CF_WND_LEN__A, 1);
5741 if (status < 0)
5742 goto error;
5743 status = write16(state, IQM_CF_PKDTH__A, 1);
5744 if (status < 0)
5745 goto error;
5746 status = write16(state, IQM_AF_INC_BYPASS__A, 1);
5747 if (status < 0)
5748 goto error;
5749
5750 /* turn on IQMAF. Must be done before setAgc**() */
5751 status = SetIqmAf(state, true);
5752 if (status < 0)
5753 goto error;
5754 status = write16(state, IQM_AF_START_LOCK__A, 0x01);
5755 if (status < 0)
5756 goto error;
5757
5758 /* IQM will not be reset from here, sync ADC and update/init AGC */
5759 status = ADCSynchronization(state);
5760 if (status < 0)
5761 goto error;
5762
5763 /* Set the FSM step period */
5764 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
5765 if (status < 0)
5766 goto error;
5767
5768 /* Halt SCU to enable safe non-atomic accesses */
5769 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5770 if (status < 0)
5771 goto error;
5772
5773 /* No more resets of the IQM, current standard correctly set =>
5774 now AGCs can be configured. */
5775
5776 status = InitAGC(state, true);
5777 if (status < 0)
5778 goto error;
5779 status = SetPreSaw(state, &(state->m_qamPreSawCfg));
5780 if (status < 0)
5781 goto error;
5782
5783 /* Configure AGC's */
5784 status = SetAgcRf(state, &(state->m_qamRfAgcCfg), true);
5785 if (status < 0)
5786 goto error;
5787 status = SetAgcIf(state, &(state->m_qamIfAgcCfg), true);
5788 if (status < 0)
5789 goto error;
5790
5791 /* Activate SCU to enable SCU commands */
5792 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5793 error:
5794 if (status < 0)
5795 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5796 return status;
5797 }
5798
5799 static int WriteGPIO(struct drxk_state *state)
5800 {
5801 int status;
5802 u16 value = 0;
5803
5804 dprintk(1, "\n");
5805 /* stop lock indicator process */
5806 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5807 if (status < 0)
5808 goto error;
5809
5810 /* Write magic word to enable pdr reg write */
5811 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5812 if (status < 0)
5813 goto error;
5814
5815 if (state->m_hasSAWSW) {
5816 if (state->UIO_mask & 0x0001) { /* UIO-1 */
5817 /* write to io pad configuration register - output mode */
5818 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg);
5819 if (status < 0)
5820 goto error;
5821
5822 /* use corresponding bit in io data output registar */
5823 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5824 if (status < 0)
5825 goto error;
5826 if ((state->m_GPIO & 0x0001) == 0)
5827 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */
5828 else
5829 value |= 0x8000; /* write one to 15th bit - 1st UIO */
5830 /* write back to io data output register */
5831 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5832 if (status < 0)
5833 goto error;
5834 }
5835 if (state->UIO_mask & 0x0002) { /* UIO-2 */
5836 /* write to io pad configuration register - output mode */
5837 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg);
5838 if (status < 0)
5839 goto error;
5840
5841 /* use corresponding bit in io data output registar */
5842 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5843 if (status < 0)
5844 goto error;
5845 if ((state->m_GPIO & 0x0002) == 0)
5846 value &= 0xBFFF; /* write zero to 14th bit - 2st UIO */
5847 else
5848 value |= 0x4000; /* write one to 14th bit - 2st UIO */
5849 /* write back to io data output register */
5850 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5851 if (status < 0)
5852 goto error;
5853 }
5854 if (state->UIO_mask & 0x0004) { /* UIO-3 */
5855 /* write to io pad configuration register - output mode */
5856 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg);
5857 if (status < 0)
5858 goto error;
5859
5860 /* use corresponding bit in io data output registar */
5861 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5862 if (status < 0)
5863 goto error;
5864 if ((state->m_GPIO & 0x0004) == 0)
5865 value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */
5866 else
5867 value |= 0x0004; /* write one to 2nd bit - 3rd UIO */
5868 /* write back to io data output register */
5869 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5870 if (status < 0)
5871 goto error;
5872 }
5873 }
5874 /* Write magic word to disable pdr reg write */
5875 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
5876 error:
5877 if (status < 0)
5878 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5879 return status;
5880 }
5881
5882 static int SwitchAntennaToQAM(struct drxk_state *state)
5883 {
5884 int status = 0;
5885 bool gpio_state;
5886
5887 dprintk(1, "\n");
5888
5889 if (!state->antenna_gpio)
5890 return 0;
5891
5892 gpio_state = state->m_GPIO & state->antenna_gpio;
5893
5894 if (state->antenna_dvbt ^ gpio_state) {
5895 /* Antenna is on DVB-T mode. Switch */
5896 if (state->antenna_dvbt)
5897 state->m_GPIO &= ~state->antenna_gpio;
5898 else
5899 state->m_GPIO |= state->antenna_gpio;
5900 status = WriteGPIO(state);
5901 }
5902 if (status < 0)
5903 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5904 return status;
5905 }
5906
5907 static int SwitchAntennaToDVBT(struct drxk_state *state)
5908 {
5909 int status = 0;
5910 bool gpio_state;
5911
5912 dprintk(1, "\n");
5913
5914 if (!state->antenna_gpio)
5915 return 0;
5916
5917 gpio_state = state->m_GPIO & state->antenna_gpio;
5918
5919 if (!(state->antenna_dvbt ^ gpio_state)) {
5920 /* Antenna is on DVB-C mode. Switch */
5921 if (state->antenna_dvbt)
5922 state->m_GPIO |= state->antenna_gpio;
5923 else
5924 state->m_GPIO &= ~state->antenna_gpio;
5925 status = WriteGPIO(state);
5926 }
5927 if (status < 0)
5928 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5929 return status;
5930 }
5931
5932
5933 static int PowerDownDevice(struct drxk_state *state)
5934 {
5935 /* Power down to requested mode */
5936 /* Backup some register settings */
5937 /* Set pins with possible pull-ups connected to them in input mode */
5938 /* Analog power down */
5939 /* ADC power down */
5940 /* Power down device */
5941 int status;
5942
5943 dprintk(1, "\n");
5944 if (state->m_bPDownOpenBridge) {
5945 /* Open I2C bridge before power down of DRXK */
5946 status = ConfigureI2CBridge(state, true);
5947 if (status < 0)
5948 goto error;
5949 }
5950 /* driver 0.9.0 */
5951 status = DVBTEnableOFDMTokenRing(state, false);
5952 if (status < 0)
5953 goto error;
5954
5955 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK);
5956 if (status < 0)
5957 goto error;
5958 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
5959 if (status < 0)
5960 goto error;
5961 state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
5962 status = HI_CfgCommand(state);
5963 error:
5964 if (status < 0)
5965 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5966
5967 return status;
5968 }
5969
5970 static int load_microcode(struct drxk_state *state, const char *mc_name)
5971 {
5972 const struct firmware *fw = NULL;
5973 int err = 0;
5974
5975 dprintk(1, "\n");
5976
5977 err = request_firmware(&fw, mc_name, state->i2c->dev.parent);
5978 if (err < 0) {
5979 printk(KERN_ERR
5980 "drxk: Could not load firmware file %s.\n", mc_name);
5981 printk(KERN_INFO
5982 "drxk: Copy %s to your hotplug directory!\n", mc_name);
5983 return err;
5984 }
5985 err = DownloadMicrocode(state, fw->data, fw->size);
5986 release_firmware(fw);
5987 return err;
5988 }
5989
5990 static int init_drxk(struct drxk_state *state)
5991 {
5992 int status = 0;
5993 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
5994 u16 driverVersion;
5995
5996 dprintk(1, "\n");
5997 if ((state->m_DrxkState == DRXK_UNINITIALIZED)) {
5998 status = PowerUpDevice(state);
5999 if (status < 0)
6000 goto error;
6001 status = DRXX_Open(state);
6002 if (status < 0)
6003 goto error;
6004 /* Soft reset of OFDM-, sys- and osc-clockdomain */
6005 status = write16(state, SIO_CC_SOFT_RST__A, SIO_CC_SOFT_RST_OFDM__M | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M);
6006 if (status < 0)
6007 goto error;
6008 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6009 if (status < 0)
6010 goto error;
6011 /* TODO is this needed, if yes how much delay in worst case scenario */
6012 msleep(1);
6013 state->m_DRXK_A3_PATCH_CODE = true;
6014 status = GetDeviceCapabilities(state);
6015 if (status < 0)
6016 goto error;
6017
6018 /* Bridge delay, uses oscilator clock */
6019 /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */
6020 /* SDA brdige delay */
6021 state->m_HICfgBridgeDelay =
6022 (u16) ((state->m_oscClockFreq / 1000) *
6023 HI_I2C_BRIDGE_DELAY) / 1000;
6024 /* Clipping */
6025 if (state->m_HICfgBridgeDelay >
6026 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) {
6027 state->m_HICfgBridgeDelay =
6028 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
6029 }
6030 /* SCL bridge delay, same as SDA for now */
6031 state->m_HICfgBridgeDelay +=
6032 state->m_HICfgBridgeDelay <<
6033 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
6034
6035 status = InitHI(state);
6036 if (status < 0)
6037 goto error;
6038 /* disable various processes */
6039 #if NOA1ROM
6040 if (!(state->m_DRXK_A1_ROM_CODE)
6041 && !(state->m_DRXK_A2_ROM_CODE))
6042 #endif
6043 {
6044 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
6045 if (status < 0)
6046 goto error;
6047 }
6048
6049 /* disable MPEG port */
6050 status = MPEGTSDisable(state);
6051 if (status < 0)
6052 goto error;
6053
6054 /* Stop AUD and SCU */
6055 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
6056 if (status < 0)
6057 goto error;
6058 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
6059 if (status < 0)
6060 goto error;
6061
6062 /* enable token-ring bus through OFDM block for possible ucode upload */
6063 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
6064 if (status < 0)
6065 goto error;
6066
6067 /* include boot loader section */
6068 status = write16(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE);
6069 if (status < 0)
6070 goto error;
6071 status = BLChainCmd(state, 0, 6, 100);
6072 if (status < 0)
6073 goto error;
6074
6075 if (!state->microcode_name)
6076 load_microcode(state, "drxk_a3.mc");
6077 else
6078 load_microcode(state, state->microcode_name);
6079
6080 /* disable token-ring bus through OFDM block for possible ucode upload */
6081 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
6082 if (status < 0)
6083 goto error;
6084
6085 /* Run SCU for a little while to initialize microcode version numbers */
6086 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6087 if (status < 0)
6088 goto error;
6089 status = DRXX_Open(state);
6090 if (status < 0)
6091 goto error;
6092 /* added for test */
6093 msleep(30);
6094
6095 powerMode = DRXK_POWER_DOWN_OFDM;
6096 status = CtrlPowerMode(state, &powerMode);
6097 if (status < 0)
6098 goto error;
6099
6100 /* Stamp driver version number in SCU data RAM in BCD code
6101 Done to enable field application engineers to retreive drxdriver version
6102 via I2C from SCU RAM.
6103 Not using SCU command interface for SCU register access since no
6104 microcode may be present.
6105 */
6106 driverVersion =
6107 (((DRXK_VERSION_MAJOR / 100) % 10) << 12) +
6108 (((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
6109 ((DRXK_VERSION_MAJOR % 10) << 4) +
6110 (DRXK_VERSION_MINOR % 10);
6111 status = write16(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion);
6112 if (status < 0)
6113 goto error;
6114 driverVersion =
6115 (((DRXK_VERSION_PATCH / 1000) % 10) << 12) +
6116 (((DRXK_VERSION_PATCH / 100) % 10) << 8) +
6117 (((DRXK_VERSION_PATCH / 10) % 10) << 4) +
6118 (DRXK_VERSION_PATCH % 10);
6119 status = write16(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion);
6120 if (status < 0)
6121 goto error;
6122
6123 printk(KERN_INFO "DRXK driver version %d.%d.%d\n",
6124 DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR,
6125 DRXK_VERSION_PATCH);
6126
6127 /* Dirty fix of default values for ROM/PATCH microcode
6128 Dirty because this fix makes it impossible to setup suitable values
6129 before calling DRX_Open. This solution requires changes to RF AGC speed
6130 to be done via the CTRL function after calling DRX_Open */
6131
6132 /* m_dvbtRfAgcCfg.speed = 3; */
6133
6134 /* Reset driver debug flags to 0 */
6135 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
6136 if (status < 0)
6137 goto error;
6138 /* driver 0.9.0 */
6139 /* Setup FEC OC:
6140 NOTE: No more full FEC resets allowed afterwards!! */
6141 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6142 if (status < 0)
6143 goto error;
6144 /* MPEGTS functions are still the same */
6145 status = MPEGTSDtoInit(state);
6146 if (status < 0)
6147 goto error;
6148 status = MPEGTSStop(state);
6149 if (status < 0)
6150 goto error;
6151 status = MPEGTSConfigurePolarity(state);
6152 if (status < 0)
6153 goto error;
6154 status = MPEGTSConfigurePins(state, state->m_enableMPEGOutput);
6155 if (status < 0)
6156 goto error;
6157 /* added: configure GPIO */
6158 status = WriteGPIO(state);
6159 if (status < 0)
6160 goto error;
6161
6162 state->m_DrxkState = DRXK_STOPPED;
6163
6164 if (state->m_bPowerDown) {
6165 status = PowerDownDevice(state);
6166 if (status < 0)
6167 goto error;
6168 state->m_DrxkState = DRXK_POWERED_DOWN;
6169 } else
6170 state->m_DrxkState = DRXK_STOPPED;
6171 }
6172 error:
6173 if (status < 0)
6174 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
6175
6176 return status;
6177 }
6178
6179 static void drxk_release(struct dvb_frontend *fe)
6180 {
6181 struct drxk_state *state = fe->demodulator_priv;
6182
6183 dprintk(1, "\n");
6184 kfree(state);
6185 }
6186
6187 static int drxk_sleep(struct dvb_frontend *fe)
6188 {
6189 struct drxk_state *state = fe->demodulator_priv;
6190
6191 dprintk(1, "\n");
6192 ShutDown(state);
6193 return 0;
6194 }
6195
6196 static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
6197 {
6198 struct drxk_state *state = fe->demodulator_priv;
6199
6200 dprintk(1, "%s\n", enable ? "enable" : "disable");
6201 return ConfigureI2CBridge(state, enable ? true : false);
6202 }
6203
6204 static int drxk_set_parameters(struct dvb_frontend *fe)
6205 {
6206 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6207 u32 delsys = p->delivery_system, old_delsys;
6208 struct drxk_state *state = fe->demodulator_priv;
6209 u32 IF;
6210
6211 dprintk(1, "\n");
6212
6213 if (!fe->ops.tuner_ops.get_if_frequency) {
6214 printk(KERN_ERR
6215 "drxk: Error: get_if_frequency() not defined at tuner. Can't work without it!\n");
6216 return -EINVAL;
6217 }
6218
6219 if (fe->ops.i2c_gate_ctrl)
6220 fe->ops.i2c_gate_ctrl(fe, 1);
6221 if (fe->ops.tuner_ops.set_params)
6222 fe->ops.tuner_ops.set_params(fe);
6223 if (fe->ops.i2c_gate_ctrl)
6224 fe->ops.i2c_gate_ctrl(fe, 0);
6225
6226 old_delsys = state->props.delivery_system;
6227 state->props = *p;
6228
6229 if (old_delsys != delsys) {
6230 ShutDown(state);
6231 switch (delsys) {
6232 case SYS_DVBC_ANNEX_A:
6233 case SYS_DVBC_ANNEX_C:
6234 if (!state->m_hasDVBC)
6235 return -EINVAL;
6236 state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? true : false;
6237 if (state->m_itut_annex_c)
6238 SetOperationMode(state, OM_QAM_ITU_C);
6239 else
6240 SetOperationMode(state, OM_QAM_ITU_A);
6241 break;
6242 case SYS_DVBT:
6243 if (!state->m_hasDVBT)
6244 return -EINVAL;
6245 SetOperationMode(state, OM_DVBT);
6246 break;
6247 default:
6248 return -EINVAL;
6249 }
6250 }
6251
6252 fe->ops.tuner_ops.get_if_frequency(fe, &IF);
6253 Start(state, 0, IF);
6254
6255 /* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */
6256
6257 return 0;
6258 }
6259
6260 static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status)
6261 {
6262 struct drxk_state *state = fe->demodulator_priv;
6263 u32 stat;
6264
6265 dprintk(1, "\n");
6266 *status = 0;
6267 GetLockStatus(state, &stat, 0);
6268 if (stat == MPEG_LOCK)
6269 *status |= 0x1f;
6270 if (stat == FEC_LOCK)
6271 *status |= 0x0f;
6272 if (stat == DEMOD_LOCK)
6273 *status |= 0x07;
6274 return 0;
6275 }
6276
6277 static int drxk_read_ber(struct dvb_frontend *fe, u32 *ber)
6278 {
6279 dprintk(1, "\n");
6280
6281 *ber = 0;
6282 return 0;
6283 }
6284
6285 static int drxk_read_signal_strength(struct dvb_frontend *fe,
6286 u16 *strength)
6287 {
6288 struct drxk_state *state = fe->demodulator_priv;
6289 u32 val = 0;
6290
6291 dprintk(1, "\n");
6292 ReadIFAgc(state, &val);
6293 *strength = val & 0xffff;
6294 return 0;
6295 }
6296
6297 static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr)
6298 {
6299 struct drxk_state *state = fe->demodulator_priv;
6300 s32 snr2;
6301
6302 dprintk(1, "\n");
6303 GetSignalToNoise(state, &snr2);
6304 *snr = snr2 & 0xffff;
6305 return 0;
6306 }
6307
6308 static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
6309 {
6310 struct drxk_state *state = fe->demodulator_priv;
6311 u16 err;
6312
6313 dprintk(1, "\n");
6314 DVBTQAMGetAccPktErr(state, &err);
6315 *ucblocks = (u32) err;
6316 return 0;
6317 }
6318
6319 static int drxk_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings
6320 *sets)
6321 {
6322 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6323
6324 dprintk(1, "\n");
6325 switch (p->delivery_system) {
6326 case SYS_DVBC_ANNEX_A:
6327 case SYS_DVBC_ANNEX_C:
6328 sets->min_delay_ms = 3000;
6329 sets->max_drift = 0;
6330 sets->step_size = 0;
6331 return 0;
6332 default:
6333 /*
6334 * For DVB-T, let it use the default DVB core way, that is:
6335 * fepriv->step_size = fe->ops.info.frequency_stepsize * 2
6336 */
6337 return -EINVAL;
6338 }
6339 }
6340
6341 static struct dvb_frontend_ops drxk_ops = {
6342 /* .delsys will be filled dynamically */
6343 .info = {
6344 .name = "DRXK",
6345 .frequency_min = 47000000,
6346 .frequency_max = 865000000,
6347 /* For DVB-C */
6348 .symbol_rate_min = 870000,
6349 .symbol_rate_max = 11700000,
6350 /* For DVB-T */
6351 .frequency_stepsize = 166667,
6352
6353 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
6354 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO |
6355 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
6356 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_MUTE_TS |
6357 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
6358 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO
6359 },
6360
6361 .release = drxk_release,
6362 .sleep = drxk_sleep,
6363 .i2c_gate_ctrl = drxk_gate_ctrl,
6364
6365 .set_frontend = drxk_set_parameters,
6366 .get_tune_settings = drxk_get_tune_settings,
6367
6368 .read_status = drxk_read_status,
6369 .read_ber = drxk_read_ber,
6370 .read_signal_strength = drxk_read_signal_strength,
6371 .read_snr = drxk_read_snr,
6372 .read_ucblocks = drxk_read_ucblocks,
6373 };
6374
6375 struct dvb_frontend *drxk_attach(const struct drxk_config *config,
6376 struct i2c_adapter *i2c)
6377 {
6378 int n;
6379
6380 struct drxk_state *state = NULL;
6381 u8 adr = config->adr;
6382
6383 dprintk(1, "\n");
6384 state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL);
6385 if (!state)
6386 return NULL;
6387
6388 state->i2c = i2c;
6389 state->demod_address = adr;
6390 state->single_master = config->single_master;
6391 state->microcode_name = config->microcode_name;
6392 state->no_i2c_bridge = config->no_i2c_bridge;
6393 state->antenna_gpio = config->antenna_gpio;
6394 state->antenna_dvbt = config->antenna_dvbt;
6395 state->m_ChunkSize = config->chunk_size;
6396
6397 if (config->parallel_ts)
6398 state->m_enableParallel = true;
6399 else
6400 state->m_enableParallel = false;
6401
6402 /* NOTE: as more UIO bits will be used, add them to the mask */
6403 state->UIO_mask = config->antenna_gpio;
6404
6405 /* Default gpio to DVB-C */
6406 if (!state->antenna_dvbt && state->antenna_gpio)
6407 state->m_GPIO |= state->antenna_gpio;
6408 else
6409 state->m_GPIO &= ~state->antenna_gpio;
6410
6411 mutex_init(&state->mutex);
6412
6413 memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops));
6414 state->frontend.demodulator_priv = state;
6415
6416 init_state(state);
6417 if (init_drxk(state) < 0)
6418 goto error;
6419
6420 /* Initialize the supported delivery systems */
6421 n = 0;
6422 if (state->m_hasDVBC) {
6423 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A;
6424 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C;
6425 strlcat(state->frontend.ops.info.name, " DVB-C",
6426 sizeof(state->frontend.ops.info.name));
6427 }
6428 if (state->m_hasDVBT) {
6429 state->frontend.ops.delsys[n++] = SYS_DVBT;
6430 strlcat(state->frontend.ops.info.name, " DVB-T",
6431 sizeof(state->frontend.ops.info.name));
6432 }
6433
6434 printk(KERN_INFO "drxk: frontend initialized.\n");
6435 return &state->frontend;
6436
6437 error:
6438 printk(KERN_ERR "drxk: not found\n");
6439 kfree(state);
6440 return NULL;
6441 }
6442 EXPORT_SYMBOL(drxk_attach);
6443
6444 MODULE_DESCRIPTION("DRX-K driver");
6445 MODULE_AUTHOR("Ralph Metzler");
6446 MODULE_LICENSE("GPL");