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Merge tag 'v3.3.7' into 3.3/master
[zen-stable.git] / drivers / media / dvb / frontends / stb0899_algo.c
blob117a56926dcad041316a53f4ea47ed3c7263505f
1 /*
2 STB0899 Multistandard Frontend driver
3 Copyright (C) Manu Abraham (abraham.manu@gmail.com)
4
5 Copyright (C) ST Microelectronics
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22 #include "stb0899_drv.h"
23 #include "stb0899_priv.h"
24 #include "stb0899_reg.h"
25
26 static inline u32 stb0899_do_div(u64 n, u32 d)
27 {
28 /* wrap do_div() for ease of use */
29
30 do_div(n, d);
31 return n;
32 }
33
34 #if 0
35 /* These functions are currently unused */
36 /*
37 * stb0899_calc_srate
38 * Compute symbol rate
39 */
40 static u32 stb0899_calc_srate(u32 master_clk, u8 *sfr)
41 {
42 u64 tmp;
43
44 /* srate = (SFR * master_clk) >> 20 */
45
46 /* sfr is of size 20 bit, stored with an offset of 4 bit */
47 tmp = (((u32)sfr[0]) << 16) | (((u32)sfr[1]) << 8) | sfr[2];
48 tmp &= ~0xf;
49 tmp *= master_clk;
50 tmp >>= 24;
51
52 return tmp;
53 }
54
55 /*
56 * stb0899_get_srate
57 * Get the current symbol rate
58 */
59 static u32 stb0899_get_srate(struct stb0899_state *state)
60 {
61 struct stb0899_internal *internal = &state->internal;
62 u8 sfr[3];
63
64 stb0899_read_regs(state, STB0899_SFRH, sfr, 3);
65
66 return stb0899_calc_srate(internal->master_clk, sfr);
67 }
68 #endif
69
70 /*
71 * stb0899_set_srate
72 * Set symbol frequency
73 * MasterClock: master clock frequency (hz)
74 * SymbolRate: symbol rate (bauds)
75 * return symbol frequency
76 */
77 static u32 stb0899_set_srate(struct stb0899_state *state, u32 master_clk, u32 srate)
78 {
79 u32 tmp;
80 u8 sfr[3];
81
82 dprintk(state->verbose, FE_DEBUG, 1, "-->");
83 /*
84 * in order to have the maximum precision, the symbol rate entered into
85 * the chip is computed as the closest value of the "true value".
86 * In this purpose, the symbol rate value is rounded (1 is added on the bit
87 * below the LSB )
88 *
89 * srate = (SFR * master_clk) >> 20
90 * <=>
91 * SFR = srate << 20 / master_clk
92 *
93 * rounded:
94 * SFR = (srate << 21 + master_clk) / (2 * master_clk)
95 *
96 * stored as 20 bit number with an offset of 4 bit:
97 * sfr = SFR << 4;
98 */
99
100 tmp = stb0899_do_div((((u64)srate) << 21) + master_clk, 2 * master_clk);
101 tmp <<= 4;
102
103 sfr[0] = tmp >> 16;
104 sfr[1] = tmp >> 8;
105 sfr[2] = tmp;
106
107 stb0899_write_regs(state, STB0899_SFRH, sfr, 3);
108
109 return srate;
110 }
111
112 /*
113 * stb0899_calc_derot_time
114 * Compute the amount of time needed by the derotator to lock
115 * SymbolRate: Symbol rate
116 * return: derotator time constant (ms)
117 */
118 static long stb0899_calc_derot_time(long srate)
119 {
120 if (srate > 0)
121 return (100000 / (srate / 1000));
122 else
123 return 0;
124 }
125
126 /*
127 * stb0899_carr_width
128 * Compute the width of the carrier
129 * return: width of carrier (kHz or Mhz)
130 */
131 long stb0899_carr_width(struct stb0899_state *state)
132 {
133 struct stb0899_internal *internal = &state->internal;
134
135 return (internal->srate + (internal->srate * internal->rolloff) / 100);
136 }
137
138 /*
139 * stb0899_first_subrange
140 * Compute the first subrange of the search
141 */
142 static void stb0899_first_subrange(struct stb0899_state *state)
143 {
144 struct stb0899_internal *internal = &state->internal;
145 struct stb0899_params *params = &state->params;
146 struct stb0899_config *config = state->config;
147
148 int range = 0;
149 u32 bandwidth = 0;
150
151 if (config->tuner_get_bandwidth) {
152 stb0899_i2c_gate_ctrl(&state->frontend, 1);
153 config->tuner_get_bandwidth(&state->frontend, &bandwidth);
154 stb0899_i2c_gate_ctrl(&state->frontend, 0);
155 range = bandwidth - stb0899_carr_width(state) / 2;
156 }
157
158 if (range > 0)
159 internal->sub_range = min(internal->srch_range, range);
160 else
161 internal->sub_range = 0;
162
163 internal->freq = params->freq;
164 internal->tuner_offst = 0L;
165 internal->sub_dir = 1;
166 }
167
168 /*
169 * stb0899_check_tmg
170 * check for timing lock
171 * internal.Ttiming: time to wait for loop lock
172 */
173 static enum stb0899_status stb0899_check_tmg(struct stb0899_state *state)
174 {
175 struct stb0899_internal *internal = &state->internal;
176 int lock;
177 u8 reg;
178 s8 timing;
179
180 msleep(internal->t_derot);
181
182 stb0899_write_reg(state, STB0899_RTF, 0xf2);
183 reg = stb0899_read_reg(state, STB0899_TLIR);
184 lock = STB0899_GETFIELD(TLIR_TMG_LOCK_IND, reg);
185 timing = stb0899_read_reg(state, STB0899_RTF);
186
187 if (lock >= 42) {
188 if ((lock > 48) && (abs(timing) >= 110)) {
189 internal->status = ANALOGCARRIER;
190 dprintk(state->verbose, FE_DEBUG, 1, "-->ANALOG Carrier !");
191 } else {
192 internal->status = TIMINGOK;
193 dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK !");
194 }
195 } else {
196 internal->status = NOTIMING;
197 dprintk(state->verbose, FE_DEBUG, 1, "-->NO TIMING !");
198 }
199 return internal->status;
200 }
201
202 /*
203 * stb0899_search_tmg
204 * perform a fs/2 zig-zag to find timing
205 */
206 static enum stb0899_status stb0899_search_tmg(struct stb0899_state *state)
207 {
208 struct stb0899_internal *internal = &state->internal;
209 struct stb0899_params *params = &state->params;
210
211 short int derot_step, derot_freq = 0, derot_limit, next_loop = 3;
212 int index = 0;
213 u8 cfr[2];
214
215 internal->status = NOTIMING;
216
217 /* timing loop computation & symbol rate optimisation */
218 derot_limit = (internal->sub_range / 2L) / internal->mclk;
219 derot_step = (params->srate / 2L) / internal->mclk;
220
221 while ((stb0899_check_tmg(state) != TIMINGOK) && next_loop) {
222 index++;
223 derot_freq += index * internal->direction * derot_step; /* next derot zig zag position */
224
225 if (abs(derot_freq) > derot_limit)
226 next_loop--;
227
228 if (next_loop) {
229 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq));
230 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq));
231 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
232 }
233 internal->direction = -internal->direction; /* Change zigzag direction */
234 }
235
236 if (internal->status == TIMINGOK) {
237 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
238 internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]);
239 dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK ! Derot Freq = %d", internal->derot_freq);
240 }
241
242 return internal->status;
243 }
244
245 /*
246 * stb0899_check_carrier
247 * Check for carrier found
248 */
249 static enum stb0899_status stb0899_check_carrier(struct stb0899_state *state)
250 {
251 struct stb0899_internal *internal = &state->internal;
252 u8 reg;
253
254 msleep(internal->t_derot); /* wait for derotator ok */
255
256 reg = stb0899_read_reg(state, STB0899_CFD);
257 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
258 stb0899_write_reg(state, STB0899_CFD, reg);
259
260 reg = stb0899_read_reg(state, STB0899_DSTATUS);
261 dprintk(state->verbose, FE_DEBUG, 1, "--------------------> STB0899_DSTATUS=[0x%02x]", reg);
262 if (STB0899_GETFIELD(CARRIER_FOUND, reg)) {
263 internal->status = CARRIEROK;
264 dprintk(state->verbose, FE_DEBUG, 1, "-------------> CARRIEROK !");
265 } else {
266 internal->status = NOCARRIER;
267 dprintk(state->verbose, FE_DEBUG, 1, "-------------> NOCARRIER !");
268 }
269
270 return internal->status;
271 }
272
273 /*
274 * stb0899_search_carrier
275 * Search for a QPSK carrier with the derotator
276 */
277 static enum stb0899_status stb0899_search_carrier(struct stb0899_state *state)
278 {
279 struct stb0899_internal *internal = &state->internal;
280
281 short int derot_freq = 0, last_derot_freq = 0, derot_limit, next_loop = 3;
282 int index = 0;
283 u8 cfr[2];
284 u8 reg;
285
286 internal->status = NOCARRIER;
287 derot_limit = (internal->sub_range / 2L) / internal->mclk;
288 derot_freq = internal->derot_freq;
289
290 reg = stb0899_read_reg(state, STB0899_CFD);
291 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
292 stb0899_write_reg(state, STB0899_CFD, reg);
293
294 do {
295 dprintk(state->verbose, FE_DEBUG, 1, "Derot Freq=%d, mclk=%d", derot_freq, internal->mclk);
296 if (stb0899_check_carrier(state) == NOCARRIER) {
297 index++;
298 last_derot_freq = derot_freq;
299 derot_freq += index * internal->direction * internal->derot_step; /* next zig zag derotator position */
300
301 if(abs(derot_freq) > derot_limit)
302 next_loop--;
303
304 if (next_loop) {
305 reg = stb0899_read_reg(state, STB0899_CFD);
306 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
307 stb0899_write_reg(state, STB0899_CFD, reg);
308
309 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq));
310 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq));
311 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
312 }
313 }
314
315 internal->direction = -internal->direction; /* Change zigzag direction */
316 } while ((internal->status != CARRIEROK) && next_loop);
317
318 if (internal->status == CARRIEROK) {
319 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
320 internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]);
321 dprintk(state->verbose, FE_DEBUG, 1, "----> CARRIER OK !, Derot Freq=%d", internal->derot_freq);
322 } else {
323 internal->derot_freq = last_derot_freq;
324 }
325
326 return internal->status;
327 }
328
329 /*
330 * stb0899_check_data
331 * Check for data found
332 */
333 static enum stb0899_status stb0899_check_data(struct stb0899_state *state)
334 {
335 struct stb0899_internal *internal = &state->internal;
336 struct stb0899_params *params = &state->params;
337
338 int lock = 0, index = 0, dataTime = 500, loop;
339 u8 reg;
340
341 internal->status = NODATA;
342
343 /* RESET FEC */
344 reg = stb0899_read_reg(state, STB0899_TSTRES);
345 STB0899_SETFIELD_VAL(FRESACS, reg, 1);
346 stb0899_write_reg(state, STB0899_TSTRES, reg);
347 msleep(1);
348 reg = stb0899_read_reg(state, STB0899_TSTRES);
349 STB0899_SETFIELD_VAL(FRESACS, reg, 0);
350 stb0899_write_reg(state, STB0899_TSTRES, reg);
351
352 if (params->srate <= 2000000)
353 dataTime = 2000;
354 else if (params->srate <= 5000000)
355 dataTime = 1500;
356 else if (params->srate <= 15000000)
357 dataTime = 1000;
358 else
359 dataTime = 500;
360
361 /* clear previous failed END_LOOPVIT */
362 stb0899_read_reg(state, STB0899_VSTATUS);
363
364 stb0899_write_reg(state, STB0899_DSTATUS2, 0x00); /* force search loop */
365 while (1) {
366 /* WARNING! VIT LOCKED has to be tested before VIT_END_LOOOP */
367 reg = stb0899_read_reg(state, STB0899_VSTATUS);
368 lock = STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg);
369 loop = STB0899_GETFIELD(VSTATUS_END_LOOPVIT, reg);
370
371 if (lock || loop || (index > dataTime))
372 break;
373 index++;
374 }
375
376 if (lock) { /* DATA LOCK indicator */
377 internal->status = DATAOK;
378 dprintk(state->verbose, FE_DEBUG, 1, "-----------------> DATA OK !");
379 }
380
381 return internal->status;
382 }
383
384 /*
385 * stb0899_search_data
386 * Search for a QPSK carrier with the derotator
387 */
388 static enum stb0899_status stb0899_search_data(struct stb0899_state *state)
389 {
390 short int derot_freq, derot_step, derot_limit, next_loop = 3;
391 u8 cfr[2];
392 u8 reg;
393 int index = 1;
394
395 struct stb0899_internal *internal = &state->internal;
396 struct stb0899_params *params = &state->params;
397
398 derot_step = (params->srate / 4L) / internal->mclk;
399 derot_limit = (internal->sub_range / 2L) / internal->mclk;
400 derot_freq = internal->derot_freq;
401
402 do {
403 if ((internal->status != CARRIEROK) || (stb0899_check_data(state) != DATAOK)) {
404
405 derot_freq += index * internal->direction * derot_step; /* next zig zag derotator position */
406 if (abs(derot_freq) > derot_limit)
407 next_loop--;
408
409 if (next_loop) {
410 dprintk(state->verbose, FE_DEBUG, 1, "Derot freq=%d, mclk=%d", derot_freq, internal->mclk);
411 reg = stb0899_read_reg(state, STB0899_CFD);
412 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
413 stb0899_write_reg(state, STB0899_CFD, reg);
414
415 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq));
416 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq));
417 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
418
419 stb0899_check_carrier(state);
420 index++;
421 }
422 }
423 internal->direction = -internal->direction; /* change zig zag direction */
424 } while ((internal->status != DATAOK) && next_loop);
425
426 if (internal->status == DATAOK) {
427 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
428 internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]);
429 dprintk(state->verbose, FE_DEBUG, 1, "------> DATAOK ! Derot Freq=%d", internal->derot_freq);
430 }
431
432 return internal->status;
433 }
434
435 /*
436 * stb0899_check_range
437 * check if the found frequency is in the correct range
438 */
439 static enum stb0899_status stb0899_check_range(struct stb0899_state *state)
440 {
441 struct stb0899_internal *internal = &state->internal;
442 struct stb0899_params *params = &state->params;
443
444 int range_offst, tp_freq;
445
446 range_offst = internal->srch_range / 2000;
447 tp_freq = internal->freq + (internal->derot_freq * internal->mclk) / 1000;
448
449 if ((tp_freq >= params->freq - range_offst) && (tp_freq <= params->freq + range_offst)) {
450 internal->status = RANGEOK;
451 dprintk(state->verbose, FE_DEBUG, 1, "----> RANGEOK !");
452 } else {
453 internal->status = OUTOFRANGE;
454 dprintk(state->verbose, FE_DEBUG, 1, "----> OUT OF RANGE !");
455 }
456
457 return internal->status;
458 }
459
460 /*
461 * NextSubRange
462 * Compute the next subrange of the search
463 */
464 static void next_sub_range(struct stb0899_state *state)
465 {
466 struct stb0899_internal *internal = &state->internal;
467 struct stb0899_params *params = &state->params;
468
469 long old_sub_range;
470
471 if (internal->sub_dir > 0) {
472 old_sub_range = internal->sub_range;
473 internal->sub_range = min((internal->srch_range / 2) -
474 (internal->tuner_offst + internal->sub_range / 2),
475 internal->sub_range);
476
477 if (internal->sub_range < 0)
478 internal->sub_range = 0;
479
480 internal->tuner_offst += (old_sub_range + internal->sub_range) / 2;
481 }
482
483 internal->freq = params->freq + (internal->sub_dir * internal->tuner_offst) / 1000;
484 internal->sub_dir = -internal->sub_dir;
485 }
486
487 /*
488 * stb0899_dvbs_algo
489 * Search for a signal, timing, carrier and data for a
490 * given frequency in a given range
491 */
492 enum stb0899_status stb0899_dvbs_algo(struct stb0899_state *state)
493 {
494 struct stb0899_params *params = &state->params;
495 struct stb0899_internal *internal = &state->internal;
496 struct stb0899_config *config = state->config;
497
498 u8 bclc, reg;
499 u8 cfr[2];
500 u8 eq_const[10];
501 s32 clnI = 3;
502 u32 bandwidth = 0;
503
504 /* BETA values rated @ 99MHz */
505 s32 betaTab[5][4] = {
506 /* 5 10 20 30MBps */
507 { 37, 34, 32, 31 }, /* QPSK 1/2 */
508 { 37, 35, 33, 31 }, /* QPSK 2/3 */
509 { 37, 35, 33, 31 }, /* QPSK 3/4 */
510 { 37, 36, 33, 32 }, /* QPSK 5/6 */
511 { 37, 36, 33, 32 } /* QPSK 7/8 */
512 };
513
514 internal->direction = 1;
515
516 stb0899_set_srate(state, internal->master_clk, params->srate);
517 /* Carrier loop optimization versus symbol rate for acquisition*/
518 if (params->srate <= 5000000) {
519 stb0899_write_reg(state, STB0899_ACLC, 0x89);
520 bclc = stb0899_read_reg(state, STB0899_BCLC);
521 STB0899_SETFIELD_VAL(BETA, bclc, 0x1c);
522 stb0899_write_reg(state, STB0899_BCLC, bclc);
523 clnI = 0;
524 } else if (params->srate <= 15000000) {
525 stb0899_write_reg(state, STB0899_ACLC, 0xc9);
526 bclc = stb0899_read_reg(state, STB0899_BCLC);
527 STB0899_SETFIELD_VAL(BETA, bclc, 0x22);
528 stb0899_write_reg(state, STB0899_BCLC, bclc);
529 clnI = 1;
530 } else if(params->srate <= 25000000) {
531 stb0899_write_reg(state, STB0899_ACLC, 0x89);
532 bclc = stb0899_read_reg(state, STB0899_BCLC);
533 STB0899_SETFIELD_VAL(BETA, bclc, 0x27);
534 stb0899_write_reg(state, STB0899_BCLC, bclc);
535 clnI = 2;
536 } else {
537 stb0899_write_reg(state, STB0899_ACLC, 0xc8);
538 bclc = stb0899_read_reg(state, STB0899_BCLC);
539 STB0899_SETFIELD_VAL(BETA, bclc, 0x29);
540 stb0899_write_reg(state, STB0899_BCLC, bclc);
541 clnI = 3;
542 }
543
544 dprintk(state->verbose, FE_DEBUG, 1, "Set the timing loop to acquisition");
545 /* Set the timing loop to acquisition */
546 stb0899_write_reg(state, STB0899_RTC, 0x46);
547 stb0899_write_reg(state, STB0899_CFD, 0xee);
548
549 /* !! WARNING !!
550 * Do not read any status variables while acquisition,
551 * If any needed, read before the acquisition starts
552 * querying status while acquiring causes the
553 * acquisition to go bad and hence no locks.
554 */
555 dprintk(state->verbose, FE_DEBUG, 1, "Derot Percent=%d Srate=%d mclk=%d",
556 internal->derot_percent, params->srate, internal->mclk);
557
558 /* Initial calculations */
559 internal->derot_step = internal->derot_percent * (params->srate / 1000L) / internal->mclk; /* DerotStep/1000 * Fsymbol */
560 internal->t_derot = stb0899_calc_derot_time(params->srate);
561 internal->t_data = 500;
562
563 dprintk(state->verbose, FE_DEBUG, 1, "RESET stream merger");
564 /* RESET Stream merger */
565 reg = stb0899_read_reg(state, STB0899_TSTRES);
566 STB0899_SETFIELD_VAL(FRESRS, reg, 1);
567 stb0899_write_reg(state, STB0899_TSTRES, reg);
568
569 /*
570 * Set KDIVIDER to an intermediate value between
571 * 1/2 and 7/8 for acquisition
572 */
573 reg = stb0899_read_reg(state, STB0899_DEMAPVIT);
574 STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 60);
575 stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
576
577 stb0899_write_reg(state, STB0899_EQON, 0x01); /* Equalizer OFF while acquiring */
578 stb0899_write_reg(state, STB0899_VITSYNC, 0x19);
579
580 stb0899_first_subrange(state);
581 do {
582 /* Initialisations */
583 cfr[0] = cfr[1] = 0;
584 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* RESET derotator frequency */
585
586 stb0899_write_reg(state, STB0899_RTF, 0);
587 reg = stb0899_read_reg(state, STB0899_CFD);
588 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
589 stb0899_write_reg(state, STB0899_CFD, reg);
590
591 internal->derot_freq = 0;
592 internal->status = NOAGC1;
593
594 /* enable tuner I/O */
595 stb0899_i2c_gate_ctrl(&state->frontend, 1);
596
597 /* Move tuner to frequency */
598 dprintk(state->verbose, FE_DEBUG, 1, "Tuner set frequency");
599 if (state->config->tuner_set_frequency)
600 state->config->tuner_set_frequency(&state->frontend, internal->freq);
601
602 if (state->config->tuner_get_frequency)
603 state->config->tuner_get_frequency(&state->frontend, &internal->freq);
604
605 msleep(internal->t_agc1 + internal->t_agc2 + internal->t_derot); /* AGC1, AGC2 and timing loop */
606 dprintk(state->verbose, FE_DEBUG, 1, "current derot freq=%d", internal->derot_freq);
607 internal->status = AGC1OK;
608
609 /* There is signal in the band */
610 if (config->tuner_get_bandwidth)
611 config->tuner_get_bandwidth(&state->frontend, &bandwidth);
612
613 /* disable tuner I/O */
614 stb0899_i2c_gate_ctrl(&state->frontend, 0);
615
616 if (params->srate <= bandwidth / 2)
617 stb0899_search_tmg(state); /* For low rates (SCPC) */
618 else
619 stb0899_check_tmg(state); /* For high rates (MCPC) */
620
621 if (internal->status == TIMINGOK) {
622 dprintk(state->verbose, FE_DEBUG, 1,
623 "TIMING OK ! Derot freq=%d, mclk=%d",
624 internal->derot_freq, internal->mclk);
625
626 if (stb0899_search_carrier(state) == CARRIEROK) { /* Search for carrier */
627 dprintk(state->verbose, FE_DEBUG, 1,
628 "CARRIER OK ! Derot freq=%d, mclk=%d",
629 internal->derot_freq, internal->mclk);
630
631 if (stb0899_search_data(state) == DATAOK) { /* Check for data */
632 dprintk(state->verbose, FE_DEBUG, 1,
633 "DATA OK ! Derot freq=%d, mclk=%d",
634 internal->derot_freq, internal->mclk);
635
636 if (stb0899_check_range(state) == RANGEOK) {
637 dprintk(state->verbose, FE_DEBUG, 1,
638 "RANGE OK ! derot freq=%d, mclk=%d",
639 internal->derot_freq, internal->mclk);
640
641 internal->freq = params->freq + ((internal->derot_freq * internal->mclk) / 1000);
642 reg = stb0899_read_reg(state, STB0899_PLPARM);
643 internal->fecrate = STB0899_GETFIELD(VITCURPUN, reg);
644 dprintk(state->verbose, FE_DEBUG, 1,
645 "freq=%d, internal resultant freq=%d",
646 params->freq, internal->freq);
647
648 dprintk(state->verbose, FE_DEBUG, 1,
649 "internal puncture rate=%d",
650 internal->fecrate);
651 }
652 }
653 }
654 }
655 if (internal->status != RANGEOK)
656 next_sub_range(state);
657
658 } while (internal->sub_range && internal->status != RANGEOK);
659
660 /* Set the timing loop to tracking */
661 stb0899_write_reg(state, STB0899_RTC, 0x33);
662 stb0899_write_reg(state, STB0899_CFD, 0xf7);
663 /* if locked and range ok, set Kdiv */
664 if (internal->status == RANGEOK) {
665 dprintk(state->verbose, FE_DEBUG, 1, "Locked & Range OK !");
666 stb0899_write_reg(state, STB0899_EQON, 0x41); /* Equalizer OFF while acquiring */
667 stb0899_write_reg(state, STB0899_VITSYNC, 0x39); /* SN to b'11 for acquisition */
668
669 /*
670 * Carrier loop optimization versus
671 * symbol Rate/Puncture Rate for Tracking
672 */
673 reg = stb0899_read_reg(state, STB0899_BCLC);
674 switch (internal->fecrate) {
675 case STB0899_FEC_1_2: /* 13 */
676 stb0899_write_reg(state, STB0899_DEMAPVIT, 0x1a);
677 STB0899_SETFIELD_VAL(BETA, reg, betaTab[0][clnI]);
678 stb0899_write_reg(state, STB0899_BCLC, reg);
679 break;
680 case STB0899_FEC_2_3: /* 18 */
681 stb0899_write_reg(state, STB0899_DEMAPVIT, 44);
682 STB0899_SETFIELD_VAL(BETA, reg, betaTab[1][clnI]);
683 stb0899_write_reg(state, STB0899_BCLC, reg);
684 break;
685 case STB0899_FEC_3_4: /* 21 */
686 stb0899_write_reg(state, STB0899_DEMAPVIT, 60);
687 STB0899_SETFIELD_VAL(BETA, reg, betaTab[2][clnI]);
688 stb0899_write_reg(state, STB0899_BCLC, reg);
689 break;
690 case STB0899_FEC_5_6: /* 24 */
691 stb0899_write_reg(state, STB0899_DEMAPVIT, 75);
692 STB0899_SETFIELD_VAL(BETA, reg, betaTab[3][clnI]);
693 stb0899_write_reg(state, STB0899_BCLC, reg);
694 break;
695 case STB0899_FEC_6_7: /* 25 */
696 stb0899_write_reg(state, STB0899_DEMAPVIT, 88);
697 stb0899_write_reg(state, STB0899_ACLC, 0x88);
698 stb0899_write_reg(state, STB0899_BCLC, 0x9a);
699 break;
700 case STB0899_FEC_7_8: /* 26 */
701 stb0899_write_reg(state, STB0899_DEMAPVIT, 94);
702 STB0899_SETFIELD_VAL(BETA, reg, betaTab[4][clnI]);
703 stb0899_write_reg(state, STB0899_BCLC, reg);
704 break;
705 default:
706 dprintk(state->verbose, FE_DEBUG, 1, "Unsupported Puncture Rate");
707 break;
708 }
709 /* release stream merger RESET */
710 reg = stb0899_read_reg(state, STB0899_TSTRES);
711 STB0899_SETFIELD_VAL(FRESRS, reg, 0);
712 stb0899_write_reg(state, STB0899_TSTRES, reg);
713
714 /* disable carrier detector */
715 reg = stb0899_read_reg(state, STB0899_CFD);
716 STB0899_SETFIELD_VAL(CFD_ON, reg, 0);
717 stb0899_write_reg(state, STB0899_CFD, reg);
718
719 stb0899_read_regs(state, STB0899_EQUAI1, eq_const, 10);
720 }
721
722 return internal->status;
723 }
724
725 /*
726 * stb0899_dvbs2_config_uwp
727 * Configure UWP state machine
728 */
729 static void stb0899_dvbs2_config_uwp(struct stb0899_state *state)
730 {
731 struct stb0899_internal *internal = &state->internal;
732 struct stb0899_config *config = state->config;
733 u32 uwp1, uwp2, uwp3, reg;
734
735 uwp1 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL1);
736 uwp2 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL2);
737 uwp3 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL3);
738
739 STB0899_SETFIELD_VAL(UWP_ESN0_AVE, uwp1, config->esno_ave);
740 STB0899_SETFIELD_VAL(UWP_ESN0_QUANT, uwp1, config->esno_quant);
741 STB0899_SETFIELD_VAL(UWP_TH_SOF, uwp1, config->uwp_threshold_sof);
742
743 STB0899_SETFIELD_VAL(FE_COARSE_TRK, uwp2, internal->av_frame_coarse);
744 STB0899_SETFIELD_VAL(FE_FINE_TRK, uwp2, internal->av_frame_fine);
745 STB0899_SETFIELD_VAL(UWP_MISS_TH, uwp2, config->miss_threshold);
746
747 STB0899_SETFIELD_VAL(UWP_TH_ACQ, uwp3, config->uwp_threshold_acq);
748 STB0899_SETFIELD_VAL(UWP_TH_TRACK, uwp3, config->uwp_threshold_track);
749
750 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL1, STB0899_OFF0_UWP_CNTRL1, uwp1);
751 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL2, STB0899_OFF0_UWP_CNTRL2, uwp2);
752 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL3, STB0899_OFF0_UWP_CNTRL3, uwp3);
753
754 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, SOF_SRCH_TO);
755 STB0899_SETFIELD_VAL(SOF_SEARCH_TIMEOUT, reg, config->sof_search_timeout);
756 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_SOF_SRCH_TO, STB0899_OFF0_SOF_SRCH_TO, reg);
757 }
758
759 /*
760 * stb0899_dvbs2_config_csm_auto
761 * Set CSM to AUTO mode
762 */
763 static void stb0899_dvbs2_config_csm_auto(struct stb0899_state *state)
764 {
765 u32 reg;
766
767 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
768 STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, reg, 1);
769 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, reg);
770 }
771
772 static long Log2Int(int number)
773 {
774 int i;
775
776 i = 0;
777 while ((1 << i) <= abs(number))
778 i++;
779
780 if (number == 0)
781 i = 1;
782
783 return i - 1;
784 }
785
786 /*
787 * stb0899_dvbs2_calc_srate
788 * compute BTR_NOM_FREQ for the symbol rate
789 */
790 static u32 stb0899_dvbs2_calc_srate(struct stb0899_state *state)
791 {
792 struct stb0899_internal *internal = &state->internal;
793 struct stb0899_config *config = state->config;
794
795 u32 dec_ratio, dec_rate, decim, remain, intval, btr_nom_freq;
796 u32 master_clk, srate;
797
798 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
799 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
800 dec_rate = Log2Int(dec_ratio);
801 decim = 1 << dec_rate;
802 master_clk = internal->master_clk / 1000;
803 srate = internal->srate / 1000;
804
805 if (decim <= 4) {
806 intval = (decim * (1 << (config->btr_nco_bits - 1))) / master_clk;
807 remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk;
808 } else {
809 intval = (1 << (config->btr_nco_bits - 1)) / (master_clk / 100) * decim / 100;
810 remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk;
811 }
812 btr_nom_freq = (intval * srate) + ((remain * srate) / master_clk);
813
814 return btr_nom_freq;
815 }
816
817 /*
818 * stb0899_dvbs2_calc_dev
819 * compute the correction to be applied to symbol rate
820 */
821 static u32 stb0899_dvbs2_calc_dev(struct stb0899_state *state)
822 {
823 struct stb0899_internal *internal = &state->internal;
824 u32 dec_ratio, correction, master_clk, srate;
825
826 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
827 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
828
829 master_clk = internal->master_clk / 1000; /* for integer Caculation*/
830 srate = internal->srate / 1000; /* for integer Caculation*/
831 correction = (512 * master_clk) / (2 * dec_ratio * srate);
832
833 return correction;
834 }
835
836 /*
837 * stb0899_dvbs2_set_srate
838 * Set DVBS2 symbol rate
839 */
840 static void stb0899_dvbs2_set_srate(struct stb0899_state *state)
841 {
842 struct stb0899_internal *internal = &state->internal;
843
844 u32 dec_ratio, dec_rate, win_sel, decim, f_sym, btr_nom_freq;
845 u32 correction, freq_adj, band_lim, decim_cntrl, reg;
846 u8 anti_alias;
847
848 /*set decimation to 1*/
849 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
850 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
851 dec_rate = Log2Int(dec_ratio);
852
853 win_sel = 0;
854 if (dec_rate >= 5)
855 win_sel = dec_rate - 4;
856
857 decim = (1 << dec_rate);
858 /* (FSamp/Fsymbol *100) for integer Caculation */
859 f_sym = internal->master_clk / ((decim * internal->srate) / 1000);
860
861 if (f_sym <= 2250) /* don't band limit signal going into btr block*/
862 band_lim = 1;
863 else
864 band_lim = 0; /* band limit signal going into btr block*/
865
866 decim_cntrl = ((win_sel << 3) & 0x18) + ((band_lim << 5) & 0x20) + (dec_rate & 0x7);
867 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DECIM_CNTRL, STB0899_OFF0_DECIM_CNTRL, decim_cntrl);
868
869 if (f_sym <= 3450)
870 anti_alias = 0;
871 else if (f_sym <= 4250)
872 anti_alias = 1;
873 else
874 anti_alias = 2;
875
876 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ANTI_ALIAS_SEL, STB0899_OFF0_ANTI_ALIAS_SEL, anti_alias);
877 btr_nom_freq = stb0899_dvbs2_calc_srate(state);
878 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_NOM_FREQ, STB0899_OFF0_BTR_NOM_FREQ, btr_nom_freq);
879
880 correction = stb0899_dvbs2_calc_dev(state);
881 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
882 STB0899_SETFIELD_VAL(BTR_FREQ_CORR, reg, correction);
883 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
884
885 /* scale UWP+CSM frequency to sample rate*/
886 freq_adj = internal->srate / (internal->master_clk / 4096);
887 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_FREQ_ADJ_SCALE, STB0899_OFF0_FREQ_ADJ_SCALE, freq_adj);
888 }
889
890 /*
891 * stb0899_dvbs2_set_btr_loopbw
892 * set bit timing loop bandwidth as a percentage of the symbol rate
893 */
894 static void stb0899_dvbs2_set_btr_loopbw(struct stb0899_state *state)
895 {
896 struct stb0899_internal *internal = &state->internal;
897 struct stb0899_config *config = state->config;
898
899 u32 sym_peak = 23, zeta = 707, loopbw_percent = 60;
900 s32 dec_ratio, dec_rate, k_btr1_rshft, k_btr1, k_btr0_rshft;
901 s32 k_btr0, k_btr2_rshft, k_direct_shift, k_indirect_shift;
902 u32 decim, K, wn, k_direct, k_indirect;
903 u32 reg;
904
905 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
906 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
907 dec_rate = Log2Int(dec_ratio);
908 decim = (1 << dec_rate);
909
910 sym_peak *= 576000;
911 K = (1 << config->btr_nco_bits) / (internal->master_clk / 1000);
912 K *= (internal->srate / 1000000) * decim; /*k=k 10^-8*/
913
914 if (K != 0) {
915 K = sym_peak / K;
916 wn = (4 * zeta * zeta) + 1000000;
917 wn = (2 * (loopbw_percent * 1000) * 40 * zeta) /wn; /*wn =wn 10^-8*/
918
919 k_indirect = (wn * wn) / K;
920 k_indirect = k_indirect; /*kindirect = kindirect 10^-6*/
921 k_direct = (2 * wn * zeta) / K; /*kDirect = kDirect 10^-2*/
922 k_direct *= 100;
923
924 k_direct_shift = Log2Int(k_direct) - Log2Int(10000) - 2;
925 k_btr1_rshft = (-1 * k_direct_shift) + config->btr_gain_shift_offset;
926 k_btr1 = k_direct / (1 << k_direct_shift);
927 k_btr1 /= 10000;
928
929 k_indirect_shift = Log2Int(k_indirect + 15) - 20 /*- 2*/;
930 k_btr0_rshft = (-1 * k_indirect_shift) + config->btr_gain_shift_offset;
931 k_btr0 = k_indirect * (1 << (-k_indirect_shift));
932 k_btr0 /= 1000000;
933
934 k_btr2_rshft = 0;
935 if (k_btr0_rshft > 15) {
936 k_btr2_rshft = k_btr0_rshft - 15;
937 k_btr0_rshft = 15;
938 }
939 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_LOOP_GAIN);
940 STB0899_SETFIELD_VAL(KBTR0_RSHFT, reg, k_btr0_rshft);
941 STB0899_SETFIELD_VAL(KBTR0, reg, k_btr0);
942 STB0899_SETFIELD_VAL(KBTR1_RSHFT, reg, k_btr1_rshft);
943 STB0899_SETFIELD_VAL(KBTR1, reg, k_btr1);
944 STB0899_SETFIELD_VAL(KBTR2_RSHFT, reg, k_btr2_rshft);
945 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, reg);
946 } else
947 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, 0xc4c4f);
948 }
949
950 /*
951 * stb0899_dvbs2_set_carr_freq
952 * set nominal frequency for carrier search
953 */
954 static void stb0899_dvbs2_set_carr_freq(struct stb0899_state *state, s32 carr_freq, u32 master_clk)
955 {
956 struct stb0899_config *config = state->config;
957 s32 crl_nom_freq;
958 u32 reg;
959
960 crl_nom_freq = (1 << config->crl_nco_bits) / master_clk;
961 crl_nom_freq *= carr_freq;
962 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
963 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, crl_nom_freq);
964 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
965 }
966
967 /*
968 * stb0899_dvbs2_init_calc
969 * Initialize DVBS2 UWP, CSM, carrier and timing loops
970 */
971 static void stb0899_dvbs2_init_calc(struct stb0899_state *state)
972 {
973 struct stb0899_internal *internal = &state->internal;
974 s32 steps, step_size;
975 u32 range, reg;
976
977 /* config uwp and csm */
978 stb0899_dvbs2_config_uwp(state);
979 stb0899_dvbs2_config_csm_auto(state);
980
981 /* initialize BTR */
982 stb0899_dvbs2_set_srate(state);
983 stb0899_dvbs2_set_btr_loopbw(state);
984
985 if (internal->srate / 1000000 >= 15)
986 step_size = (1 << 17) / 5;
987 else if (internal->srate / 1000000 >= 10)
988 step_size = (1 << 17) / 7;
989 else if (internal->srate / 1000000 >= 5)
990 step_size = (1 << 17) / 10;
991 else
992 step_size = (1 << 17) / 4;
993
994 range = internal->srch_range / 1000000;
995 steps = (10 * range * (1 << 17)) / (step_size * (internal->srate / 1000000));
996 steps = (steps + 6) / 10;
997 steps = (steps == 0) ? 1 : steps;
998 if (steps % 2 == 0)
999 stb0899_dvbs2_set_carr_freq(state, internal->center_freq -
1000 (internal->step_size * (internal->srate / 20000000)),
1001 (internal->master_clk) / 1000000);
1002 else
1003 stb0899_dvbs2_set_carr_freq(state, internal->center_freq, (internal->master_clk) / 1000000);
1004
1005 /*Set Carrier Search params (zigzag, num steps and freq step size*/
1006 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, ACQ_CNTRL2);
1007 STB0899_SETFIELD_VAL(ZIGZAG, reg, 1);
1008 STB0899_SETFIELD_VAL(NUM_STEPS, reg, steps);
1009 STB0899_SETFIELD_VAL(FREQ_STEPSIZE, reg, step_size);
1010 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQ_CNTRL2, STB0899_OFF0_ACQ_CNTRL2, reg);
1011 }
1012
1013 /*
1014 * stb0899_dvbs2_btr_init
1015 * initialize the timing loop
1016 */
1017 static void stb0899_dvbs2_btr_init(struct stb0899_state *state)
1018 {
1019 u32 reg;
1020
1021 /* set enable BTR loopback */
1022 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
1023 STB0899_SETFIELD_VAL(INTRP_PHS_SENSE, reg, 1);
1024 STB0899_SETFIELD_VAL(BTR_ERR_ENA, reg, 1);
1025 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
1026
1027 /* fix btr freq accum at 0 */
1028 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x10000000);
1029 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x00000000);
1030
1031 /* fix btr freq accum at 0 */
1032 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x10000000);
1033 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x00000000);
1034 }
1035
1036 /*
1037 * stb0899_dvbs2_reacquire
1038 * trigger a DVB-S2 acquisition
1039 */
1040 static void stb0899_dvbs2_reacquire(struct stb0899_state *state)
1041 {
1042 u32 reg = 0;
1043
1044 /* demod soft reset */
1045 STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 1);
1046 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
1047
1048 /*Reset Timing Loop */
1049 stb0899_dvbs2_btr_init(state);
1050
1051 /* reset Carrier loop */
1052 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, (1 << 30));
1053 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, 0);
1054 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_LOOP_GAIN, STB0899_OFF0_CRL_LOOP_GAIN, 0);
1055 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, (1 << 30));
1056 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, 0);
1057
1058 /*release demod soft reset */
1059 reg = 0;
1060 STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 0);
1061 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
1062
1063 /* start acquisition process */
1064 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQUIRE_TRIG, STB0899_OFF0_ACQUIRE_TRIG, 1);
1065 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_LOCK_LOST, STB0899_OFF0_LOCK_LOST, 0);
1066
1067 /* equalizer Init */
1068 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 1);
1069
1070 /*Start equilizer */
1071 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 0);
1072
1073 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1074 STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0);
1075 STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 0);
1076 STB0899_SETFIELD_VAL(EQ_DELAY, reg, 0x05);
1077 STB0899_SETFIELD_VAL(EQ_ADAPT_MODE, reg, 0x01);
1078 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1079
1080 /* RESET Packet delineator */
1081 stb0899_write_reg(state, STB0899_PDELCTRL, 0x4a);
1082 }
1083
1084 /*
1085 * stb0899_dvbs2_get_dmd_status
1086 * get DVB-S2 Demod LOCK status
1087 */
1088 static enum stb0899_status stb0899_dvbs2_get_dmd_status(struct stb0899_state *state, int timeout)
1089 {
1090 int time = -10, lock = 0, uwp, csm;
1091 u32 reg;
1092
1093 do {
1094 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STATUS);
1095 dprintk(state->verbose, FE_DEBUG, 1, "DMD_STATUS=[0x%02x]", reg);
1096 if (STB0899_GETFIELD(IF_AGC_LOCK, reg))
1097 dprintk(state->verbose, FE_DEBUG, 1, "------------->IF AGC LOCKED !");
1098 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STAT2);
1099 dprintk(state->verbose, FE_DEBUG, 1, "----------->DMD STAT2=[0x%02x]", reg);
1100 uwp = STB0899_GETFIELD(UWP_LOCK, reg);
1101 csm = STB0899_GETFIELD(CSM_LOCK, reg);
1102 if (uwp && csm)
1103 lock = 1;
1104
1105 time += 10;
1106 msleep(10);
1107
1108 } while ((!lock) && (time <= timeout));
1109
1110 if (lock) {
1111 dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 LOCK !");
1112 return DVBS2_DEMOD_LOCK;
1113 } else {
1114 return DVBS2_DEMOD_NOLOCK;
1115 }
1116 }
1117
1118 /*
1119 * stb0899_dvbs2_get_data_lock
1120 * get FEC status
1121 */
1122 static int stb0899_dvbs2_get_data_lock(struct stb0899_state *state, int timeout)
1123 {
1124 int time = 0, lock = 0;
1125 u8 reg;
1126
1127 while ((!lock) && (time < timeout)) {
1128 reg = stb0899_read_reg(state, STB0899_CFGPDELSTATUS1);
1129 dprintk(state->verbose, FE_DEBUG, 1, "---------> CFGPDELSTATUS=[0x%02x]", reg);
1130 lock = STB0899_GETFIELD(CFGPDELSTATUS_LOCK, reg);
1131 time++;
1132 }
1133
1134 return lock;
1135 }
1136
1137 /*
1138 * stb0899_dvbs2_get_fec_status
1139 * get DVB-S2 FEC LOCK status
1140 */
1141 static enum stb0899_status stb0899_dvbs2_get_fec_status(struct stb0899_state *state, int timeout)
1142 {
1143 int time = 0, Locked;
1144
1145 do {
1146 Locked = stb0899_dvbs2_get_data_lock(state, 1);
1147 time++;
1148 msleep(1);
1149
1150 } while ((!Locked) && (time < timeout));
1151
1152 if (Locked) {
1153 dprintk(state->verbose, FE_DEBUG, 1, "---------->DVB-S2 FEC LOCK !");
1154 return DVBS2_FEC_LOCK;
1155 } else {
1156 return DVBS2_FEC_NOLOCK;
1157 }
1158 }
1159
1160
1161 /*
1162 * stb0899_dvbs2_init_csm
1163 * set parameters for manual mode
1164 */
1165 static void stb0899_dvbs2_init_csm(struct stb0899_state *state, int pilots, enum stb0899_modcod modcod)
1166 {
1167 struct stb0899_internal *internal = &state->internal;
1168
1169 s32 dvt_tbl = 1, two_pass = 0, agc_gain = 6, agc_shift = 0, loop_shift = 0, phs_diff_thr = 0x80;
1170 s32 gamma_acq, gamma_rho_acq, gamma_trk, gamma_rho_trk, lock_count_thr;
1171 u32 csm1, csm2, csm3, csm4;
1172
1173 if (((internal->master_clk / internal->srate) <= 4) && (modcod <= 11) && (pilots == 1)) {
1174 switch (modcod) {
1175 case STB0899_QPSK_12:
1176 gamma_acq = 25;
1177 gamma_rho_acq = 2700;
1178 gamma_trk = 12;
1179 gamma_rho_trk = 180;
1180 lock_count_thr = 8;
1181 break;
1182 case STB0899_QPSK_35:
1183 gamma_acq = 38;
1184 gamma_rho_acq = 7182;
1185 gamma_trk = 14;
1186 gamma_rho_trk = 308;
1187 lock_count_thr = 8;
1188 break;
1189 case STB0899_QPSK_23:
1190 gamma_acq = 42;
1191 gamma_rho_acq = 9408;
1192 gamma_trk = 17;
1193 gamma_rho_trk = 476;
1194 lock_count_thr = 8;
1195 break;
1196 case STB0899_QPSK_34:
1197 gamma_acq = 53;
1198 gamma_rho_acq = 16642;
1199 gamma_trk = 19;
1200 gamma_rho_trk = 646;
1201 lock_count_thr = 8;
1202 break;
1203 case STB0899_QPSK_45:
1204 gamma_acq = 53;
1205 gamma_rho_acq = 17119;
1206 gamma_trk = 22;
1207 gamma_rho_trk = 880;
1208 lock_count_thr = 8;
1209 break;
1210 case STB0899_QPSK_56:
1211 gamma_acq = 55;
1212 gamma_rho_acq = 19250;
1213 gamma_trk = 23;
1214 gamma_rho_trk = 989;
1215 lock_count_thr = 8;
1216 break;
1217 case STB0899_QPSK_89:
1218 gamma_acq = 60;
1219 gamma_rho_acq = 24240;
1220 gamma_trk = 24;
1221 gamma_rho_trk = 1176;
1222 lock_count_thr = 8;
1223 break;
1224 case STB0899_QPSK_910:
1225 gamma_acq = 66;
1226 gamma_rho_acq = 29634;
1227 gamma_trk = 24;
1228 gamma_rho_trk = 1176;
1229 lock_count_thr = 8;
1230 break;
1231 default:
1232 gamma_acq = 66;
1233 gamma_rho_acq = 29634;
1234 gamma_trk = 24;
1235 gamma_rho_trk = 1176;
1236 lock_count_thr = 8;
1237 break;
1238 }
1239
1240 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1241 STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, csm1, 0);
1242 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1243
1244 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1245 csm2 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL2);
1246 csm3 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL3);
1247 csm4 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL4);
1248
1249 STB0899_SETFIELD_VAL(CSM_DVT_TABLE, csm1, dvt_tbl);
1250 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, two_pass);
1251 STB0899_SETFIELD_VAL(CSM_AGC_GAIN, csm1, agc_gain);
1252 STB0899_SETFIELD_VAL(CSM_AGC_SHIFT, csm1, agc_shift);
1253 STB0899_SETFIELD_VAL(FE_LOOP_SHIFT, csm1, loop_shift);
1254 STB0899_SETFIELD_VAL(CSM_GAMMA_ACQ, csm2, gamma_acq);
1255 STB0899_SETFIELD_VAL(CSM_GAMMA_RHOACQ, csm2, gamma_rho_acq);
1256 STB0899_SETFIELD_VAL(CSM_GAMMA_TRACK, csm3, gamma_trk);
1257 STB0899_SETFIELD_VAL(CSM_GAMMA_RHOTRACK, csm3, gamma_rho_trk);
1258 STB0899_SETFIELD_VAL(CSM_LOCKCOUNT_THRESH, csm4, lock_count_thr);
1259 STB0899_SETFIELD_VAL(CSM_PHASEDIFF_THRESH, csm4, phs_diff_thr);
1260
1261 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1262 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL2, STB0899_OFF0_CSM_CNTRL2, csm2);
1263 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL3, STB0899_OFF0_CSM_CNTRL3, csm3);
1264 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL4, STB0899_OFF0_CSM_CNTRL4, csm4);
1265 }
1266 }
1267
1268 /*
1269 * stb0899_dvbs2_get_srate
1270 * get DVB-S2 Symbol Rate
1271 */
1272 static u32 stb0899_dvbs2_get_srate(struct stb0899_state *state)
1273 {
1274 struct stb0899_internal *internal = &state->internal;
1275 struct stb0899_config *config = state->config;
1276
1277 u32 bTrNomFreq, srate, decimRate, intval1, intval2, reg;
1278 int div1, div2, rem1, rem2;
1279
1280 div1 = config->btr_nco_bits / 2;
1281 div2 = config->btr_nco_bits - div1 - 1;
1282
1283 bTrNomFreq = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_NOM_FREQ);
1284
1285 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DECIM_CNTRL);
1286 decimRate = STB0899_GETFIELD(DECIM_RATE, reg);
1287 decimRate = (1 << decimRate);
1288
1289 intval1 = internal->master_clk / (1 << div1);
1290 intval2 = bTrNomFreq / (1 << div2);
1291
1292 rem1 = internal->master_clk % (1 << div1);
1293 rem2 = bTrNomFreq % (1 << div2);
1294 /* only for integer calculation */
1295 srate = (intval1 * intval2) + ((intval1 * rem2) / (1 << div2)) + ((intval2 * rem1) / (1 << div1));
1296 srate /= decimRate; /*symbrate = (btrnomfreq_register_val*MasterClock)/2^(27+decim_rate_field) */
1297
1298 return srate;
1299 }
1300
1301 /*
1302 * stb0899_dvbs2_algo
1303 * Search for signal, timing, carrier and data for a given
1304 * frequency in a given range
1305 */
1306 enum stb0899_status stb0899_dvbs2_algo(struct stb0899_state *state)
1307 {
1308 struct stb0899_internal *internal = &state->internal;
1309 enum stb0899_modcod modcod;
1310
1311 s32 offsetfreq, searchTime, FecLockTime, pilots, iqSpectrum;
1312 int i = 0;
1313 u32 reg, csm1;
1314
1315 if (internal->srate <= 2000000) {
1316 searchTime = 5000; /* 5000 ms max time to lock UWP and CSM, SYMB <= 2Mbs */
1317 FecLockTime = 350; /* 350 ms max time to lock FEC, SYMB <= 2Mbs */
1318 } else if (internal->srate <= 5000000) {
1319 searchTime = 2500; /* 2500 ms max time to lock UWP and CSM, 2Mbs < SYMB <= 5Mbs */
1320 FecLockTime = 170; /* 170 ms max time to lock FEC, 2Mbs< SYMB <= 5Mbs */
1321 } else if (internal->srate <= 10000000) {
1322 searchTime = 1500; /* 1500 ms max time to lock UWP and CSM, 5Mbs <SYMB <= 10Mbs */
1323 FecLockTime = 80; /* 80 ms max time to lock FEC, 5Mbs< SYMB <= 10Mbs */
1324 } else if (internal->srate <= 15000000) {
1325 searchTime = 500; /* 500 ms max time to lock UWP and CSM, 10Mbs <SYMB <= 15Mbs */
1326 FecLockTime = 50; /* 50 ms max time to lock FEC, 10Mbs< SYMB <= 15Mbs */
1327 } else if (internal->srate <= 20000000) {
1328 searchTime = 300; /* 300 ms max time to lock UWP and CSM, 15Mbs < SYMB <= 20Mbs */
1329 FecLockTime = 30; /* 50 ms max time to lock FEC, 15Mbs< SYMB <= 20Mbs */
1330 } else if (internal->srate <= 25000000) {
1331 searchTime = 250; /* 250 ms max time to lock UWP and CSM, 20 Mbs < SYMB <= 25Mbs */
1332 FecLockTime = 25; /* 25 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs */
1333 } else {
1334 searchTime = 150; /* 150 ms max time to lock UWP and CSM, SYMB > 25Mbs */
1335 FecLockTime = 20; /* 20 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs */
1336 }
1337
1338 /* Maintain Stream Merger in reset during acquisition */
1339 reg = stb0899_read_reg(state, STB0899_TSTRES);
1340 STB0899_SETFIELD_VAL(FRESRS, reg, 1);
1341 stb0899_write_reg(state, STB0899_TSTRES, reg);
1342
1343 /* enable tuner I/O */
1344 stb0899_i2c_gate_ctrl(&state->frontend, 1);
1345
1346 /* Move tuner to frequency */
1347 if (state->config->tuner_set_frequency)
1348 state->config->tuner_set_frequency(&state->frontend, internal->freq);
1349 if (state->config->tuner_get_frequency)
1350 state->config->tuner_get_frequency(&state->frontend, &internal->freq);
1351
1352 /* disable tuner I/O */
1353 stb0899_i2c_gate_ctrl(&state->frontend, 0);
1354
1355 /* Set IF AGC to acquisition */
1356 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
1357 STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg, 4);
1358 STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 32);
1359 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
1360
1361 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
1362 STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 0);
1363 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
1364
1365 /* Initialisation */
1366 stb0899_dvbs2_init_calc(state);
1367
1368 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1369 switch (internal->inversion) {
1370 case IQ_SWAP_OFF:
1371 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 0);
1372 break;
1373 case IQ_SWAP_ON:
1374 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1);
1375 break;
1376 case IQ_SWAP_AUTO: /* use last successful search first */
1377 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1);
1378 break;
1379 }
1380 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
1381 stb0899_dvbs2_reacquire(state);
1382
1383 /* Wait for demod lock (UWP and CSM) */
1384 internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime);
1385
1386 if (internal->status == DVBS2_DEMOD_LOCK) {
1387 dprintk(state->verbose, FE_DEBUG, 1, "------------> DVB-S2 DEMOD LOCK !");
1388 i = 0;
1389 /* Demod Locked, check FEC status */
1390 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1391
1392 /*If false lock (UWP and CSM Locked but no FEC) try 3 time max*/
1393 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1394 /* Read the frequency offset*/
1395 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1396
1397 /* Set the Nominal frequency to the found frequency offset for the next reacquire*/
1398 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
1399 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
1400 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
1401 stb0899_dvbs2_reacquire(state);
1402 internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
1403 i++;
1404 }
1405 }
1406
1407 if (internal->status != DVBS2_FEC_LOCK) {
1408 if (internal->inversion == IQ_SWAP_AUTO) {
1409 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1410 iqSpectrum = STB0899_GETFIELD(SPECTRUM_INVERT, reg);
1411 /* IQ Spectrum Inversion */
1412 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, !iqSpectrum);
1413 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
1414 /* start acquistion process */
1415 stb0899_dvbs2_reacquire(state);
1416
1417 /* Wait for demod lock (UWP and CSM) */
1418 internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime);
1419 if (internal->status == DVBS2_DEMOD_LOCK) {
1420 i = 0;
1421 /* Demod Locked, check FEC */
1422 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1423 /*try thrice for false locks, (UWP and CSM Locked but no FEC) */
1424 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1425 /* Read the frequency offset*/
1426 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1427
1428 /* Set the Nominal frequency to the found frequency offset for the next reacquire*/
1429 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
1430 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
1431 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
1432
1433 stb0899_dvbs2_reacquire(state);
1434 internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
1435 i++;
1436 }
1437 }
1438 /*
1439 if (pParams->DVBS2State == FE_DVBS2_FEC_LOCKED)
1440 pParams->IQLocked = !iqSpectrum;
1441 */
1442 }
1443 }
1444 if (internal->status == DVBS2_FEC_LOCK) {
1445 dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 FEC Lock !");
1446 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
1447 modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
1448 pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
1449
1450 if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) &&
1451 (INRANGE(STB0899_QPSK_23, modcod, STB0899_QPSK_910)) &&
1452 (pilots == 1)) {
1453
1454 stb0899_dvbs2_init_csm(state, pilots, modcod);
1455 /* Wait for UWP,CSM and data LOCK 20ms max */
1456 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1457
1458 i = 0;
1459 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1460 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1461 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 1);
1462 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1463 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1464 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 0);
1465 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1466
1467 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1468 i++;
1469 }
1470 }
1471
1472 if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) &&
1473 (INRANGE(STB0899_QPSK_12, modcod, STB0899_QPSK_35)) &&
1474 (pilots == 1)) {
1475
1476 /* Equalizer Disable update */
1477 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1478 STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 1);
1479 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1480 }
1481
1482 /* slow down the Equalizer once locked */
1483 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1484 STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0x02);
1485 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1486
1487 /* Store signal parameters */
1488 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1489
1490 offsetfreq = offsetfreq / ((1 << 30) / 1000);
1491 offsetfreq *= (internal->master_clk / 1000000);
1492 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1493 if (STB0899_GETFIELD(SPECTRUM_INVERT, reg))
1494 offsetfreq *= -1;
1495
1496 internal->freq = internal->freq - offsetfreq;
1497 internal->srate = stb0899_dvbs2_get_srate(state);
1498
1499 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
1500 internal->modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
1501 internal->pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
1502 internal->frame_length = (STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 1) & 0x01;
1503
1504 /* Set IF AGC to tracking */
1505 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
1506 STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg, 3);
1507
1508 /* if QPSK 1/2,QPSK 3/5 or QPSK 2/3 set IF AGC reference to 16 otherwise 32*/
1509 if (INRANGE(STB0899_QPSK_12, internal->modcod, STB0899_QPSK_23))
1510 STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 16);
1511
1512 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
1513
1514 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
1515 STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 7);
1516 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
1517 }
1518
1519 /* Release Stream Merger Reset */
1520 reg = stb0899_read_reg(state, STB0899_TSTRES);
1521 STB0899_SETFIELD_VAL(FRESRS, reg, 0);
1522 stb0899_write_reg(state, STB0899_TSTRES, reg);
1523
1524 return internal->status;
1525 }