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Merge tag 'v3.3.7' into 3.3/master
[zen-stable.git] / drivers / media / video / omap3isp / ispccp2.c
blob70ddbf35b223bc7f070d6572d0c1e60cbc15b74c
1 /*
2 * ispccp2.c
3 *
4 * TI OMAP3 ISP - CCP2 module
5 *
6 * Copyright (C) 2010 Nokia Corporation
7 * Copyright (C) 2010 Texas Instruments, Inc.
8 *
9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 * Sakari Ailus <sakari.ailus@iki.fi>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 * 02110-1301 USA
25 */
26
27 #include <linux/delay.h>
28 #include <linux/device.h>
29 #include <linux/mm.h>
30 #include <linux/module.h>
31 #include <linux/mutex.h>
32 #include <linux/uaccess.h>
33 #include <linux/regulator/consumer.h>
34
35 #include "isp.h"
36 #include "ispreg.h"
37 #include "ispccp2.h"
38
39 /* Number of LCX channels */
40 #define CCP2_LCx_CHANS_NUM 3
41 /* Max/Min size for CCP2 video port */
42 #define ISPCCP2_DAT_START_MIN 0
43 #define ISPCCP2_DAT_START_MAX 4095
44 #define ISPCCP2_DAT_SIZE_MIN 0
45 #define ISPCCP2_DAT_SIZE_MAX 4095
46 #define ISPCCP2_VPCLK_FRACDIV 65536
47 #define ISPCCP2_LCx_CTRL_FORMAT_RAW8_DPCM10_VP 0x12
48 #define ISPCCP2_LCx_CTRL_FORMAT_RAW10_VP 0x16
49 /* Max/Min size for CCP2 memory channel */
50 #define ISPCCP2_LCM_HSIZE_COUNT_MIN 16
51 #define ISPCCP2_LCM_HSIZE_COUNT_MAX 8191
52 #define ISPCCP2_LCM_HSIZE_SKIP_MIN 0
53 #define ISPCCP2_LCM_HSIZE_SKIP_MAX 8191
54 #define ISPCCP2_LCM_VSIZE_MIN 1
55 #define ISPCCP2_LCM_VSIZE_MAX 8191
56 #define ISPCCP2_LCM_HWORDS_MIN 1
57 #define ISPCCP2_LCM_HWORDS_MAX 4095
58 #define ISPCCP2_LCM_CTRL_BURST_SIZE_32X 5
59 #define ISPCCP2_LCM_CTRL_READ_THROTTLE_FULL 0
60 #define ISPCCP2_LCM_CTRL_SRC_DECOMPR_DPCM10 2
61 #define ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW8 2
62 #define ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW10 3
63 #define ISPCCP2_LCM_CTRL_DST_FORMAT_RAW10 3
64 #define ISPCCP2_LCM_CTRL_DST_PORT_VP 0
65 #define ISPCCP2_LCM_CTRL_DST_PORT_MEM 1
66
67 /* Set only the required bits */
68 #define BIT_SET(var, shift, mask, val) \
69 do { \
70 var = ((var) & ~((mask) << (shift))) \
71 | ((val) << (shift)); \
72 } while (0)
73
74 /*
75 * ccp2_print_status - Print current CCP2 module register values.
76 */
77 #define CCP2_PRINT_REGISTER(isp, name)\
78 dev_dbg(isp->dev, "###CCP2 " #name "=0x%08x\n", \
79 isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_##name))
80
81 static void ccp2_print_status(struct isp_ccp2_device *ccp2)
82 {
83 struct isp_device *isp = to_isp_device(ccp2);
84
85 dev_dbg(isp->dev, "-------------CCP2 Register dump-------------\n");
86
87 CCP2_PRINT_REGISTER(isp, SYSCONFIG);
88 CCP2_PRINT_REGISTER(isp, SYSSTATUS);
89 CCP2_PRINT_REGISTER(isp, LC01_IRQENABLE);
90 CCP2_PRINT_REGISTER(isp, LC01_IRQSTATUS);
91 CCP2_PRINT_REGISTER(isp, LC23_IRQENABLE);
92 CCP2_PRINT_REGISTER(isp, LC23_IRQSTATUS);
93 CCP2_PRINT_REGISTER(isp, LCM_IRQENABLE);
94 CCP2_PRINT_REGISTER(isp, LCM_IRQSTATUS);
95 CCP2_PRINT_REGISTER(isp, CTRL);
96 CCP2_PRINT_REGISTER(isp, LCx_CTRL(0));
97 CCP2_PRINT_REGISTER(isp, LCx_CODE(0));
98 CCP2_PRINT_REGISTER(isp, LCx_STAT_START(0));
99 CCP2_PRINT_REGISTER(isp, LCx_STAT_SIZE(0));
100 CCP2_PRINT_REGISTER(isp, LCx_SOF_ADDR(0));
101 CCP2_PRINT_REGISTER(isp, LCx_EOF_ADDR(0));
102 CCP2_PRINT_REGISTER(isp, LCx_DAT_START(0));
103 CCP2_PRINT_REGISTER(isp, LCx_DAT_SIZE(0));
104 CCP2_PRINT_REGISTER(isp, LCx_DAT_PING_ADDR(0));
105 CCP2_PRINT_REGISTER(isp, LCx_DAT_PONG_ADDR(0));
106 CCP2_PRINT_REGISTER(isp, LCx_DAT_OFST(0));
107 CCP2_PRINT_REGISTER(isp, LCM_CTRL);
108 CCP2_PRINT_REGISTER(isp, LCM_VSIZE);
109 CCP2_PRINT_REGISTER(isp, LCM_HSIZE);
110 CCP2_PRINT_REGISTER(isp, LCM_PREFETCH);
111 CCP2_PRINT_REGISTER(isp, LCM_SRC_ADDR);
112 CCP2_PRINT_REGISTER(isp, LCM_SRC_OFST);
113 CCP2_PRINT_REGISTER(isp, LCM_DST_ADDR);
114 CCP2_PRINT_REGISTER(isp, LCM_DST_OFST);
115
116 dev_dbg(isp->dev, "--------------------------------------------\n");
117 }
118
119 /*
120 * ccp2_reset - Reset the CCP2
121 * @ccp2: pointer to ISP CCP2 device
122 */
123 static void ccp2_reset(struct isp_ccp2_device *ccp2)
124 {
125 struct isp_device *isp = to_isp_device(ccp2);
126 int i = 0;
127
128 /* Reset the CSI1/CCP2B and wait for reset to complete */
129 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_SYSCONFIG,
130 ISPCCP2_SYSCONFIG_SOFT_RESET);
131 while (!(isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_SYSSTATUS) &
132 ISPCCP2_SYSSTATUS_RESET_DONE)) {
133 udelay(10);
134 if (i++ > 10) { /* try read 10 times */
135 dev_warn(isp->dev,
136 "omap3_isp: timeout waiting for ccp2 reset\n");
137 break;
138 }
139 }
140 }
141
142 /*
143 * ccp2_pwr_cfg - Configure the power mode settings
144 * @ccp2: pointer to ISP CCP2 device
145 */
146 static void ccp2_pwr_cfg(struct isp_ccp2_device *ccp2)
147 {
148 struct isp_device *isp = to_isp_device(ccp2);
149
150 isp_reg_writel(isp, ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SMART |
151 ((isp->revision == ISP_REVISION_15_0 && isp->autoidle) ?
152 ISPCCP2_SYSCONFIG_AUTO_IDLE : 0),
153 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_SYSCONFIG);
154 }
155
156 /*
157 * ccp2_if_enable - Enable CCP2 interface.
158 * @ccp2: pointer to ISP CCP2 device
159 * @enable: enable/disable flag
160 */
161 static void ccp2_if_enable(struct isp_ccp2_device *ccp2, u8 enable)
162 {
163 struct isp_device *isp = to_isp_device(ccp2);
164 struct isp_pipeline *pipe = to_isp_pipeline(&ccp2->subdev.entity);
165 int i;
166
167 if (enable && ccp2->vdds_csib)
168 regulator_enable(ccp2->vdds_csib);
169
170 /* Enable/Disable all the LCx channels */
171 for (i = 0; i < CCP2_LCx_CHANS_NUM; i++)
172 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_CTRL(i),
173 ISPCCP2_LCx_CTRL_CHAN_EN,
174 enable ? ISPCCP2_LCx_CTRL_CHAN_EN : 0);
175
176 /* Enable/Disable ccp2 interface in ccp2 mode */
177 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL,
178 ISPCCP2_CTRL_MODE | ISPCCP2_CTRL_IF_EN,
179 enable ? (ISPCCP2_CTRL_MODE | ISPCCP2_CTRL_IF_EN) : 0);
180
181 /* For frame count propagation */
182 if (pipe->do_propagation) {
183 /* We may want the Frame Start IRQ from LC0 */
184 if (enable)
185 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2,
186 ISPCCP2_LC01_IRQENABLE,
187 ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ);
188 else
189 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCP2,
190 ISPCCP2_LC01_IRQENABLE,
191 ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ);
192 }
193
194 if (!enable && ccp2->vdds_csib)
195 regulator_disable(ccp2->vdds_csib);
196 }
197
198 /*
199 * ccp2_mem_enable - Enable CCP2 memory interface.
200 * @ccp2: pointer to ISP CCP2 device
201 * @enable: enable/disable flag
202 */
203 static void ccp2_mem_enable(struct isp_ccp2_device *ccp2, u8 enable)
204 {
205 struct isp_device *isp = to_isp_device(ccp2);
206
207 if (enable)
208 ccp2_if_enable(ccp2, 0);
209
210 /* Enable/Disable ccp2 interface in ccp2 mode */
211 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL,
212 ISPCCP2_CTRL_MODE, enable ? ISPCCP2_CTRL_MODE : 0);
213
214 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_CTRL,
215 ISPCCP2_LCM_CTRL_CHAN_EN,
216 enable ? ISPCCP2_LCM_CTRL_CHAN_EN : 0);
217 }
218
219 /*
220 * ccp2_phyif_config - Initialize CCP2 phy interface config
221 * @ccp2: Pointer to ISP CCP2 device
222 * @config: CCP2 platform data
223 *
224 * Configure the CCP2 physical interface module from platform data.
225 *
226 * Returns -EIO if strobe is chosen in CSI1 mode, or 0 on success.
227 */
228 static int ccp2_phyif_config(struct isp_ccp2_device *ccp2,
229 const struct isp_ccp2_platform_data *pdata)
230 {
231 struct isp_device *isp = to_isp_device(ccp2);
232 u32 val;
233
234 /* CCP2B mode */
235 val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL) |
236 ISPCCP2_CTRL_IO_OUT_SEL | ISPCCP2_CTRL_MODE;
237 /* Data/strobe physical layer */
238 BIT_SET(val, ISPCCP2_CTRL_PHY_SEL_SHIFT, ISPCCP2_CTRL_PHY_SEL_MASK,
239 pdata->phy_layer);
240 BIT_SET(val, ISPCCP2_CTRL_INV_SHIFT, ISPCCP2_CTRL_INV_MASK,
241 pdata->strobe_clk_pol);
242 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);
243
244 val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);
245 if (!(val & ISPCCP2_CTRL_MODE)) {
246 if (pdata->ccp2_mode == ISP_CCP2_MODE_CCP2)
247 dev_warn(isp->dev, "OMAP3 CCP2 bus not available\n");
248 if (pdata->phy_layer == ISP_CCP2_PHY_DATA_STROBE)
249 /* Strobe mode requires CCP2 */
250 return -EIO;
251 }
252
253 return 0;
254 }
255
256 /*
257 * ccp2_vp_config - Initialize CCP2 video port interface.
258 * @ccp2: Pointer to ISP CCP2 device
259 * @vpclk_div: Video port divisor
260 *
261 * Configure the CCP2 video port with the given clock divisor. The valid divisor
262 * values depend on the ISP revision:
263 *
264 * - revision 1.0 and 2.0 1 to 4
265 * - revision 15.0 1 to 65536
266 *
267 * The exact divisor value used might differ from the requested value, as ISP
268 * revision 15.0 represent the divisor by 65536 divided by an integer.
269 */
270 static void ccp2_vp_config(struct isp_ccp2_device *ccp2,
271 unsigned int vpclk_div)
272 {
273 struct isp_device *isp = to_isp_device(ccp2);
274 u32 val;
275
276 /* ISPCCP2_CTRL Video port */
277 val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);
278 val |= ISPCCP2_CTRL_VP_ONLY_EN; /* Disable the memory write port */
279
280 if (isp->revision == ISP_REVISION_15_0) {
281 vpclk_div = clamp_t(unsigned int, vpclk_div, 1, 65536);
282 vpclk_div = min(ISPCCP2_VPCLK_FRACDIV / vpclk_div, 65535U);
283 BIT_SET(val, ISPCCP2_CTRL_VPCLK_DIV_SHIFT,
284 ISPCCP2_CTRL_VPCLK_DIV_MASK, vpclk_div);
285 } else {
286 vpclk_div = clamp_t(unsigned int, vpclk_div, 1, 4);
287 BIT_SET(val, ISPCCP2_CTRL_VP_OUT_CTRL_SHIFT,
288 ISPCCP2_CTRL_VP_OUT_CTRL_MASK, vpclk_div - 1);
289 }
290
291 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);
292 }
293
294 /*
295 * ccp2_lcx_config - Initialize CCP2 logical channel interface.
296 * @ccp2: Pointer to ISP CCP2 device
297 * @config: Pointer to ISP LCx config structure.
298 *
299 * This will analyze the parameters passed by the interface config
300 * and configure CSI1/CCP2 logical channel
301 *
302 */
303 static void ccp2_lcx_config(struct isp_ccp2_device *ccp2,
304 struct isp_interface_lcx_config *config)
305 {
306 struct isp_device *isp = to_isp_device(ccp2);
307 u32 val, format;
308
309 switch (config->format) {
310 case V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8:
311 format = ISPCCP2_LCx_CTRL_FORMAT_RAW8_DPCM10_VP;
312 break;
313 case V4L2_MBUS_FMT_SGRBG10_1X10:
314 default:
315 format = ISPCCP2_LCx_CTRL_FORMAT_RAW10_VP; /* RAW10+VP */
316 break;
317 }
318 /* ISPCCP2_LCx_CTRL logical channel #0 */
319 val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_CTRL(0))
320 | (ISPCCP2_LCx_CTRL_REGION_EN); /* Region */
321
322 if (isp->revision == ISP_REVISION_15_0) {
323 /* CRC */
324 BIT_SET(val, ISPCCP2_LCx_CTRL_CRC_SHIFT_15_0,
325 ISPCCP2_LCx_CTRL_CRC_MASK,
326 config->crc);
327 /* Format = RAW10+VP or RAW8+DPCM10+VP*/
328 BIT_SET(val, ISPCCP2_LCx_CTRL_FORMAT_SHIFT_15_0,
329 ISPCCP2_LCx_CTRL_FORMAT_MASK_15_0, format);
330 } else {
331 BIT_SET(val, ISPCCP2_LCx_CTRL_CRC_SHIFT,
332 ISPCCP2_LCx_CTRL_CRC_MASK,
333 config->crc);
334
335 BIT_SET(val, ISPCCP2_LCx_CTRL_FORMAT_SHIFT,
336 ISPCCP2_LCx_CTRL_FORMAT_MASK, format);
337 }
338 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_CTRL(0));
339
340 /* ISPCCP2_DAT_START for logical channel #0 */
341 isp_reg_writel(isp, config->data_start << ISPCCP2_LCx_DAT_SHIFT,
342 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_DAT_START(0));
343
344 /* ISPCCP2_DAT_SIZE for logical channel #0 */
345 isp_reg_writel(isp, config->data_size << ISPCCP2_LCx_DAT_SHIFT,
346 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_DAT_SIZE(0));
347
348 /* Enable error IRQs for logical channel #0 */
349 val = ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ |
350 ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ |
351 ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ |
352 ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ |
353 ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ |
354 ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ |
355 ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ;
356
357 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LC01_IRQSTATUS);
358 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LC01_IRQENABLE, val);
359 }
360
361 /*
362 * ccp2_if_configure - Configure ccp2 with data from sensor
363 * @ccp2: Pointer to ISP CCP2 device
364 *
365 * Return 0 on success or a negative error code
366 */
367 static int ccp2_if_configure(struct isp_ccp2_device *ccp2)
368 {
369 const struct isp_v4l2_subdevs_group *pdata;
370 struct v4l2_mbus_framefmt *format;
371 struct media_pad *pad;
372 struct v4l2_subdev *sensor;
373 u32 lines = 0;
374 int ret;
375
376 ccp2_pwr_cfg(ccp2);
377
378 pad = media_entity_remote_source(&ccp2->pads[CCP2_PAD_SINK]);
379 sensor = media_entity_to_v4l2_subdev(pad->entity);
380 pdata = sensor->host_priv;
381
382 ret = ccp2_phyif_config(ccp2, &pdata->bus.ccp2);
383 if (ret < 0)
384 return ret;
385
386 ccp2_vp_config(ccp2, pdata->bus.ccp2.vpclk_div + 1);
387
388 v4l2_subdev_call(sensor, sensor, g_skip_top_lines, &lines);
389
390 format = &ccp2->formats[CCP2_PAD_SINK];
391
392 ccp2->if_cfg.data_start = lines;
393 ccp2->if_cfg.crc = pdata->bus.ccp2.crc;
394 ccp2->if_cfg.format = format->code;
395 ccp2->if_cfg.data_size = format->height;
396
397 ccp2_lcx_config(ccp2, &ccp2->if_cfg);
398
399 return 0;
400 }
401
402 static int ccp2_adjust_bandwidth(struct isp_ccp2_device *ccp2)
403 {
404 struct isp_pipeline *pipe = to_isp_pipeline(&ccp2->subdev.entity);
405 struct isp_device *isp = to_isp_device(ccp2);
406 const struct v4l2_mbus_framefmt *ofmt = &ccp2->formats[CCP2_PAD_SOURCE];
407 unsigned long l3_ick = pipe->l3_ick;
408 struct v4l2_fract *timeperframe;
409 unsigned int vpclk_div = 2;
410 unsigned int value;
411 u64 bound;
412 u64 area;
413
414 /* Compute the minimum clock divisor, based on the pipeline maximum
415 * data rate. This is an absolute lower bound if we don't want SBL
416 * overflows, so round the value up.
417 */
418 vpclk_div = max_t(unsigned int, DIV_ROUND_UP(l3_ick, pipe->max_rate),
419 vpclk_div);
420
421 /* Compute the maximum clock divisor, based on the requested frame rate.
422 * This is a soft lower bound to achieve a frame rate equal or higher
423 * than the requested value, so round the value down.
424 */
425 timeperframe = &pipe->max_timeperframe;
426
427 if (timeperframe->numerator) {
428 area = ofmt->width * ofmt->height;
429 bound = div_u64(area * timeperframe->denominator,
430 timeperframe->numerator);
431 value = min_t(u64, bound, l3_ick);
432 vpclk_div = max_t(unsigned int, l3_ick / value, vpclk_div);
433 }
434
435 dev_dbg(isp->dev, "%s: minimum clock divisor = %u\n", __func__,
436 vpclk_div);
437
438 return vpclk_div;
439 }
440
441 /*
442 * ccp2_mem_configure - Initialize CCP2 memory input/output interface
443 * @ccp2: Pointer to ISP CCP2 device
444 * @config: Pointer to ISP mem interface config structure
445 *
446 * This will analyze the parameters passed by the interface config
447 * structure, and configure the respective registers for proper
448 * CSI1/CCP2 memory input.
449 */
450 static void ccp2_mem_configure(struct isp_ccp2_device *ccp2,
451 struct isp_interface_mem_config *config)
452 {
453 struct isp_device *isp = to_isp_device(ccp2);
454 u32 sink_pixcode = ccp2->formats[CCP2_PAD_SINK].code;
455 u32 source_pixcode = ccp2->formats[CCP2_PAD_SOURCE].code;
456 unsigned int dpcm_decompress = 0;
457 u32 val, hwords;
458
459 if (sink_pixcode != source_pixcode &&
460 sink_pixcode == V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8)
461 dpcm_decompress = 1;
462
463 ccp2_pwr_cfg(ccp2);
464
465 /* Hsize, Skip */
466 isp_reg_writel(isp, ISPCCP2_LCM_HSIZE_SKIP_MIN |
467 (config->hsize_count << ISPCCP2_LCM_HSIZE_SHIFT),
468 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_HSIZE);
469
470 /* Vsize, no. of lines */
471 isp_reg_writel(isp, config->vsize_count << ISPCCP2_LCM_VSIZE_SHIFT,
472 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_VSIZE);
473
474 if (ccp2->video_in.bpl_padding == 0)
475 config->src_ofst = 0;
476 else
477 config->src_ofst = ccp2->video_in.bpl_value;
478
479 isp_reg_writel(isp, config->src_ofst, OMAP3_ISP_IOMEM_CCP2,
480 ISPCCP2_LCM_SRC_OFST);
481
482 /* Source and Destination formats */
483 val = ISPCCP2_LCM_CTRL_DST_FORMAT_RAW10 <<
484 ISPCCP2_LCM_CTRL_DST_FORMAT_SHIFT;
485
486 if (dpcm_decompress) {
487 /* source format is RAW8 */
488 val |= ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW8 <<
489 ISPCCP2_LCM_CTRL_SRC_FORMAT_SHIFT;
490
491 /* RAW8 + DPCM10 - simple predictor */
492 val |= ISPCCP2_LCM_CTRL_SRC_DPCM_PRED;
493
494 /* enable source DPCM decompression */
495 val |= ISPCCP2_LCM_CTRL_SRC_DECOMPR_DPCM10 <<
496 ISPCCP2_LCM_CTRL_SRC_DECOMPR_SHIFT;
497 } else {
498 /* source format is RAW10 */
499 val |= ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW10 <<
500 ISPCCP2_LCM_CTRL_SRC_FORMAT_SHIFT;
501 }
502
503 /* Burst size to 32x64 */
504 val |= ISPCCP2_LCM_CTRL_BURST_SIZE_32X <<
505 ISPCCP2_LCM_CTRL_BURST_SIZE_SHIFT;
506
507 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_CTRL);
508
509 /* Prefetch setup */
510 if (dpcm_decompress)
511 hwords = (ISPCCP2_LCM_HSIZE_SKIP_MIN +
512 config->hsize_count) >> 3;
513 else
514 hwords = (ISPCCP2_LCM_HSIZE_SKIP_MIN +
515 config->hsize_count) >> 2;
516
517 isp_reg_writel(isp, hwords << ISPCCP2_LCM_PREFETCH_SHIFT,
518 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_PREFETCH);
519
520 /* Video port */
521 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL,
522 ISPCCP2_CTRL_IO_OUT_SEL | ISPCCP2_CTRL_MODE);
523 ccp2_vp_config(ccp2, ccp2_adjust_bandwidth(ccp2));
524
525 /* Clear LCM interrupts */
526 isp_reg_writel(isp, ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ |
527 ISPCCP2_LCM_IRQSTATUS_EOF_IRQ,
528 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_IRQSTATUS);
529
530 /* Enable LCM interupts */
531 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_IRQENABLE,
532 ISPCCP2_LCM_IRQSTATUS_EOF_IRQ |
533 ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ);
534 }
535
536 /*
537 * ccp2_set_inaddr - Sets memory address of input frame.
538 * @ccp2: Pointer to ISP CCP2 device
539 * @addr: 32bit memory address aligned on 32byte boundary.
540 *
541 * Configures the memory address from which the input frame is to be read.
542 */
543 static void ccp2_set_inaddr(struct isp_ccp2_device *ccp2, u32 addr)
544 {
545 struct isp_device *isp = to_isp_device(ccp2);
546
547 isp_reg_writel(isp, addr, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_SRC_ADDR);
548 }
549
550 /* -----------------------------------------------------------------------------
551 * Interrupt handling
552 */
553
554 static void ccp2_isr_buffer(struct isp_ccp2_device *ccp2)
555 {
556 struct isp_pipeline *pipe = to_isp_pipeline(&ccp2->subdev.entity);
557 struct isp_buffer *buffer;
558
559 buffer = omap3isp_video_buffer_next(&ccp2->video_in);
560 if (buffer != NULL)
561 ccp2_set_inaddr(ccp2, buffer->isp_addr);
562
563 pipe->state |= ISP_PIPELINE_IDLE_INPUT;
564
565 if (ccp2->state == ISP_PIPELINE_STREAM_SINGLESHOT) {
566 if (isp_pipeline_ready(pipe))
567 omap3isp_pipeline_set_stream(pipe,
568 ISP_PIPELINE_STREAM_SINGLESHOT);
569 }
570 }
571
572 /*
573 * omap3isp_ccp2_isr - Handle ISP CCP2 interrupts
574 * @ccp2: Pointer to ISP CCP2 device
575 *
576 * This will handle the CCP2 interrupts
577 */
578 void omap3isp_ccp2_isr(struct isp_ccp2_device *ccp2)
579 {
580 struct isp_pipeline *pipe = to_isp_pipeline(&ccp2->subdev.entity);
581 struct isp_device *isp = to_isp_device(ccp2);
582 static const u32 ISPCCP2_LC01_ERROR =
583 ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ |
584 ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ |
585 ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ |
586 ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ |
587 ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ |
588 ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ;
589 u32 lcx_irqstatus, lcm_irqstatus;
590
591 /* First clear the interrupts */
592 lcx_irqstatus = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2,
593 ISPCCP2_LC01_IRQSTATUS);
594 isp_reg_writel(isp, lcx_irqstatus, OMAP3_ISP_IOMEM_CCP2,
595 ISPCCP2_LC01_IRQSTATUS);
596
597 lcm_irqstatus = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2,
598 ISPCCP2_LCM_IRQSTATUS);
599 isp_reg_writel(isp, lcm_irqstatus, OMAP3_ISP_IOMEM_CCP2,
600 ISPCCP2_LCM_IRQSTATUS);
601 /* Errors */
602 if (lcx_irqstatus & ISPCCP2_LC01_ERROR) {
603 pipe->error = true;
604 dev_dbg(isp->dev, "CCP2 err:%x\n", lcx_irqstatus);
605 return;
606 }
607
608 if (lcm_irqstatus & ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ) {
609 pipe->error = true;
610 dev_dbg(isp->dev, "CCP2 OCP err:%x\n", lcm_irqstatus);
611 }
612
613 if (omap3isp_module_sync_is_stopping(&ccp2->wait, &ccp2->stopping))
614 return;
615
616 /* Frame number propagation */
617 if (lcx_irqstatus & ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ) {
618 struct isp_pipeline *pipe =
619 to_isp_pipeline(&ccp2->subdev.entity);
620 if (pipe->do_propagation)
621 atomic_inc(&pipe->frame_number);
622 }
623
624 /* Handle queued buffers on frame end interrupts */
625 if (lcm_irqstatus & ISPCCP2_LCM_IRQSTATUS_EOF_IRQ)
626 ccp2_isr_buffer(ccp2);
627 }
628
629 /* -----------------------------------------------------------------------------
630 * V4L2 subdev operations
631 */
632
633 static const unsigned int ccp2_fmts[] = {
634 V4L2_MBUS_FMT_SGRBG10_1X10,
635 V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8,
636 };
637
638 /*
639 * __ccp2_get_format - helper function for getting ccp2 format
640 * @ccp2 : Pointer to ISP CCP2 device
641 * @fh : V4L2 subdev file handle
642 * @pad : pad number
643 * @which : wanted subdev format
644 * return format structure or NULL on error
645 */
646 static struct v4l2_mbus_framefmt *
647 __ccp2_get_format(struct isp_ccp2_device *ccp2, struct v4l2_subdev_fh *fh,
648 unsigned int pad, enum v4l2_subdev_format_whence which)
649 {
650 if (which == V4L2_SUBDEV_FORMAT_TRY)
651 return v4l2_subdev_get_try_format(fh, pad);
652 else
653 return &ccp2->formats[pad];
654 }
655
656 /*
657 * ccp2_try_format - Handle try format by pad subdev method
658 * @ccp2 : Pointer to ISP CCP2 device
659 * @fh : V4L2 subdev file handle
660 * @pad : pad num
661 * @fmt : pointer to v4l2 mbus format structure
662 * @which : wanted subdev format
663 */
664 static void ccp2_try_format(struct isp_ccp2_device *ccp2,
665 struct v4l2_subdev_fh *fh, unsigned int pad,
666 struct v4l2_mbus_framefmt *fmt,
667 enum v4l2_subdev_format_whence which)
668 {
669 struct v4l2_mbus_framefmt *format;
670
671 switch (pad) {
672 case CCP2_PAD_SINK:
673 if (fmt->code != V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8)
674 fmt->code = V4L2_MBUS_FMT_SGRBG10_1X10;
675
676 if (ccp2->input == CCP2_INPUT_SENSOR) {
677 fmt->width = clamp_t(u32, fmt->width,
678 ISPCCP2_DAT_START_MIN,
679 ISPCCP2_DAT_START_MAX);
680 fmt->height = clamp_t(u32, fmt->height,
681 ISPCCP2_DAT_SIZE_MIN,
682 ISPCCP2_DAT_SIZE_MAX);
683 } else if (ccp2->input == CCP2_INPUT_MEMORY) {
684 fmt->width = clamp_t(u32, fmt->width,
685 ISPCCP2_LCM_HSIZE_COUNT_MIN,
686 ISPCCP2_LCM_HSIZE_COUNT_MAX);
687 fmt->height = clamp_t(u32, fmt->height,
688 ISPCCP2_LCM_VSIZE_MIN,
689 ISPCCP2_LCM_VSIZE_MAX);
690 }
691 break;
692
693 case CCP2_PAD_SOURCE:
694 /* Source format - copy sink format and change pixel code
695 * to SGRBG10_1X10 as we don't support CCP2 write to memory.
696 * When CCP2 write to memory feature will be added this
697 * should be changed properly.
698 */
699 format = __ccp2_get_format(ccp2, fh, CCP2_PAD_SINK, which);
700 memcpy(fmt, format, sizeof(*fmt));
701 fmt->code = V4L2_MBUS_FMT_SGRBG10_1X10;
702 break;
703 }
704
705 fmt->field = V4L2_FIELD_NONE;
706 fmt->colorspace = V4L2_COLORSPACE_SRGB;
707 }
708
709 /*
710 * ccp2_enum_mbus_code - Handle pixel format enumeration
711 * @sd : pointer to v4l2 subdev structure
712 * @fh : V4L2 subdev file handle
713 * @code : pointer to v4l2_subdev_mbus_code_enum structure
714 * return -EINVAL or zero on success
715 */
716 static int ccp2_enum_mbus_code(struct v4l2_subdev *sd,
717 struct v4l2_subdev_fh *fh,
718 struct v4l2_subdev_mbus_code_enum *code)
719 {
720 struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
721 struct v4l2_mbus_framefmt *format;
722
723 if (code->pad == CCP2_PAD_SINK) {
724 if (code->index >= ARRAY_SIZE(ccp2_fmts))
725 return -EINVAL;
726
727 code->code = ccp2_fmts[code->index];
728 } else {
729 if (code->index != 0)
730 return -EINVAL;
731
732 format = __ccp2_get_format(ccp2, fh, CCP2_PAD_SINK,
733 V4L2_SUBDEV_FORMAT_TRY);
734 code->code = format->code;
735 }
736
737 return 0;
738 }
739
740 static int ccp2_enum_frame_size(struct v4l2_subdev *sd,
741 struct v4l2_subdev_fh *fh,
742 struct v4l2_subdev_frame_size_enum *fse)
743 {
744 struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
745 struct v4l2_mbus_framefmt format;
746
747 if (fse->index != 0)
748 return -EINVAL;
749
750 format.code = fse->code;
751 format.width = 1;
752 format.height = 1;
753 ccp2_try_format(ccp2, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY);
754 fse->min_width = format.width;
755 fse->min_height = format.height;
756
757 if (format.code != fse->code)
758 return -EINVAL;
759
760 format.code = fse->code;
761 format.width = -1;
762 format.height = -1;
763 ccp2_try_format(ccp2, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY);
764 fse->max_width = format.width;
765 fse->max_height = format.height;
766
767 return 0;
768 }
769
770 /*
771 * ccp2_get_format - Handle get format by pads subdev method
772 * @sd : pointer to v4l2 subdev structure
773 * @fh : V4L2 subdev file handle
774 * @fmt : pointer to v4l2 subdev format structure
775 * return -EINVAL or zero on success
776 */
777 static int ccp2_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
778 struct v4l2_subdev_format *fmt)
779 {
780 struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
781 struct v4l2_mbus_framefmt *format;
782
783 format = __ccp2_get_format(ccp2, fh, fmt->pad, fmt->which);
784 if (format == NULL)
785 return -EINVAL;
786
787 fmt->format = *format;
788 return 0;
789 }
790
791 /*
792 * ccp2_set_format - Handle set format by pads subdev method
793 * @sd : pointer to v4l2 subdev structure
794 * @fh : V4L2 subdev file handle
795 * @fmt : pointer to v4l2 subdev format structure
796 * returns zero
797 */
798 static int ccp2_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
799 struct v4l2_subdev_format *fmt)
800 {
801 struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
802 struct v4l2_mbus_framefmt *format;
803
804 format = __ccp2_get_format(ccp2, fh, fmt->pad, fmt->which);
805 if (format == NULL)
806 return -EINVAL;
807
808 ccp2_try_format(ccp2, fh, fmt->pad, &fmt->format, fmt->which);
809 *format = fmt->format;
810
811 /* Propagate the format from sink to source */
812 if (fmt->pad == CCP2_PAD_SINK) {
813 format = __ccp2_get_format(ccp2, fh, CCP2_PAD_SOURCE,
814 fmt->which);
815 *format = fmt->format;
816 ccp2_try_format(ccp2, fh, CCP2_PAD_SOURCE, format, fmt->which);
817 }
818
819 return 0;
820 }
821
822 /*
823 * ccp2_init_formats - Initialize formats on all pads
824 * @sd: ISP CCP2 V4L2 subdevice
825 * @fh: V4L2 subdev file handle
826 *
827 * Initialize all pad formats with default values. If fh is not NULL, try
828 * formats are initialized on the file handle. Otherwise active formats are
829 * initialized on the device.
830 */
831 static int ccp2_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
832 {
833 struct v4l2_subdev_format format;
834
835 memset(&format, 0, sizeof(format));
836 format.pad = CCP2_PAD_SINK;
837 format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
838 format.format.code = V4L2_MBUS_FMT_SGRBG10_1X10;
839 format.format.width = 4096;
840 format.format.height = 4096;
841 ccp2_set_format(sd, fh, &format);
842
843 return 0;
844 }
845
846 /*
847 * ccp2_s_stream - Enable/Disable streaming on ccp2 subdev
848 * @sd : pointer to v4l2 subdev structure
849 * @enable: 1 == Enable, 0 == Disable
850 * return zero
851 */
852 static int ccp2_s_stream(struct v4l2_subdev *sd, int enable)
853 {
854 struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
855 struct isp_device *isp = to_isp_device(ccp2);
856 struct device *dev = to_device(ccp2);
857 int ret;
858
859 if (ccp2->state == ISP_PIPELINE_STREAM_STOPPED) {
860 if (enable == ISP_PIPELINE_STREAM_STOPPED)
861 return 0;
862 atomic_set(&ccp2->stopping, 0);
863 }
864
865 switch (enable) {
866 case ISP_PIPELINE_STREAM_CONTINUOUS:
867 if (ccp2->phy) {
868 ret = omap3isp_csiphy_acquire(ccp2->phy);
869 if (ret < 0)
870 return ret;
871 }
872
873 ccp2_if_configure(ccp2);
874 ccp2_print_status(ccp2);
875
876 /* Enable CSI1/CCP2 interface */
877 ccp2_if_enable(ccp2, 1);
878 break;
879
880 case ISP_PIPELINE_STREAM_SINGLESHOT:
881 if (ccp2->state != ISP_PIPELINE_STREAM_SINGLESHOT) {
882 struct v4l2_mbus_framefmt *format;
883
884 format = &ccp2->formats[CCP2_PAD_SINK];
885
886 ccp2->mem_cfg.hsize_count = format->width;
887 ccp2->mem_cfg.vsize_count = format->height;
888 ccp2->mem_cfg.src_ofst = 0;
889
890 ccp2_mem_configure(ccp2, &ccp2->mem_cfg);
891 omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_CSI1_READ);
892 ccp2_print_status(ccp2);
893 }
894 ccp2_mem_enable(ccp2, 1);
895 break;
896
897 case ISP_PIPELINE_STREAM_STOPPED:
898 if (omap3isp_module_sync_idle(&sd->entity, &ccp2->wait,
899 &ccp2->stopping))
900 dev_dbg(dev, "%s: module stop timeout.\n", sd->name);
901 if (ccp2->input == CCP2_INPUT_MEMORY) {
902 ccp2_mem_enable(ccp2, 0);
903 omap3isp_sbl_disable(isp, OMAP3_ISP_SBL_CSI1_READ);
904 } else if (ccp2->input == CCP2_INPUT_SENSOR) {
905 /* Disable CSI1/CCP2 interface */
906 ccp2_if_enable(ccp2, 0);
907 if (ccp2->phy)
908 omap3isp_csiphy_release(ccp2->phy);
909 }
910 break;
911 }
912
913 ccp2->state = enable;
914 return 0;
915 }
916
917 /* subdev video operations */
918 static const struct v4l2_subdev_video_ops ccp2_sd_video_ops = {
919 .s_stream = ccp2_s_stream,
920 };
921
922 /* subdev pad operations */
923 static const struct v4l2_subdev_pad_ops ccp2_sd_pad_ops = {
924 .enum_mbus_code = ccp2_enum_mbus_code,
925 .enum_frame_size = ccp2_enum_frame_size,
926 .get_fmt = ccp2_get_format,
927 .set_fmt = ccp2_set_format,
928 };
929
930 /* subdev operations */
931 static const struct v4l2_subdev_ops ccp2_sd_ops = {
932 .video = &ccp2_sd_video_ops,
933 .pad = &ccp2_sd_pad_ops,
934 };
935
936 /* subdev internal operations */
937 static const struct v4l2_subdev_internal_ops ccp2_sd_internal_ops = {
938 .open = ccp2_init_formats,
939 };
940
941 /* --------------------------------------------------------------------------
942 * ISP ccp2 video device node
943 */
944
945 /*
946 * ccp2_video_queue - Queue video buffer.
947 * @video : Pointer to isp video structure
948 * @buffer: Pointer to isp_buffer structure
949 * return -EIO or zero on success
950 */
951 static int ccp2_video_queue(struct isp_video *video, struct isp_buffer *buffer)
952 {
953 struct isp_ccp2_device *ccp2 = &video->isp->isp_ccp2;
954
955 ccp2_set_inaddr(ccp2, buffer->isp_addr);
956 return 0;
957 }
958
959 static const struct isp_video_operations ccp2_video_ops = {
960 .queue = ccp2_video_queue,
961 };
962
963 /* -----------------------------------------------------------------------------
964 * Media entity operations
965 */
966
967 /*
968 * ccp2_link_setup - Setup ccp2 connections.
969 * @entity : Pointer to media entity structure
970 * @local : Pointer to local pad array
971 * @remote : Pointer to remote pad array
972 * @flags : Link flags
973 * return -EINVAL on error or zero on success
974 */
975 static int ccp2_link_setup(struct media_entity *entity,
976 const struct media_pad *local,
977 const struct media_pad *remote, u32 flags)
978 {
979 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
980 struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
981
982 switch (local->index | media_entity_type(remote->entity)) {
983 case CCP2_PAD_SINK | MEDIA_ENT_T_DEVNODE:
984 /* read from memory */
985 if (flags & MEDIA_LNK_FL_ENABLED) {
986 if (ccp2->input == CCP2_INPUT_SENSOR)
987 return -EBUSY;
988 ccp2->input = CCP2_INPUT_MEMORY;
989 } else {
990 if (ccp2->input == CCP2_INPUT_MEMORY)
991 ccp2->input = CCP2_INPUT_NONE;
992 }
993 break;
994
995 case CCP2_PAD_SINK | MEDIA_ENT_T_V4L2_SUBDEV:
996 /* read from sensor/phy */
997 if (flags & MEDIA_LNK_FL_ENABLED) {
998 if (ccp2->input == CCP2_INPUT_MEMORY)
999 return -EBUSY;
1000 ccp2->input = CCP2_INPUT_SENSOR;
1001 } else {
1002 if (ccp2->input == CCP2_INPUT_SENSOR)
1003 ccp2->input = CCP2_INPUT_NONE;
1004 } break;
1005
1006 case CCP2_PAD_SOURCE | MEDIA_ENT_T_V4L2_SUBDEV:
1007 /* write to video port/ccdc */
1008 if (flags & MEDIA_LNK_FL_ENABLED)
1009 ccp2->output = CCP2_OUTPUT_CCDC;
1010 else
1011 ccp2->output = CCP2_OUTPUT_NONE;
1012 break;
1013
1014 default:
1015 return -EINVAL;
1016 }
1017
1018 return 0;
1019 }
1020
1021 /* media operations */
1022 static const struct media_entity_operations ccp2_media_ops = {
1023 .link_setup = ccp2_link_setup,
1024 };
1025
1026 /*
1027 * omap3isp_ccp2_unregister_entities - Unregister media entities: subdev
1028 * @ccp2: Pointer to ISP CCP2 device
1029 */
1030 void omap3isp_ccp2_unregister_entities(struct isp_ccp2_device *ccp2)
1031 {
1032 v4l2_device_unregister_subdev(&ccp2->subdev);
1033 omap3isp_video_unregister(&ccp2->video_in);
1034 }
1035
1036 /*
1037 * omap3isp_ccp2_register_entities - Register the subdev media entity
1038 * @ccp2: Pointer to ISP CCP2 device
1039 * @vdev: Pointer to v4l device
1040 * return negative error code or zero on success
1041 */
1042
1043 int omap3isp_ccp2_register_entities(struct isp_ccp2_device *ccp2,
1044 struct v4l2_device *vdev)
1045 {
1046 int ret;
1047
1048 /* Register the subdev and video nodes. */
1049 ret = v4l2_device_register_subdev(vdev, &ccp2->subdev);
1050 if (ret < 0)
1051 goto error;
1052
1053 ret = omap3isp_video_register(&ccp2->video_in, vdev);
1054 if (ret < 0)
1055 goto error;
1056
1057 return 0;
1058
1059 error:
1060 omap3isp_ccp2_unregister_entities(ccp2);
1061 return ret;
1062 }
1063
1064 /* -----------------------------------------------------------------------------
1065 * ISP ccp2 initialisation and cleanup
1066 */
1067
1068 /*
1069 * ccp2_init_entities - Initialize ccp2 subdev and media entity.
1070 * @ccp2: Pointer to ISP CCP2 device
1071 * return negative error code or zero on success
1072 */
1073 static int ccp2_init_entities(struct isp_ccp2_device *ccp2)
1074 {
1075 struct v4l2_subdev *sd = &ccp2->subdev;
1076 struct media_pad *pads = ccp2->pads;
1077 struct media_entity *me = &sd->entity;
1078 int ret;
1079
1080 ccp2->input = CCP2_INPUT_NONE;
1081 ccp2->output = CCP2_OUTPUT_NONE;
1082
1083 v4l2_subdev_init(sd, &ccp2_sd_ops);
1084 sd->internal_ops = &ccp2_sd_internal_ops;
1085 strlcpy(sd->name, "OMAP3 ISP CCP2", sizeof(sd->name));
1086 sd->grp_id = 1 << 16; /* group ID for isp subdevs */
1087 v4l2_set_subdevdata(sd, ccp2);
1088 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1089
1090 pads[CCP2_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
1091 pads[CCP2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
1092
1093 me->ops = &ccp2_media_ops;
1094 ret = media_entity_init(me, CCP2_PADS_NUM, pads, 0);
1095 if (ret < 0)
1096 return ret;
1097
1098 ccp2_init_formats(sd, NULL);
1099
1100 /*
1101 * The CCP2 has weird line alignment requirements, possibly caused by
1102 * DPCM8 decompression. Line length for data read from memory must be a
1103 * multiple of 128 bits (16 bytes) in continuous mode (when no padding
1104 * is present at end of lines). Additionally, if padding is used, the
1105 * padded line length must be a multiple of 32 bytes. To simplify the
1106 * implementation we use a fixed 32 bytes alignment regardless of the
1107 * input format and width. If strict 128 bits alignment support is
1108 * required ispvideo will need to be made aware of this special dual
1109 * alignement requirements.
1110 */
1111 ccp2->video_in.type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
1112 ccp2->video_in.bpl_alignment = 32;
1113 ccp2->video_in.bpl_max = 0xffffffe0;
1114 ccp2->video_in.isp = to_isp_device(ccp2);
1115 ccp2->video_in.ops = &ccp2_video_ops;
1116 ccp2->video_in.capture_mem = PAGE_ALIGN(4096 * 4096) * 3;
1117
1118 ret = omap3isp_video_init(&ccp2->video_in, "CCP2");
1119 if (ret < 0)
1120 goto error_video;
1121
1122 /* Connect the video node to the ccp2 subdev. */
1123 ret = media_entity_create_link(&ccp2->video_in.video.entity, 0,
1124 &ccp2->subdev.entity, CCP2_PAD_SINK, 0);
1125 if (ret < 0)
1126 goto error_link;
1127
1128 return 0;
1129
1130 error_link:
1131 omap3isp_video_cleanup(&ccp2->video_in);
1132 error_video:
1133 media_entity_cleanup(&ccp2->subdev.entity);
1134 return ret;
1135 }
1136
1137 /*
1138 * omap3isp_ccp2_init - CCP2 initialization.
1139 * @isp : Pointer to ISP device
1140 * return negative error code or zero on success
1141 */
1142 int omap3isp_ccp2_init(struct isp_device *isp)
1143 {
1144 struct isp_ccp2_device *ccp2 = &isp->isp_ccp2;
1145 int ret;
1146
1147 init_waitqueue_head(&ccp2->wait);
1148
1149 /*
1150 * On the OMAP34xx the CSI1 receiver is operated in the CSIb IO
1151 * complex, which is powered by vdds_csib power rail. Hence the
1152 * request for the regulator.
1153 *
1154 * On the OMAP36xx, the CCP2 uses the CSI PHY1 or PHY2, shared with
1155 * the CSI2c or CSI2a receivers. The PHY then needs to be explicitly
1156 * configured.
1157 *
1158 * TODO: Don't hardcode the usage of PHY1 (shared with CSI2c).
1159 */
1160 if (isp->revision == ISP_REVISION_2_0) {
1161 ccp2->vdds_csib = regulator_get(isp->dev, "vdds_csib");
1162 if (IS_ERR(ccp2->vdds_csib)) {
1163 dev_dbg(isp->dev,
1164 "Could not get regulator vdds_csib\n");
1165 ccp2->vdds_csib = NULL;
1166 }
1167 } else if (isp->revision == ISP_REVISION_15_0) {
1168 ccp2->phy = &isp->isp_csiphy1;
1169 }
1170
1171 ret = ccp2_init_entities(ccp2);
1172 if (ret < 0) {
1173 regulator_put(ccp2->vdds_csib);
1174 return ret;
1175 }
1176
1177 ccp2_reset(ccp2);
1178 return 0;
1179 }
1180
1181 /*
1182 * omap3isp_ccp2_cleanup - CCP2 un-initialization
1183 * @isp : Pointer to ISP device
1184 */
1185 void omap3isp_ccp2_cleanup(struct isp_device *isp)
1186 {
1187 struct isp_ccp2_device *ccp2 = &isp->isp_ccp2;
1188
1189 omap3isp_video_cleanup(&ccp2->video_in);
1190 media_entity_cleanup(&ccp2->subdev.entity);
1191
1192 regulator_put(ccp2->vdds_csib);
1193 }