2 * Samsung S5P Multi Format Codec v 5.1
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Kamil Debski, <k.debski@samsung.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/videodev2.h>
22 #include <linux/workqueue.h>
23 #include <media/videobuf2-core.h>
25 #include "s5p_mfc_ctrl.h"
26 #include "s5p_mfc_debug.h"
27 #include "s5p_mfc_dec.h"
28 #include "s5p_mfc_enc.h"
29 #include "s5p_mfc_intr.h"
30 #include "s5p_mfc_opr.h"
31 #include "s5p_mfc_pm.h"
32 #include "s5p_mfc_shm.h"
34 #define S5P_MFC_NAME "s5p-mfc"
35 #define S5P_MFC_DEC_NAME "s5p-mfc-dec"
36 #define S5P_MFC_ENC_NAME "s5p-mfc-enc"
39 module_param(debug
, int, S_IRUGO
| S_IWUSR
);
40 MODULE_PARM_DESC(debug
, "Debug level - higher value produces more verbose messages");
42 /* Helper functions for interrupt processing */
43 /* Remove from hw execution round robin */
44 static void clear_work_bit(struct s5p_mfc_ctx
*ctx
)
46 struct s5p_mfc_dev
*dev
= ctx
->dev
;
48 spin_lock(&dev
->condlock
);
49 clear_bit(ctx
->num
, &dev
->ctx_work_bits
);
50 spin_unlock(&dev
->condlock
);
53 /* Wake up context wait_queue */
54 static void wake_up_ctx(struct s5p_mfc_ctx
*ctx
, unsigned int reason
,
58 ctx
->int_type
= reason
;
63 /* Wake up device wait_queue */
64 static void wake_up_dev(struct s5p_mfc_dev
*dev
, unsigned int reason
,
68 dev
->int_type
= reason
;
73 void s5p_mfc_watchdog(unsigned long arg
)
75 struct s5p_mfc_dev
*dev
= (struct s5p_mfc_dev
*)arg
;
77 if (test_bit(0, &dev
->hw_lock
))
78 atomic_inc(&dev
->watchdog_cnt
);
79 if (atomic_read(&dev
->watchdog_cnt
) >= MFC_WATCHDOG_CNT
) {
80 /* This means that hw is busy and no interrupts were
81 * generated by hw for the Nth time of running this
82 * watchdog timer. This usually means a serious hw
83 * error. Now it is time to kill all instances and
85 mfc_err("Time out during waiting for HW\n");
86 queue_work(dev
->watchdog_workqueue
, &dev
->watchdog_work
);
88 dev
->watchdog_timer
.expires
= jiffies
+
89 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL
);
90 add_timer(&dev
->watchdog_timer
);
93 static void s5p_mfc_watchdog_worker(struct work_struct
*work
)
95 struct s5p_mfc_dev
*dev
;
96 struct s5p_mfc_ctx
*ctx
;
101 dev
= container_of(work
, struct s5p_mfc_dev
, watchdog_work
);
103 mfc_err("Driver timeout error handling\n");
104 /* Lock the mutex that protects open and release.
105 * This is necessary as they may load and unload firmware. */
106 mutex_locked
= mutex_trylock(&dev
->mfc_mutex
);
108 mfc_err("Error: some instance may be closing/opening\n");
109 spin_lock_irqsave(&dev
->irqlock
, flags
);
113 for (i
= 0; i
< MFC_NUM_CONTEXTS
; i
++) {
117 ctx
->state
= MFCINST_ERROR
;
118 s5p_mfc_cleanup_queue(&ctx
->dst_queue
, &ctx
->vq_dst
);
119 s5p_mfc_cleanup_queue(&ctx
->src_queue
, &ctx
->vq_src
);
121 wake_up_ctx(ctx
, S5P_FIMV_R2H_CMD_ERR_RET
, 0);
123 clear_bit(0, &dev
->hw_lock
);
124 spin_unlock_irqrestore(&dev
->irqlock
, flags
);
125 /* Double check if there is at least one instance running.
126 * If no instance is in memory than no firmware should be present */
127 if (dev
->num_inst
> 0) {
128 ret
= s5p_mfc_reload_firmware(dev
);
130 mfc_err("Failed to reload FW\n");
134 ret
= s5p_mfc_init_hw(dev
);
136 mfc_err("Failed to reinit FW\n");
140 mutex_unlock(&dev
->mfc_mutex
);
143 static enum s5p_mfc_node_type
s5p_mfc_get_node_type(struct file
*file
)
145 struct video_device
*vdev
= video_devdata(file
);
148 mfc_err("failed to get video_device");
149 return MFCNODE_INVALID
;
151 if (vdev
->index
== 0)
152 return MFCNODE_DECODER
;
153 else if (vdev
->index
== 1)
154 return MFCNODE_ENCODER
;
155 return MFCNODE_INVALID
;
158 static void s5p_mfc_clear_int_flags(struct s5p_mfc_dev
*dev
)
160 mfc_write(dev
, 0, S5P_FIMV_RISC_HOST_INT
);
161 mfc_write(dev
, 0, S5P_FIMV_RISC2HOST_CMD
);
162 mfc_write(dev
, 0xffff, S5P_FIMV_SI_RTN_CHID
);
165 static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx
*ctx
)
167 struct s5p_mfc_buf
*dst_buf
;
169 ctx
->state
= MFCINST_FINISHED
;
171 while (!list_empty(&ctx
->dst_queue
)) {
172 dst_buf
= list_entry(ctx
->dst_queue
.next
,
173 struct s5p_mfc_buf
, list
);
174 mfc_debug(2, "Cleaning up buffer: %d\n",
175 dst_buf
->b
->v4l2_buf
.index
);
176 vb2_set_plane_payload(dst_buf
->b
, 0, 0);
177 vb2_set_plane_payload(dst_buf
->b
, 1, 0);
178 list_del(&dst_buf
->list
);
179 ctx
->dst_queue_cnt
--;
180 dst_buf
->b
->v4l2_buf
.sequence
= (ctx
->sequence
++);
182 if (s5p_mfc_read_shm(ctx
, PIC_TIME_TOP
) ==
183 s5p_mfc_read_shm(ctx
, PIC_TIME_BOT
))
184 dst_buf
->b
->v4l2_buf
.field
= V4L2_FIELD_NONE
;
186 dst_buf
->b
->v4l2_buf
.field
= V4L2_FIELD_INTERLACED
;
188 ctx
->dec_dst_flag
&= ~(1 << dst_buf
->b
->v4l2_buf
.index
);
189 vb2_buffer_done(dst_buf
->b
, VB2_BUF_STATE_DONE
);
193 static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx
*ctx
)
195 struct s5p_mfc_dev
*dev
= ctx
->dev
;
196 struct s5p_mfc_buf
*dst_buf
, *src_buf
;
197 size_t dec_y_addr
= s5p_mfc_get_dec_y_adr();
198 unsigned int frame_type
= s5p_mfc_get_frame_type();
200 /* Copy timestamp / timecode from decoded src to dst and set
202 src_buf
= list_entry(ctx
->src_queue
.next
, struct s5p_mfc_buf
, list
);
203 list_for_each_entry(dst_buf
, &ctx
->dst_queue
, list
) {
204 if (vb2_dma_contig_plane_dma_addr(dst_buf
->b
, 0) == dec_y_addr
) {
205 memcpy(&dst_buf
->b
->v4l2_buf
.timecode
,
206 &src_buf
->b
->v4l2_buf
.timecode
,
207 sizeof(struct v4l2_timecode
));
208 memcpy(&dst_buf
->b
->v4l2_buf
.timestamp
,
209 &src_buf
->b
->v4l2_buf
.timestamp
,
210 sizeof(struct timeval
));
211 switch (frame_type
) {
212 case S5P_FIMV_DECODE_FRAME_I_FRAME
:
213 dst_buf
->b
->v4l2_buf
.flags
|=
214 V4L2_BUF_FLAG_KEYFRAME
;
216 case S5P_FIMV_DECODE_FRAME_P_FRAME
:
217 dst_buf
->b
->v4l2_buf
.flags
|=
218 V4L2_BUF_FLAG_PFRAME
;
220 case S5P_FIMV_DECODE_FRAME_B_FRAME
:
221 dst_buf
->b
->v4l2_buf
.flags
|=
222 V4L2_BUF_FLAG_BFRAME
;
230 static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx
*ctx
, unsigned int err
)
232 struct s5p_mfc_dev
*dev
= ctx
->dev
;
233 struct s5p_mfc_buf
*dst_buf
;
234 size_t dspl_y_addr
= s5p_mfc_get_dspl_y_adr();
235 unsigned int frame_type
= s5p_mfc_get_frame_type();
238 /* If frame is same as previous then skip and do not dequeue */
239 if (frame_type
== S5P_FIMV_DECODE_FRAME_SKIPPED
) {
240 if (!ctx
->after_packed_pb
)
242 ctx
->after_packed_pb
= 0;
246 /* The MFC returns address of the buffer, now we have to
247 * check which videobuf does it correspond to */
248 list_for_each_entry(dst_buf
, &ctx
->dst_queue
, list
) {
249 /* Check if this is the buffer we're looking for */
250 if (vb2_dma_contig_plane_dma_addr(dst_buf
->b
, 0) == dspl_y_addr
) {
251 list_del(&dst_buf
->list
);
252 ctx
->dst_queue_cnt
--;
253 dst_buf
->b
->v4l2_buf
.sequence
= ctx
->sequence
;
254 if (s5p_mfc_read_shm(ctx
, PIC_TIME_TOP
) ==
255 s5p_mfc_read_shm(ctx
, PIC_TIME_BOT
))
256 dst_buf
->b
->v4l2_buf
.field
= V4L2_FIELD_NONE
;
258 dst_buf
->b
->v4l2_buf
.field
=
259 V4L2_FIELD_INTERLACED
;
260 vb2_set_plane_payload(dst_buf
->b
, 0, ctx
->luma_size
);
261 vb2_set_plane_payload(dst_buf
->b
, 1, ctx
->chroma_size
);
262 clear_bit(dst_buf
->b
->v4l2_buf
.index
,
265 vb2_buffer_done(dst_buf
->b
,
266 err
? VB2_BUF_STATE_ERROR
: VB2_BUF_STATE_DONE
);
268 index
= dst_buf
->b
->v4l2_buf
.index
;
274 /* Handle frame decoding interrupt */
275 static void s5p_mfc_handle_frame(struct s5p_mfc_ctx
*ctx
,
276 unsigned int reason
, unsigned int err
)
278 struct s5p_mfc_dev
*dev
= ctx
->dev
;
279 unsigned int dst_frame_status
;
280 struct s5p_mfc_buf
*src_buf
;
282 unsigned int res_change
;
286 dst_frame_status
= s5p_mfc_get_dspl_status()
287 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK
;
288 res_change
= s5p_mfc_get_dspl_status()
289 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK
;
290 mfc_debug(2, "Frame Status: %x\n", dst_frame_status
);
291 if (ctx
->state
== MFCINST_RES_CHANGE_INIT
)
292 ctx
->state
= MFCINST_RES_CHANGE_FLUSH
;
294 ctx
->state
= MFCINST_RES_CHANGE_INIT
;
295 s5p_mfc_clear_int_flags(dev
);
296 wake_up_ctx(ctx
, reason
, err
);
297 if (test_and_clear_bit(0, &dev
->hw_lock
) == 0)
300 s5p_mfc_try_run(dev
);
303 if (ctx
->dpb_flush_flag
)
304 ctx
->dpb_flush_flag
= 0;
306 spin_lock_irqsave(&dev
->irqlock
, flags
);
307 /* All frames remaining in the buffer have been extracted */
308 if (dst_frame_status
== S5P_FIMV_DEC_STATUS_DECODING_EMPTY
) {
309 if (ctx
->state
== MFCINST_RES_CHANGE_FLUSH
) {
310 s5p_mfc_handle_frame_all_extracted(ctx
);
311 ctx
->state
= MFCINST_RES_CHANGE_END
;
312 goto leave_handle_frame
;
314 s5p_mfc_handle_frame_all_extracted(ctx
);
318 if (dst_frame_status
== S5P_FIMV_DEC_STATUS_DECODING_DISPLAY
||
319 dst_frame_status
== S5P_FIMV_DEC_STATUS_DECODING_ONLY
)
320 s5p_mfc_handle_frame_copy_time(ctx
);
322 /* A frame has been decoded and is in the buffer */
323 if (dst_frame_status
== S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
||
324 dst_frame_status
== S5P_FIMV_DEC_STATUS_DECODING_DISPLAY
) {
325 s5p_mfc_handle_frame_new(ctx
, err
);
327 mfc_debug(2, "No frame decode\n");
329 /* Mark source buffer as complete */
330 if (dst_frame_status
!= S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
331 && !list_empty(&ctx
->src_queue
)) {
332 src_buf
= list_entry(ctx
->src_queue
.next
, struct s5p_mfc_buf
,
334 ctx
->consumed_stream
+= s5p_mfc_get_consumed_stream();
335 if (ctx
->codec_mode
!= S5P_FIMV_CODEC_H264_DEC
&&
336 s5p_mfc_get_frame_type() == S5P_FIMV_DECODE_FRAME_P_FRAME
337 && ctx
->consumed_stream
+ STUFF_BYTE
<
338 src_buf
->b
->v4l2_planes
[0].bytesused
) {
339 /* Run MFC again on the same buffer */
340 mfc_debug(2, "Running again the same buffer\n");
341 ctx
->after_packed_pb
= 1;
343 index
= src_buf
->b
->v4l2_buf
.index
;
344 mfc_debug(2, "MFC needs next buffer\n");
345 ctx
->consumed_stream
= 0;
346 list_del(&src_buf
->list
);
347 ctx
->src_queue_cnt
--;
348 if (s5p_mfc_err_dec(err
) > 0)
349 vb2_buffer_done(src_buf
->b
, VB2_BUF_STATE_ERROR
);
351 vb2_buffer_done(src_buf
->b
, VB2_BUF_STATE_DONE
);
355 spin_unlock_irqrestore(&dev
->irqlock
, flags
);
356 if ((ctx
->src_queue_cnt
== 0 && ctx
->state
!= MFCINST_FINISHING
)
357 || ctx
->dst_queue_cnt
< ctx
->dpb_count
)
359 s5p_mfc_clear_int_flags(dev
);
360 wake_up_ctx(ctx
, reason
, err
);
361 if (test_and_clear_bit(0, &dev
->hw_lock
) == 0)
364 s5p_mfc_try_run(dev
);
367 /* Error handling for interrupt */
368 static void s5p_mfc_handle_error(struct s5p_mfc_ctx
*ctx
,
369 unsigned int reason
, unsigned int err
)
371 struct s5p_mfc_dev
*dev
;
374 /* If no context is available then all necessary
375 * processing has been done. */
380 mfc_err("Interrupt Error: %08x\n", err
);
381 s5p_mfc_clear_int_flags(dev
);
382 wake_up_dev(dev
, reason
, err
);
384 /* Error recovery is dependent on the state of context */
385 switch (ctx
->state
) {
387 /* This error had to happen while acquireing instance */
388 case MFCINST_GOT_INST
:
389 /* This error had to happen while parsing the header */
390 case MFCINST_HEAD_PARSED
:
391 /* This error had to happen while setting dst buffers */
392 case MFCINST_RETURN_INST
:
393 /* This error had to happen while releasing instance */
395 wake_up_ctx(ctx
, reason
, err
);
396 if (test_and_clear_bit(0, &dev
->hw_lock
) == 0)
399 ctx
->state
= MFCINST_ERROR
;
401 case MFCINST_FINISHING
:
402 case MFCINST_FINISHED
:
403 case MFCINST_RUNNING
:
404 /* It is higly probable that an error occured
405 * while decoding a frame */
407 ctx
->state
= MFCINST_ERROR
;
408 /* Mark all dst buffers as having an error */
409 spin_lock_irqsave(&dev
->irqlock
, flags
);
410 s5p_mfc_cleanup_queue(&ctx
->dst_queue
, &ctx
->vq_dst
);
411 /* Mark all src buffers as having an error */
412 s5p_mfc_cleanup_queue(&ctx
->src_queue
, &ctx
->vq_src
);
413 spin_unlock_irqrestore(&dev
->irqlock
, flags
);
414 if (test_and_clear_bit(0, &dev
->hw_lock
) == 0)
419 mfc_err("Encountered an error interrupt which had not been handled\n");
425 /* Header parsing interrupt handling */
426 static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx
*ctx
,
427 unsigned int reason
, unsigned int err
)
429 struct s5p_mfc_dev
*dev
;
430 unsigned int guard_width
, guard_height
;
435 if (ctx
->c_ops
->post_seq_start
) {
436 if (ctx
->c_ops
->post_seq_start(ctx
))
437 mfc_err("post_seq_start() failed\n");
439 ctx
->img_width
= s5p_mfc_get_img_width();
440 ctx
->img_height
= s5p_mfc_get_img_height();
442 ctx
->buf_width
= ALIGN(ctx
->img_width
,
443 S5P_FIMV_NV12MT_HALIGN
);
444 ctx
->buf_height
= ALIGN(ctx
->img_height
,
445 S5P_FIMV_NV12MT_VALIGN
);
446 mfc_debug(2, "SEQ Done: Movie dimensions %dx%d, "
447 "buffer dimensions: %dx%d\n", ctx
->img_width
,
448 ctx
->img_height
, ctx
->buf_width
,
450 if (ctx
->codec_mode
== S5P_FIMV_CODEC_H264_DEC
) {
451 ctx
->luma_size
= ALIGN(ctx
->buf_width
*
452 ctx
->buf_height
, S5P_FIMV_DEC_BUF_ALIGN
);
453 ctx
->chroma_size
= ALIGN(ctx
->buf_width
*
454 ALIGN((ctx
->img_height
>> 1),
455 S5P_FIMV_NV12MT_VALIGN
),
456 S5P_FIMV_DEC_BUF_ALIGN
);
457 ctx
->mv_size
= ALIGN(ctx
->buf_width
*
458 ALIGN((ctx
->buf_height
>> 2),
459 S5P_FIMV_NV12MT_VALIGN
),
460 S5P_FIMV_DEC_BUF_ALIGN
);
462 guard_width
= ALIGN(ctx
->img_width
+ 24,
463 S5P_FIMV_NV12MT_HALIGN
);
464 guard_height
= ALIGN(ctx
->img_height
+ 16,
465 S5P_FIMV_NV12MT_VALIGN
);
466 ctx
->luma_size
= ALIGN(guard_width
*
467 guard_height
, S5P_FIMV_DEC_BUF_ALIGN
);
468 guard_width
= ALIGN(ctx
->img_width
+ 16,
469 S5P_FIMV_NV12MT_HALIGN
);
470 guard_height
= ALIGN((ctx
->img_height
>> 1) + 4,
471 S5P_FIMV_NV12MT_VALIGN
);
472 ctx
->chroma_size
= ALIGN(guard_width
*
473 guard_height
, S5P_FIMV_DEC_BUF_ALIGN
);
476 ctx
->dpb_count
= s5p_mfc_get_dpb_count();
477 if (ctx
->img_width
== 0 || ctx
->img_height
== 0)
478 ctx
->state
= MFCINST_ERROR
;
480 ctx
->state
= MFCINST_HEAD_PARSED
;
482 s5p_mfc_clear_int_flags(dev
);
484 if (test_and_clear_bit(0, &dev
->hw_lock
) == 0)
487 s5p_mfc_try_run(dev
);
488 wake_up_ctx(ctx
, reason
, err
);
491 /* Header parsing interrupt handling */
492 static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx
*ctx
,
493 unsigned int reason
, unsigned int err
)
495 struct s5p_mfc_buf
*src_buf
;
496 struct s5p_mfc_dev
*dev
;
502 s5p_mfc_clear_int_flags(dev
);
503 ctx
->int_type
= reason
;
506 spin_lock(&dev
->condlock
);
507 clear_bit(ctx
->num
, &dev
->ctx_work_bits
);
508 spin_unlock(&dev
->condlock
);
510 ctx
->state
= MFCINST_RUNNING
;
511 if (!ctx
->dpb_flush_flag
) {
512 spin_lock_irqsave(&dev
->irqlock
, flags
);
513 if (!list_empty(&ctx
->src_queue
)) {
514 src_buf
= list_entry(ctx
->src_queue
.next
,
515 struct s5p_mfc_buf
, list
);
516 list_del(&src_buf
->list
);
517 ctx
->src_queue_cnt
--;
518 vb2_buffer_done(src_buf
->b
,
521 spin_unlock_irqrestore(&dev
->irqlock
, flags
);
523 ctx
->dpb_flush_flag
= 0;
525 if (test_and_clear_bit(0, &dev
->hw_lock
) == 0)
530 wake_up(&ctx
->queue
);
531 s5p_mfc_try_run(dev
);
533 if (test_and_clear_bit(0, &dev
->hw_lock
) == 0)
538 wake_up(&ctx
->queue
);
542 /* Interrupt processing */
543 static irqreturn_t
s5p_mfc_irq(int irq
, void *priv
)
545 struct s5p_mfc_dev
*dev
= priv
;
546 struct s5p_mfc_ctx
*ctx
;
551 /* Reset the timeout watchdog */
552 atomic_set(&dev
->watchdog_cnt
, 0);
553 ctx
= dev
->ctx
[dev
->curr_ctx
];
554 /* Get the reason of interrupt and the error code */
555 reason
= s5p_mfc_get_int_reason();
556 err
= s5p_mfc_get_int_err();
557 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason
, err
);
559 case S5P_FIMV_R2H_CMD_ERR_RET
:
560 /* An error has occured */
561 if (ctx
->state
== MFCINST_RUNNING
&&
562 s5p_mfc_err_dec(err
) >= S5P_FIMV_ERR_WARNINGS_START
)
563 s5p_mfc_handle_frame(ctx
, reason
, err
);
565 s5p_mfc_handle_error(ctx
, reason
, err
);
566 clear_bit(0, &dev
->enter_suspend
);
569 case S5P_FIMV_R2H_CMD_SLICE_DONE_RET
:
570 case S5P_FIMV_R2H_CMD_FRAME_DONE_RET
:
571 if (ctx
->c_ops
->post_frame_start
) {
572 if (ctx
->c_ops
->post_frame_start(ctx
))
573 mfc_err("post_frame_start() failed\n");
574 s5p_mfc_clear_int_flags(dev
);
575 wake_up_ctx(ctx
, reason
, err
);
576 if (test_and_clear_bit(0, &dev
->hw_lock
) == 0)
579 s5p_mfc_try_run(dev
);
581 s5p_mfc_handle_frame(ctx
, reason
, err
);
585 case S5P_FIMV_R2H_CMD_SEQ_DONE_RET
:
586 s5p_mfc_handle_seq_done(ctx
, reason
, err
);
589 case S5P_FIMV_R2H_CMD_OPEN_INSTANCE_RET
:
590 ctx
->inst_no
= s5p_mfc_get_inst_no();
591 ctx
->state
= MFCINST_GOT_INST
;
593 wake_up(&ctx
->queue
);
596 case S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET
:
598 ctx
->state
= MFCINST_FREE
;
599 wake_up(&ctx
->queue
);
602 case S5P_FIMV_R2H_CMD_SYS_INIT_RET
:
603 case S5P_FIMV_R2H_CMD_FW_STATUS_RET
:
604 case S5P_FIMV_R2H_CMD_SLEEP_RET
:
605 case S5P_FIMV_R2H_CMD_WAKEUP_RET
:
608 s5p_mfc_clear_int_flags(dev
);
609 wake_up_dev(dev
, reason
, err
);
610 clear_bit(0, &dev
->hw_lock
);
611 clear_bit(0, &dev
->enter_suspend
);
614 case S5P_FIMV_R2H_CMD_INIT_BUFFERS_RET
:
615 s5p_mfc_handle_init_buffers(ctx
, reason
, err
);
618 mfc_debug(2, "Unknown int reason\n");
619 s5p_mfc_clear_int_flags(dev
);
624 s5p_mfc_clear_int_flags(dev
);
625 ctx
->int_type
= reason
;
628 if (test_and_clear_bit(0, &dev
->hw_lock
) == 0)
629 mfc_err("Failed to unlock hw\n");
633 s5p_mfc_try_run(dev
);
634 mfc_debug(2, "Exit via irq_cleanup_hw\n");
638 /* Open an MFC node */
639 static int s5p_mfc_open(struct file
*file
)
641 struct s5p_mfc_dev
*dev
= video_drvdata(file
);
642 struct s5p_mfc_ctx
*ctx
= NULL
;
648 dev
->num_inst
++; /* It is guarded by mfc_mutex in vfd */
649 /* Allocate memory for context */
650 ctx
= kzalloc(sizeof *ctx
, GFP_KERNEL
);
652 mfc_err("Not enough memory\n");
656 v4l2_fh_init(&ctx
->fh
, video_devdata(file
));
657 file
->private_data
= &ctx
->fh
;
658 v4l2_fh_add(&ctx
->fh
);
660 INIT_LIST_HEAD(&ctx
->src_queue
);
661 INIT_LIST_HEAD(&ctx
->dst_queue
);
662 ctx
->src_queue_cnt
= 0;
663 ctx
->dst_queue_cnt
= 0;
664 /* Get context number */
666 while (dev
->ctx
[ctx
->num
]) {
668 if (ctx
->num
>= MFC_NUM_CONTEXTS
) {
669 mfc_err("Too many open contexts\n");
674 /* Mark context as idle */
675 spin_lock_irqsave(&dev
->condlock
, flags
);
676 clear_bit(ctx
->num
, &dev
->ctx_work_bits
);
677 spin_unlock_irqrestore(&dev
->condlock
, flags
);
678 dev
->ctx
[ctx
->num
] = ctx
;
679 if (s5p_mfc_get_node_type(file
) == MFCNODE_DECODER
) {
680 ctx
->type
= MFCINST_DECODER
;
681 ctx
->c_ops
= get_dec_codec_ops();
682 /* Setup ctrl handler */
683 ret
= s5p_mfc_dec_ctrls_setup(ctx
);
685 mfc_err("Failed to setup mfc controls\n");
686 goto err_ctrls_setup
;
688 } else if (s5p_mfc_get_node_type(file
) == MFCNODE_ENCODER
) {
689 ctx
->type
= MFCINST_ENCODER
;
690 ctx
->c_ops
= get_enc_codec_ops();
691 /* only for encoder */
692 INIT_LIST_HEAD(&ctx
->ref_queue
);
693 ctx
->ref_queue_cnt
= 0;
694 /* Setup ctrl handler */
695 ret
= s5p_mfc_enc_ctrls_setup(ctx
);
697 mfc_err("Failed to setup mfc controls\n");
698 goto err_ctrls_setup
;
704 ctx
->fh
.ctrl_handler
= &ctx
->ctrl_handler
;
706 /* Load firmware if this is the first instance */
707 if (dev
->num_inst
== 1) {
708 dev
->watchdog_timer
.expires
= jiffies
+
709 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL
);
710 add_timer(&dev
->watchdog_timer
);
711 ret
= s5p_mfc_power_on();
713 mfc_err("power on failed\n");
717 ret
= s5p_mfc_alloc_and_load_firmware(dev
);
721 ret
= s5p_mfc_init_hw(dev
);
726 /* Init videobuf2 queue for CAPTURE */
728 q
->type
= V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE
;
729 q
->drv_priv
= &ctx
->fh
;
730 if (s5p_mfc_get_node_type(file
) == MFCNODE_DECODER
) {
731 q
->io_modes
= VB2_MMAP
;
732 q
->ops
= get_dec_queue_ops();
733 } else if (s5p_mfc_get_node_type(file
) == MFCNODE_ENCODER
) {
734 q
->io_modes
= VB2_MMAP
| VB2_USERPTR
;
735 q
->ops
= get_enc_queue_ops();
740 q
->mem_ops
= (struct vb2_mem_ops
*)&vb2_dma_contig_memops
;
741 ret
= vb2_queue_init(q
);
743 mfc_err("Failed to initialize videobuf2 queue(capture)\n");
746 /* Init videobuf2 queue for OUTPUT */
748 q
->type
= V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE
;
749 q
->io_modes
= VB2_MMAP
;
750 q
->drv_priv
= &ctx
->fh
;
751 if (s5p_mfc_get_node_type(file
) == MFCNODE_DECODER
) {
752 q
->io_modes
= VB2_MMAP
;
753 q
->ops
= get_dec_queue_ops();
754 } else if (s5p_mfc_get_node_type(file
) == MFCNODE_ENCODER
) {
755 q
->io_modes
= VB2_MMAP
| VB2_USERPTR
;
756 q
->ops
= get_enc_queue_ops();
761 q
->mem_ops
= (struct vb2_mem_ops
*)&vb2_dma_contig_memops
;
762 ret
= vb2_queue_init(q
);
764 mfc_err("Failed to initialize videobuf2 queue(output)\n");
767 init_waitqueue_head(&ctx
->queue
);
770 /* Deinit when failure occured */
773 s5p_mfc_release_firmware(dev
);
775 dev
->ctx
[ctx
->num
] = 0;
776 del_timer_sync(&dev
->watchdog_timer
);
779 if (dev
->num_inst
== 1) {
780 if (s5p_mfc_power_off() < 0)
781 mfc_err("power off failed\n");
782 s5p_mfc_release_firmware(dev
);
785 s5p_mfc_dec_ctrls_delete(ctx
);
788 v4l2_fh_del(&ctx
->fh
);
789 v4l2_fh_exit(&ctx
->fh
);
797 /* Release MFC context */
798 static int s5p_mfc_release(struct file
*file
)
800 struct s5p_mfc_ctx
*ctx
= fh_to_ctx(file
->private_data
);
801 struct s5p_mfc_dev
*dev
= ctx
->dev
;
806 vb2_queue_release(&ctx
->vq_src
);
807 vb2_queue_release(&ctx
->vq_dst
);
808 /* Mark context as idle */
809 spin_lock_irqsave(&dev
->condlock
, flags
);
810 clear_bit(ctx
->num
, &dev
->ctx_work_bits
);
811 spin_unlock_irqrestore(&dev
->condlock
, flags
);
812 /* If instance was initialised then
813 * return instance and free reosurces */
814 if (ctx
->inst_no
!= MFC_NO_INSTANCE_SET
) {
815 mfc_debug(2, "Has to free instance\n");
816 ctx
->state
= MFCINST_RETURN_INST
;
817 spin_lock_irqsave(&dev
->condlock
, flags
);
818 set_bit(ctx
->num
, &dev
->ctx_work_bits
);
819 spin_unlock_irqrestore(&dev
->condlock
, flags
);
820 s5p_mfc_clean_ctx_int_flags(ctx
);
821 s5p_mfc_try_run(dev
);
822 /* Wait until instance is returned or timeout occured */
823 if (s5p_mfc_wait_for_done_ctx
824 (ctx
, S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET
, 0)) {
826 mfc_err("Err returning instance\n");
828 mfc_debug(2, "After free instance\n");
830 s5p_mfc_release_codec_buffers(ctx
);
831 s5p_mfc_release_instance_buffer(ctx
);
832 if (ctx
->type
== MFCINST_DECODER
)
833 s5p_mfc_release_dec_desc_buffer(ctx
);
835 ctx
->inst_no
= MFC_NO_INSTANCE_SET
;
837 /* hardware locking scheme */
838 if (dev
->curr_ctx
== ctx
->num
)
839 clear_bit(0, &dev
->hw_lock
);
841 if (dev
->num_inst
== 0) {
842 mfc_debug(2, "Last instance - release firmware\n");
843 /* reset <-> F/W release */
845 s5p_mfc_release_firmware(dev
);
846 del_timer_sync(&dev
->watchdog_timer
);
847 if (s5p_mfc_power_off() < 0)
848 mfc_err("Power off failed\n");
850 mfc_debug(2, "Shutting down clock\n");
852 dev
->ctx
[ctx
->num
] = 0;
853 s5p_mfc_dec_ctrls_delete(ctx
);
854 v4l2_fh_del(&ctx
->fh
);
855 v4l2_fh_exit(&ctx
->fh
);
862 static unsigned int s5p_mfc_poll(struct file
*file
,
863 struct poll_table_struct
*wait
)
865 struct s5p_mfc_ctx
*ctx
= fh_to_ctx(file
->private_data
);
866 struct s5p_mfc_dev
*dev
= ctx
->dev
;
867 struct vb2_queue
*src_q
, *dst_q
;
868 struct vb2_buffer
*src_vb
= NULL
, *dst_vb
= NULL
;
872 src_q
= &ctx
->vq_src
;
873 dst_q
= &ctx
->vq_dst
;
875 * There has to be at least one buffer queued on each queued_list, which
876 * means either in driver already or waiting for driver to claim it
877 * and start processing.
879 if ((!src_q
->streaming
|| list_empty(&src_q
->queued_list
))
880 && (!dst_q
->streaming
|| list_empty(&dst_q
->queued_list
))) {
884 mutex_unlock(&dev
->mfc_mutex
);
885 poll_wait(file
, &src_q
->done_wq
, wait
);
886 poll_wait(file
, &dst_q
->done_wq
, wait
);
887 mutex_lock(&dev
->mfc_mutex
);
888 spin_lock_irqsave(&src_q
->done_lock
, flags
);
889 if (!list_empty(&src_q
->done_list
))
890 src_vb
= list_first_entry(&src_q
->done_list
, struct vb2_buffer
,
892 if (src_vb
&& (src_vb
->state
== VB2_BUF_STATE_DONE
893 || src_vb
->state
== VB2_BUF_STATE_ERROR
))
894 rc
|= POLLOUT
| POLLWRNORM
;
895 spin_unlock_irqrestore(&src_q
->done_lock
, flags
);
896 spin_lock_irqsave(&dst_q
->done_lock
, flags
);
897 if (!list_empty(&dst_q
->done_list
))
898 dst_vb
= list_first_entry(&dst_q
->done_list
, struct vb2_buffer
,
900 if (dst_vb
&& (dst_vb
->state
== VB2_BUF_STATE_DONE
901 || dst_vb
->state
== VB2_BUF_STATE_ERROR
))
902 rc
|= POLLIN
| POLLRDNORM
;
903 spin_unlock_irqrestore(&dst_q
->done_lock
, flags
);
909 static int s5p_mfc_mmap(struct file
*file
, struct vm_area_struct
*vma
)
911 struct s5p_mfc_ctx
*ctx
= fh_to_ctx(file
->private_data
);
912 unsigned long offset
= vma
->vm_pgoff
<< PAGE_SHIFT
;
914 if (offset
< DST_QUEUE_OFF_BASE
) {
915 mfc_debug(2, "mmaping source\n");
916 ret
= vb2_mmap(&ctx
->vq_src
, vma
);
917 } else { /* capture */
918 mfc_debug(2, "mmaping destination\n");
919 vma
->vm_pgoff
-= (DST_QUEUE_OFF_BASE
>> PAGE_SHIFT
);
920 ret
= vb2_mmap(&ctx
->vq_dst
, vma
);
926 static const struct v4l2_file_operations s5p_mfc_fops
= {
927 .owner
= THIS_MODULE
,
928 .open
= s5p_mfc_open
,
929 .release
= s5p_mfc_release
,
930 .poll
= s5p_mfc_poll
,
931 .unlocked_ioctl
= video_ioctl2
,
932 .mmap
= s5p_mfc_mmap
,
935 static int match_child(struct device
*dev
, void *data
)
939 return !strcmp(dev_name(dev
), (char *)data
);
942 /* MFC probe function */
943 static int s5p_mfc_probe(struct platform_device
*pdev
)
945 struct s5p_mfc_dev
*dev
;
946 struct video_device
*vfd
;
947 struct resource
*res
;
950 pr_debug("%s++\n", __func__
);
951 dev
= kzalloc(sizeof *dev
, GFP_KERNEL
);
953 dev_err(&pdev
->dev
, "Not enough memory for MFC device\n");
957 spin_lock_init(&dev
->irqlock
);
958 spin_lock_init(&dev
->condlock
);
959 dev
->plat_dev
= pdev
;
960 if (!dev
->plat_dev
) {
961 dev_err(&pdev
->dev
, "No platform data specified\n");
966 ret
= s5p_mfc_init_pm(dev
);
968 dev_err(&pdev
->dev
, "failed to get mfc clock source\n");
972 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
974 dev_err(&pdev
->dev
, "failed to get memory region resource\n");
979 dev
->mfc_mem
= request_mem_region(res
->start
, resource_size(res
),
981 if (dev
->mfc_mem
== NULL
) {
982 dev_err(&pdev
->dev
, "failed to get memory region\n");
986 dev
->regs_base
= ioremap(dev
->mfc_mem
->start
, resource_size(dev
->mfc_mem
));
987 if (dev
->regs_base
== NULL
) {
988 dev_err(&pdev
->dev
, "failed to ioremap address region\n");
993 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
995 dev_err(&pdev
->dev
, "failed to get irq resource\n");
999 dev
->irq
= res
->start
;
1000 ret
= request_irq(dev
->irq
, s5p_mfc_irq
, IRQF_DISABLED
, pdev
->name
,
1003 dev_err(&pdev
->dev
, "Failed to install irq (%d)\n", ret
);
1007 dev
->mem_dev_l
= device_find_child(&dev
->plat_dev
->dev
, "s5p-mfc-l",
1009 if (!dev
->mem_dev_l
) {
1010 mfc_err("Mem child (L) device get failed\n");
1012 goto err_find_child
;
1014 dev
->mem_dev_r
= device_find_child(&dev
->plat_dev
->dev
, "s5p-mfc-r",
1016 if (!dev
->mem_dev_r
) {
1017 mfc_err("Mem child (R) device get failed\n");
1019 goto err_find_child
;
1022 dev
->alloc_ctx
[0] = vb2_dma_contig_init_ctx(dev
->mem_dev_l
);
1023 if (IS_ERR_OR_NULL(dev
->alloc_ctx
[0])) {
1024 ret
= PTR_ERR(dev
->alloc_ctx
[0]);
1025 goto err_mem_init_ctx_0
;
1027 dev
->alloc_ctx
[1] = vb2_dma_contig_init_ctx(dev
->mem_dev_r
);
1028 if (IS_ERR_OR_NULL(dev
->alloc_ctx
[1])) {
1029 ret
= PTR_ERR(dev
->alloc_ctx
[1]);
1030 goto err_mem_init_ctx_1
;
1033 mutex_init(&dev
->mfc_mutex
);
1035 ret
= v4l2_device_register(&pdev
->dev
, &dev
->v4l2_dev
);
1037 goto err_v4l2_dev_reg
;
1038 init_waitqueue_head(&dev
->queue
);
1041 vfd
= video_device_alloc();
1043 v4l2_err(&dev
->v4l2_dev
, "Failed to allocate video device\n");
1047 vfd
->fops
= &s5p_mfc_fops
,
1048 vfd
->ioctl_ops
= get_dec_v4l2_ioctl_ops();
1049 vfd
->release
= video_device_release
,
1050 vfd
->lock
= &dev
->mfc_mutex
;
1051 vfd
->v4l2_dev
= &dev
->v4l2_dev
;
1052 snprintf(vfd
->name
, sizeof(vfd
->name
), "%s", S5P_MFC_DEC_NAME
);
1054 ret
= video_register_device(vfd
, VFL_TYPE_GRABBER
, 0);
1056 v4l2_err(&dev
->v4l2_dev
, "Failed to register video device\n");
1057 video_device_release(vfd
);
1060 v4l2_info(&dev
->v4l2_dev
,
1061 "decoder registered as /dev/video%d\n", vfd
->num
);
1062 video_set_drvdata(vfd
, dev
);
1065 vfd
= video_device_alloc();
1067 v4l2_err(&dev
->v4l2_dev
, "Failed to allocate video device\n");
1071 vfd
->fops
= &s5p_mfc_fops
,
1072 vfd
->ioctl_ops
= get_enc_v4l2_ioctl_ops();
1073 vfd
->release
= video_device_release
,
1074 vfd
->lock
= &dev
->mfc_mutex
;
1075 vfd
->v4l2_dev
= &dev
->v4l2_dev
;
1076 snprintf(vfd
->name
, sizeof(vfd
->name
), "%s", S5P_MFC_ENC_NAME
);
1078 ret
= video_register_device(vfd
, VFL_TYPE_GRABBER
, 0);
1080 v4l2_err(&dev
->v4l2_dev
, "Failed to register video device\n");
1081 video_device_release(vfd
);
1084 v4l2_info(&dev
->v4l2_dev
,
1085 "encoder registered as /dev/video%d\n", vfd
->num
);
1086 video_set_drvdata(vfd
, dev
);
1087 platform_set_drvdata(pdev
, dev
);
1090 dev
->watchdog_workqueue
= create_singlethread_workqueue(S5P_MFC_NAME
);
1091 INIT_WORK(&dev
->watchdog_work
, s5p_mfc_watchdog_worker
);
1092 atomic_set(&dev
->watchdog_cnt
, 0);
1093 init_timer(&dev
->watchdog_timer
);
1094 dev
->watchdog_timer
.data
= (unsigned long)dev
;
1095 dev
->watchdog_timer
.function
= s5p_mfc_watchdog
;
1097 pr_debug("%s--\n", __func__
);
1100 /* Deinit MFC if probe had failed */
1102 video_device_release(dev
->vfd_enc
);
1104 video_unregister_device(dev
->vfd_dec
);
1106 video_device_release(dev
->vfd_dec
);
1108 v4l2_device_unregister(&dev
->v4l2_dev
);
1110 vb2_dma_contig_cleanup_ctx(dev
->alloc_ctx
[1]);
1112 vb2_dma_contig_cleanup_ctx(dev
->alloc_ctx
[0]);
1115 free_irq(dev
->irq
, dev
);
1118 iounmap(dev
->regs_base
);
1119 dev
->regs_base
= NULL
;
1121 release_resource(dev
->mfc_mem
);
1122 kfree(dev
->mfc_mem
);
1125 s5p_mfc_final_pm(dev
);
1129 pr_debug("%s-- with error\n", __func__
);
1134 /* Remove the driver */
1135 static int __devexit
s5p_mfc_remove(struct platform_device
*pdev
)
1137 struct s5p_mfc_dev
*dev
= platform_get_drvdata(pdev
);
1139 v4l2_info(&dev
->v4l2_dev
, "Removing %s\n", pdev
->name
);
1141 del_timer_sync(&dev
->watchdog_timer
);
1142 flush_workqueue(dev
->watchdog_workqueue
);
1143 destroy_workqueue(dev
->watchdog_workqueue
);
1145 video_unregister_device(dev
->vfd_enc
);
1146 video_unregister_device(dev
->vfd_dec
);
1147 v4l2_device_unregister(&dev
->v4l2_dev
);
1148 vb2_dma_contig_cleanup_ctx(dev
->alloc_ctx
[0]);
1149 vb2_dma_contig_cleanup_ctx(dev
->alloc_ctx
[1]);
1151 free_irq(dev
->irq
, dev
);
1152 iounmap(dev
->regs_base
);
1154 release_resource(dev
->mfc_mem
);
1155 kfree(dev
->mfc_mem
);
1156 dev
->mfc_mem
= NULL
;
1158 s5p_mfc_final_pm(dev
);
1163 #ifdef CONFIG_PM_SLEEP
1165 static int s5p_mfc_suspend(struct device
*dev
)
1167 struct platform_device
*pdev
= to_platform_device(dev
);
1168 struct s5p_mfc_dev
*m_dev
= platform_get_drvdata(pdev
);
1171 if (m_dev
->num_inst
== 0)
1173 return s5p_mfc_sleep(m_dev
);
1174 if (test_and_set_bit(0, &m_dev
->enter_suspend
) != 0) {
1175 mfc_err("Error: going to suspend for a second time\n");
1179 /* Check if we're processing then wait if it necessary. */
1180 while (test_and_set_bit(0, &m_dev
->hw_lock
) != 0) {
1181 /* Try and lock the HW */
1182 /* Wait on the interrupt waitqueue */
1183 ret
= wait_event_interruptible_timeout(m_dev
->queue
,
1184 m_dev
->int_cond
|| m_dev
->ctx
[m_dev
->curr_ctx
]->int_cond
,
1185 msecs_to_jiffies(MFC_INT_TIMEOUT
));
1188 mfc_err("Waiting for hardware to finish timed out\n");
1195 static int s5p_mfc_resume(struct device
*dev
)
1197 struct platform_device
*pdev
= to_platform_device(dev
);
1198 struct s5p_mfc_dev
*m_dev
= platform_get_drvdata(pdev
);
1200 if (m_dev
->num_inst
== 0)
1202 return s5p_mfc_wakeup(m_dev
);
1206 #ifdef CONFIG_PM_RUNTIME
1207 static int s5p_mfc_runtime_suspend(struct device
*dev
)
1209 struct platform_device
*pdev
= to_platform_device(dev
);
1210 struct s5p_mfc_dev
*m_dev
= platform_get_drvdata(pdev
);
1212 atomic_set(&m_dev
->pm
.power
, 0);
1216 static int s5p_mfc_runtime_resume(struct device
*dev
)
1218 struct platform_device
*pdev
= to_platform_device(dev
);
1219 struct s5p_mfc_dev
*m_dev
= platform_get_drvdata(pdev
);
1222 if (!m_dev
->alloc_ctx
)
1224 pre_power
= atomic_read(&m_dev
->pm
.power
);
1225 atomic_set(&m_dev
->pm
.power
, 1);
1230 /* Power management */
1231 static const struct dev_pm_ops s5p_mfc_pm_ops
= {
1232 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend
, s5p_mfc_resume
)
1233 SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend
, s5p_mfc_runtime_resume
,
1237 static struct platform_driver s5p_mfc_driver
= {
1238 .probe
= s5p_mfc_probe
,
1239 .remove
= __devexit_p(s5p_mfc_remove
),
1241 .name
= S5P_MFC_NAME
,
1242 .owner
= THIS_MODULE
,
1243 .pm
= &s5p_mfc_pm_ops
1247 module_platform_driver(s5p_mfc_driver
);
1249 MODULE_LICENSE("GPL");
1250 MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1251 MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");