| blob | 33247d13e4c0c08d93709d73e4664b20c6a2ac26 |
1 /* linux/arch/arm/mach-exynos4/include/mach/regs-hdmi.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * HDMI register header file for Samsung TVOUT driver
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
13 #ifndef SAMSUNG_REGS_HDMI_H
14 #define SAMSUNG_REGS_HDMI_H
16 /*
17 * Register part
18 */
20 #define HDMI_CTRL_BASE(x) ((x) + 0x00000000)
21 #define HDMI_CORE_BASE(x) ((x) + 0x00010000)
22 #define HDMI_TG_BASE(x) ((x) + 0x00050000)
24 /* Control registers */
25 #define HDMI_INTC_CON HDMI_CTRL_BASE(0x0000)
26 #define HDMI_INTC_FLAG HDMI_CTRL_BASE(0x0004)
27 #define HDMI_HPD_STATUS HDMI_CTRL_BASE(0x000C)
28 #define HDMI_PHY_RSTOUT HDMI_CTRL_BASE(0x0014)
29 #define HDMI_PHY_VPLL HDMI_CTRL_BASE(0x0018)
30 #define HDMI_PHY_CMU HDMI_CTRL_BASE(0x001C)
31 #define HDMI_CORE_RSTOUT HDMI_CTRL_BASE(0x0020)
33 /* Core registers */
34 #define HDMI_CON_0 HDMI_CORE_BASE(0x0000)
35 #define HDMI_CON_1 HDMI_CORE_BASE(0x0004)
36 #define HDMI_CON_2 HDMI_CORE_BASE(0x0008)
37 #define HDMI_SYS_STATUS HDMI_CORE_BASE(0x0010)
38 #define HDMI_PHY_STATUS HDMI_CORE_BASE(0x0014)
39 #define HDMI_STATUS_EN HDMI_CORE_BASE(0x0020)
40 #define HDMI_HPD HDMI_CORE_BASE(0x0030)
41 #define HDMI_MODE_SEL HDMI_CORE_BASE(0x0040)
42 #define HDMI_BLUE_SCREEN_0 HDMI_CORE_BASE(0x0050)
43 #define HDMI_BLUE_SCREEN_1 HDMI_CORE_BASE(0x0054)
44 #define HDMI_BLUE_SCREEN_2 HDMI_CORE_BASE(0x0058)
45 #define HDMI_H_BLANK_0 HDMI_CORE_BASE(0x00A0)
46 #define HDMI_H_BLANK_1 HDMI_CORE_BASE(0x00A4)
47 #define HDMI_V_BLANK_0 HDMI_CORE_BASE(0x00B0)
48 #define HDMI_V_BLANK_1 HDMI_CORE_BASE(0x00B4)
49 #define HDMI_V_BLANK_2 HDMI_CORE_BASE(0x00B8)
50 #define HDMI_H_V_LINE_0 HDMI_CORE_BASE(0x00C0)
51 #define HDMI_H_V_LINE_1 HDMI_CORE_BASE(0x00C4)
52 #define HDMI_H_V_LINE_2 HDMI_CORE_BASE(0x00C8)
53 #define HDMI_VSYNC_POL HDMI_CORE_BASE(0x00E4)
54 #define HDMI_INT_PRO_MODE HDMI_CORE_BASE(0x00E8)
55 #define HDMI_V_BLANK_F_0 HDMI_CORE_BASE(0x0110)
56 #define HDMI_V_BLANK_F_1 HDMI_CORE_BASE(0x0114)
57 #define HDMI_V_BLANK_F_2 HDMI_CORE_BASE(0x0118)
58 #define HDMI_H_SYNC_GEN_0 HDMI_CORE_BASE(0x0120)
59 #define HDMI_H_SYNC_GEN_1 HDMI_CORE_BASE(0x0124)
60 #define HDMI_H_SYNC_GEN_2 HDMI_CORE_BASE(0x0128)
61 #define HDMI_V_SYNC_GEN_1_0 HDMI_CORE_BASE(0x0130)
62 #define HDMI_V_SYNC_GEN_1_1 HDMI_CORE_BASE(0x0134)
63 #define HDMI_V_SYNC_GEN_1_2 HDMI_CORE_BASE(0x0138)
64 #define HDMI_V_SYNC_GEN_2_0 HDMI_CORE_BASE(0x0140)
65 #define HDMI_V_SYNC_GEN_2_1 HDMI_CORE_BASE(0x0144)
66 #define HDMI_V_SYNC_GEN_2_2 HDMI_CORE_BASE(0x0148)
67 #define HDMI_V_SYNC_GEN_3_0 HDMI_CORE_BASE(0x0150)
68 #define HDMI_V_SYNC_GEN_3_1 HDMI_CORE_BASE(0x0154)
69 #define HDMI_V_SYNC_GEN_3_2 HDMI_CORE_BASE(0x0158)
70 #define HDMI_AVI_CON HDMI_CORE_BASE(0x0300)
71 #define HDMI_AVI_BYTE(n) HDMI_CORE_BASE(0x0320 + 4 * (n))
72 #define HDMI_DC_CONTROL HDMI_CORE_BASE(0x05C0)
73 #define HDMI_VIDEO_PATTERN_GEN HDMI_CORE_BASE(0x05C4)
74 #define HDMI_HPD_GEN HDMI_CORE_BASE(0x05C8)
76 /* Timing generator registers */
77 #define HDMI_TG_CMD HDMI_TG_BASE(0x0000)
78 #define HDMI_TG_H_FSZ_L HDMI_TG_BASE(0x0018)
79 #define HDMI_TG_H_FSZ_H HDMI_TG_BASE(0x001C)
80 #define HDMI_TG_HACT_ST_L HDMI_TG_BASE(0x0020)
81 #define HDMI_TG_HACT_ST_H HDMI_TG_BASE(0x0024)
82 #define HDMI_TG_HACT_SZ_L HDMI_TG_BASE(0x0028)
83 #define HDMI_TG_HACT_SZ_H HDMI_TG_BASE(0x002C)
84 #define HDMI_TG_V_FSZ_L HDMI_TG_BASE(0x0030)
85 #define HDMI_TG_V_FSZ_H HDMI_TG_BASE(0x0034)
86 #define HDMI_TG_VSYNC_L HDMI_TG_BASE(0x0038)
87 #define HDMI_TG_VSYNC_H HDMI_TG_BASE(0x003C)
88 #define HDMI_TG_VSYNC2_L HDMI_TG_BASE(0x0040)
89 #define HDMI_TG_VSYNC2_H HDMI_TG_BASE(0x0044)
90 #define HDMI_TG_VACT_ST_L HDMI_TG_BASE(0x0048)
91 #define HDMI_TG_VACT_ST_H HDMI_TG_BASE(0x004C)
92 #define HDMI_TG_VACT_SZ_L HDMI_TG_BASE(0x0050)
93 #define HDMI_TG_VACT_SZ_H HDMI_TG_BASE(0x0054)
94 #define HDMI_TG_FIELD_CHG_L HDMI_TG_BASE(0x0058)
95 #define HDMI_TG_FIELD_CHG_H HDMI_TG_BASE(0x005C)
96 #define HDMI_TG_VACT_ST2_L HDMI_TG_BASE(0x0060)
97 #define HDMI_TG_VACT_ST2_H HDMI_TG_BASE(0x0064)
98 #define HDMI_TG_VSYNC_TOP_HDMI_L HDMI_TG_BASE(0x0078)
99 #define HDMI_TG_VSYNC_TOP_HDMI_H HDMI_TG_BASE(0x007C)
100 #define HDMI_TG_VSYNC_BOT_HDMI_L HDMI_TG_BASE(0x0080)
101 #define HDMI_TG_VSYNC_BOT_HDMI_H HDMI_TG_BASE(0x0084)
102 #define HDMI_TG_FIELD_TOP_HDMI_L HDMI_TG_BASE(0x0088)
103 #define HDMI_TG_FIELD_TOP_HDMI_H HDMI_TG_BASE(0x008C)
104 #define HDMI_TG_FIELD_BOT_HDMI_L HDMI_TG_BASE(0x0090)
105 #define HDMI_TG_FIELD_BOT_HDMI_H HDMI_TG_BASE(0x0094)
107 /*
108 * Bit definition part
109 */
111 /* HDMI_INTC_CON */
112 #define HDMI_INTC_EN_GLOBAL (1 << 6)
113 #define HDMI_INTC_EN_HPD_PLUG (1 << 3)
114 #define HDMI_INTC_EN_HPD_UNPLUG (1 << 2)
116 /* HDMI_INTC_FLAG */
117 #define HDMI_INTC_FLAG_HPD_PLUG (1 << 3)
118 #define HDMI_INTC_FLAG_HPD_UNPLUG (1 << 2)
120 /* HDMI_PHY_RSTOUT */
121 #define HDMI_PHY_SW_RSTOUT (1 << 0)
123 /* HDMI_CORE_RSTOUT */
124 #define HDMI_CORE_SW_RSTOUT (1 << 0)
126 /* HDMI_CON_0 */
127 #define HDMI_BLUE_SCR_EN (1 << 5)
128 #define HDMI_EN (1 << 0)
130 /* HDMI_CON_2 */
131 #define HDMI_DVI_PERAMBLE_EN (1 << 5)
132 #define HDMI_DVI_BAND_EN (1 << 1)
134 /* HDMI_PHY_STATUS */
135 #define HDMI_PHY_STATUS_READY (1 << 0)
137 /* HDMI_MODE_SEL */
138 #define HDMI_MODE_HDMI_EN (1 << 1)
139 #define HDMI_MODE_DVI_EN (1 << 0)
140 #define HDMI_MODE_MASK (3 << 0)
142 /* HDMI_TG_CMD */
143 #define HDMI_TG_EN (1 << 0)