drivers/mmc/host/mmci.h

   1 /*
   2  *  linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver
   3  *
   4  *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #define MMCIPOWER               0x000
  11 #define MCI_PWR_OFF             0x00
  12 #define MCI_PWR_UP              0x02
  13 #define MCI_PWR_ON              0x03
  14 #define MCI_OD                  (1 << 6)
  15 #define MCI_ROD                 (1 << 7)
  16 /*
  17  * The ST Micro version does not have ROD and reuse the voltage registers
  18  * for direction settings
  19  */
  20 #define MCI_ST_DATA2DIREN       (1 << 2)
  21 #define MCI_ST_CMDDIREN         (1 << 3)
  22 #define MCI_ST_DATA0DIREN       (1 << 4)
  23 #define MCI_ST_DATA31DIREN      (1 << 5)
  24 #define MCI_ST_FBCLKEN          (1 << 7)
  25 #define MCI_ST_DATA74DIREN      (1 << 8)
  26
  27 #define MMCICLOCK               0x004
  28 #define MCI_CLK_ENABLE          (1 << 8)
  29 #define MCI_CLK_PWRSAVE         (1 << 9)
  30 #define MCI_CLK_BYPASS          (1 << 10)
  31 #define MCI_4BIT_BUS            (1 << 11)
  32 /*
  33  * 8bit wide buses, hardware flow contronl, negative edges and clock inversion
  34  * supported in ST Micro U300 and Ux500 versions
  35  */
  36 #define MCI_ST_8BIT_BUS         (1 << 12)
  37 #define MCI_ST_U300_HWFCEN      (1 << 13)
  38 #define MCI_ST_UX500_NEG_EDGE   (1 << 13)
  39 #define MCI_ST_UX500_HWFCEN     (1 << 14)
  40 #define MCI_ST_UX500_CLK_INV    (1 << 15)
  41
  42 #define MMCIARGUMENT            0x008
  43 #define MMCICOMMAND             0x00c
  44 #define MCI_CPSM_RESPONSE       (1 << 6)
  45 #define MCI_CPSM_LONGRSP        (1 << 7)
  46 #define MCI_CPSM_INTERRUPT      (1 << 8)
  47 #define MCI_CPSM_PENDING        (1 << 9)
  48 #define MCI_CPSM_ENABLE         (1 << 10)
  49 #define MCI_SDIO_SUSP           (1 << 11)
  50 #define MCI_ENCMD_COMPL         (1 << 12)
  51 #define MCI_NIEN                (1 << 13)
  52 #define MCI_CE_ATACMD           (1 << 14)
  53
  54 #define MMCIRESPCMD             0x010
  55 #define MMCIRESPONSE0           0x014
  56 #define MMCIRESPONSE1           0x018
  57 #define MMCIRESPONSE2           0x01c
  58 #define MMCIRESPONSE3           0x020
  59 #define MMCIDATATIMER           0x024
  60 #define MMCIDATALENGTH          0x028
  61 #define MMCIDATACTRL            0x02c
  62 #define MCI_DPSM_ENABLE         (1 << 0)
  63 #define MCI_DPSM_DIRECTION      (1 << 1)
  64 #define MCI_DPSM_MODE           (1 << 2)
  65 #define MCI_DPSM_DMAENABLE      (1 << 3)
  66 #define MCI_DPSM_BLOCKSIZE      (1 << 4)
  67 /* Control register extensions in the ST Micro U300 and Ux500 versions */
  68 #define MCI_ST_DPSM_RWSTART     (1 << 8)
  69 #define MCI_ST_DPSM_RWSTOP      (1 << 9)
  70 #define MCI_ST_DPSM_RWMOD       (1 << 10)
  71 #define MCI_ST_DPSM_SDIOEN      (1 << 11)
  72 /* Control register extensions in the ST Micro Ux500 versions */
  73 #define MCI_ST_DPSM_DMAREQCTL   (1 << 12)
  74 #define MCI_ST_DPSM_DBOOTMODEEN (1 << 13)
  75 #define MCI_ST_DPSM_BUSYMODE    (1 << 14)
  76 #define MCI_ST_DPSM_DDRMODE     (1 << 15)
  77
  78 #define MMCIDATACNT             0x030
  79 #define MMCISTATUS              0x034
  80 #define MCI_CMDCRCFAIL          (1 << 0)
  81 #define MCI_DATACRCFAIL         (1 << 1)
  82 #define MCI_CMDTIMEOUT          (1 << 2)
  83 #define MCI_DATATIMEOUT         (1 << 3)
  84 #define MCI_TXUNDERRUN          (1 << 4)
  85 #define MCI_RXOVERRUN           (1 << 5)
  86 #define MCI_CMDRESPEND          (1 << 6)
  87 #define MCI_CMDSENT             (1 << 7)
  88 #define MCI_DATAEND             (1 << 8)
  89 #define MCI_STARTBITERR         (1 << 9)
  90 #define MCI_DATABLOCKEND        (1 << 10)
  91 #define MCI_CMDACTIVE           (1 << 11)
  92 #define MCI_TXACTIVE            (1 << 12)
  93 #define MCI_RXACTIVE            (1 << 13)
  94 #define MCI_TXFIFOHALFEMPTY     (1 << 14)
  95 #define MCI_RXFIFOHALFFULL      (1 << 15)
  96 #define MCI_TXFIFOFULL          (1 << 16)
  97 #define MCI_RXFIFOFULL          (1 << 17)
  98 #define MCI_TXFIFOEMPTY         (1 << 18)
  99 #define MCI_RXFIFOEMPTY         (1 << 19)
 100 #define MCI_TXDATAAVLBL         (1 << 20)
 101 #define MCI_RXDATAAVLBL         (1 << 21)
 102 /* Extended status bits for the ST Micro variants */
 103 #define MCI_ST_SDIOIT           (1 << 22)
 104 #define MCI_ST_CEATAEND         (1 << 23)
 105
 106 #define MMCICLEAR               0x038
 107 #define MCI_CMDCRCFAILCLR       (1 << 0)
 108 #define MCI_DATACRCFAILCLR      (1 << 1)
 109 #define MCI_CMDTIMEOUTCLR       (1 << 2)
 110 #define MCI_DATATIMEOUTCLR      (1 << 3)
 111 #define MCI_TXUNDERRUNCLR       (1 << 4)
 112 #define MCI_RXOVERRUNCLR        (1 << 5)
 113 #define MCI_CMDRESPENDCLR       (1 << 6)
 114 #define MCI_CMDSENTCLR          (1 << 7)
 115 #define MCI_DATAENDCLR          (1 << 8)
 116 #define MCI_STARTBITERRCLR      (1 << 9)
 117 #define MCI_DATABLOCKENDCLR     (1 << 10)
 118 /* Extended status bits for the ST Micro variants */
 119 #define MCI_ST_SDIOITC          (1 << 22)
 120 #define MCI_ST_CEATAENDC        (1 << 23)
 121
 122 #define MMCIMASK0               0x03c
 123 #define MCI_CMDCRCFAILMASK      (1 << 0)
 124 #define MCI_DATACRCFAILMASK     (1 << 1)
 125 #define MCI_CMDTIMEOUTMASK      (1 << 2)
 126 #define MCI_DATATIMEOUTMASK     (1 << 3)
 127 #define MCI_TXUNDERRUNMASK      (1 << 4)
 128 #define MCI_RXOVERRUNMASK       (1 << 5)
 129 #define MCI_CMDRESPENDMASK      (1 << 6)
 130 #define MCI_CMDSENTMASK         (1 << 7)
 131 #define MCI_DATAENDMASK         (1 << 8)
 132 #define MCI_STARTBITERRMASK     (1 << 9)
 133 #define MCI_DATABLOCKENDMASK    (1 << 10)
 134 #define MCI_CMDACTIVEMASK       (1 << 11)
 135 #define MCI_TXACTIVEMASK        (1 << 12)
 136 #define MCI_RXACTIVEMASK        (1 << 13)
 137 #define MCI_TXFIFOHALFEMPTYMASK (1 << 14)
 138 #define MCI_RXFIFOHALFFULLMASK  (1 << 15)
 139 #define MCI_TXFIFOFULLMASK      (1 << 16)
 140 #define MCI_RXFIFOFULLMASK      (1 << 17)
 141 #define MCI_TXFIFOEMPTYMASK     (1 << 18)
 142 #define MCI_RXFIFOEMPTYMASK     (1 << 19)
 143 #define MCI_TXDATAAVLBLMASK     (1 << 20)
 144 #define MCI_RXDATAAVLBLMASK     (1 << 21)
 145 /* Extended status bits for the ST Micro variants */
 146 #define MCI_ST_SDIOITMASK       (1 << 22)
 147 #define MCI_ST_CEATAENDMASK     (1 << 23)
 148
 149 #define MMCIMASK1               0x040
 150 #define MMCIFIFOCNT             0x048
 151 #define MMCIFIFO                0x080 /* to 0x0bc */
 152
 153 #define MCI_IRQENABLE   \
 154         (MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK|     \
 155         MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK|       \
 156         MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_STARTBITERRMASK)
 157
 158 /* These interrupts are directed to IRQ1 when two IRQ lines are available */
 159 #define MCI_IRQ1MASK \
 160         (MCI_RXFIFOHALFFULLMASK | MCI_RXDATAAVLBLMASK | \
 161          MCI_TXFIFOHALFEMPTYMASK)
 162
 163 #define NR_SG           16
 164
 165 struct clk;
 166 struct variant_data;
 167 struct dma_chan;
 168
 169 struct mmci_host_next {
 170         struct dma_async_tx_descriptor  *dma_desc;
 171         struct dma_chan                 *dma_chan;
 172         s32                             cookie;
 173 };
 174
 175 struct mmci_host {
 176         phys_addr_t             phybase;
 177         void __iomem            *base;
 178         struct mmc_request      *mrq;
 179         struct mmc_command      *cmd;
 180         struct mmc_data         *data;
 181         struct mmc_host         *mmc;
 182         struct clk              *clk;
 183         int                     gpio_cd;
 184         int                     gpio_wp;
 185         int                     gpio_cd_irq;
 186         bool                    singleirq;
 187
 188         spinlock_t              lock;
 189
 190         unsigned int            mclk;
 191         unsigned int            cclk;
 192         u32                     pwr;
 193         struct mmci_platform_data *plat;
 194         struct variant_data     *variant;
 195
 196         u8                      hw_designer;
 197         u8                      hw_revision:4;
 198
 199         struct timer_list       timer;
 200         unsigned int            oldstat;
 201
 202         /* pio stuff */
 203         struct sg_mapping_iter  sg_miter;
 204         unsigned int            size;
 205         struct regulator        *vcc;
 206
 207 #ifdef CONFIG_DMA_ENGINE
 208         /* DMA stuff */
 209         struct dma_chan         *dma_current;
 210         struct dma_chan         *dma_rx_channel;
 211         struct dma_chan         *dma_tx_channel;
 212         struct dma_async_tx_descriptor  *dma_desc_current;
 213         struct mmci_host_next   next_data;
 214
 215 #define dma_inprogress(host)    ((host)->dma_current)
 216 #else
 217 #define dma_inprogress(host)    (0)
 218 #endif
 219 };
 220