drivers/net/can/ti_hecc.c

   1 /*
   2  * TI HECC (CAN) device driver
   3  *
   4  * This driver supports TI's HECC (High End CAN Controller module) and the
   5  * specs for the same is available at <http://www.ti.com>
   6  *
   7  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation version 2.
  12  *
  13  * This program is distributed as is WITHOUT ANY WARRANTY of any
  14  * kind, whether express or implied; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 /*
  21  * Your platform definitions should specify module ram offsets and interrupt
  22  * number to use as follows:
  23  *
  24  * static struct ti_hecc_platform_data am3517_evm_hecc_pdata = {
  25  *         .scc_hecc_offset        = 0,
  26  *         .scc_ram_offset         = 0x3000,
  27  *         .hecc_ram_offset        = 0x3000,
  28  *         .mbx_offset             = 0x2000,
  29  *         .int_line               = 0,
  30  *         .revision               = 1,
  31  *         .transceiver_switch     = hecc_phy_control,
  32  * };
  33  *
  34  * Please see include/linux/can/platform/ti_hecc.h for description of
  35  * above fields.
  36  *
  37  */
  38
  39 #include <linux/module.h>
  40 #include <linux/init.h>
  41 #include <linux/kernel.h>
  42 #include <linux/types.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/errno.h>
  45 #include <linux/netdevice.h>
  46 #include <linux/skbuff.h>
  47 #include <linux/platform_device.h>
  48 #include <linux/clk.h>
  49 #include <linux/io.h>
  50
  51 #include <linux/can/dev.h>
  52 #include <linux/can/error.h>
  53 #include <linux/can/platform/ti_hecc.h>
  54
  55 #define DRV_NAME "ti_hecc"
  56 #define HECC_MODULE_VERSION     "0.7"
  57 MODULE_VERSION(HECC_MODULE_VERSION);
  58 #define DRV_DESC "TI High End CAN Controller Driver " HECC_MODULE_VERSION
  59
  60 /* TX / RX Mailbox Configuration */
  61 #define HECC_MAX_MAILBOXES      32      /* hardware mailboxes - do not change */
  62 #define MAX_TX_PRIO             0x3F    /* hardware value - do not change */
  63
  64 /*
  65  * Important Note: TX mailbox configuration
  66  * TX mailboxes should be restricted to the number of SKB buffers to avoid
  67  * maintaining SKB buffers separately. TX mailboxes should be a power of 2
  68  * for the mailbox logic to work.  Top mailbox numbers are reserved for RX
  69  * and lower mailboxes for TX.
  70  *
  71  * HECC_MAX_TX_MBOX     HECC_MB_TX_SHIFT
  72  * 4 (default)          2
  73  * 8                    3
  74  * 16                   4
  75  */
  76 #define HECC_MB_TX_SHIFT        2 /* as per table above */
  77 #define HECC_MAX_TX_MBOX        BIT(HECC_MB_TX_SHIFT)
  78
  79 #define HECC_TX_PRIO_SHIFT      (HECC_MB_TX_SHIFT)
  80 #define HECC_TX_PRIO_MASK       (MAX_TX_PRIO << HECC_MB_TX_SHIFT)
  81 #define HECC_TX_MB_MASK         (HECC_MAX_TX_MBOX - 1)
  82 #define HECC_TX_MASK            ((HECC_MAX_TX_MBOX - 1) | HECC_TX_PRIO_MASK)
  83 #define HECC_TX_MBOX_MASK       (~(BIT(HECC_MAX_TX_MBOX) - 1))
  84 #define HECC_DEF_NAPI_WEIGHT    HECC_MAX_RX_MBOX
  85
  86 /*
  87  * Important Note: RX mailbox configuration
  88  * RX mailboxes are further logically split into two - main and buffer
  89  * mailboxes. The goal is to get all packets into main mailboxes as
  90  * driven by mailbox number and receive priority (higher to lower) and
  91  * buffer mailboxes are used to receive pkts while main mailboxes are being
  92  * processed. This ensures in-order packet reception.
  93  *
  94  * Here are the recommended values for buffer mailbox. Note that RX mailboxes
  95  * start after TX mailboxes:
  96  *
  97  * HECC_MAX_RX_MBOX             HECC_RX_BUFFER_MBOX     No of buffer mailboxes
  98  * 28                           12                      8
  99  * 16                           20                      4
 100  */
 101
 102 #define HECC_MAX_RX_MBOX        (HECC_MAX_MAILBOXES - HECC_MAX_TX_MBOX)
 103 #define HECC_RX_BUFFER_MBOX     12 /* as per table above */
 104 #define HECC_RX_FIRST_MBOX      (HECC_MAX_MAILBOXES - 1)
 105 #define HECC_RX_HIGH_MBOX_MASK  (~(BIT(HECC_RX_BUFFER_MBOX) - 1))
 106
 107 /* TI HECC module registers */
 108 #define HECC_CANME              0x0     /* Mailbox enable */
 109 #define HECC_CANMD              0x4     /* Mailbox direction */
 110 #define HECC_CANTRS             0x8     /* Transmit request set */
 111 #define HECC_CANTRR             0xC     /* Transmit request */
 112 #define HECC_CANTA              0x10    /* Transmission acknowledge */
 113 #define HECC_CANAA              0x14    /* Abort acknowledge */
 114 #define HECC_CANRMP             0x18    /* Receive message pending */
 115 #define HECC_CANRML             0x1C    /* Remote message lost */
 116 #define HECC_CANRFP             0x20    /* Remote frame pending */
 117 #define HECC_CANGAM             0x24    /* SECC only:Global acceptance mask */
 118 #define HECC_CANMC              0x28    /* Master control */
 119 #define HECC_CANBTC             0x2C    /* Bit timing configuration */
 120 #define HECC_CANES              0x30    /* Error and status */
 121 #define HECC_CANTEC             0x34    /* Transmit error counter */
 122 #define HECC_CANREC             0x38    /* Receive error counter */
 123 #define HECC_CANGIF0            0x3C    /* Global interrupt flag 0 */
 124 #define HECC_CANGIM             0x40    /* Global interrupt mask */
 125 #define HECC_CANGIF1            0x44    /* Global interrupt flag 1 */
 126 #define HECC_CANMIM             0x48    /* Mailbox interrupt mask */
 127 #define HECC_CANMIL             0x4C    /* Mailbox interrupt level */
 128 #define HECC_CANOPC             0x50    /* Overwrite protection control */
 129 #define HECC_CANTIOC            0x54    /* Transmit I/O control */
 130 #define HECC_CANRIOC            0x58    /* Receive I/O control */
 131 #define HECC_CANLNT             0x5C    /* HECC only: Local network time */
 132 #define HECC_CANTOC             0x60    /* HECC only: Time-out control */
 133 #define HECC_CANTOS             0x64    /* HECC only: Time-out status */
 134 #define HECC_CANTIOCE           0x68    /* SCC only:Enhanced TX I/O control */
 135 #define HECC_CANRIOCE           0x6C    /* SCC only:Enhanced RX I/O control */
 136
 137 /* Mailbox registers */
 138 #define HECC_CANMID             0x0
 139 #define HECC_CANMCF             0x4
 140 #define HECC_CANMDL             0x8
 141 #define HECC_CANMDH             0xC
 142
 143 #define HECC_SET_REG            0xFFFFFFFF
 144 #define HECC_CANID_MASK         0x3FF   /* 18 bits mask for extended id's */
 145 #define HECC_CCE_WAIT_COUNT     100     /* Wait for ~1 sec for CCE bit */
 146
 147 #define HECC_CANMC_SCM          BIT(13) /* SCC compat mode */
 148 #define HECC_CANMC_CCR          BIT(12) /* Change config request */
 149 #define HECC_CANMC_PDR          BIT(11) /* Local Power down - for sleep mode */
 150 #define HECC_CANMC_ABO          BIT(7)  /* Auto Bus On */
 151 #define HECC_CANMC_STM          BIT(6)  /* Self test mode - loopback */
 152 #define HECC_CANMC_SRES         BIT(5)  /* Software reset */
 153
 154 #define HECC_CANTIOC_EN         BIT(3)  /* Enable CAN TX I/O pin */
 155 #define HECC_CANRIOC_EN         BIT(3)  /* Enable CAN RX I/O pin */
 156
 157 #define HECC_CANMID_IDE         BIT(31) /* Extended frame format */
 158 #define HECC_CANMID_AME         BIT(30) /* Acceptance mask enable */
 159 #define HECC_CANMID_AAM         BIT(29) /* Auto answer mode */
 160
 161 #define HECC_CANES_FE           BIT(24) /* form error */
 162 #define HECC_CANES_BE           BIT(23) /* bit error */
 163 #define HECC_CANES_SA1          BIT(22) /* stuck at dominant error */
 164 #define HECC_CANES_CRCE         BIT(21) /* CRC error */
 165 #define HECC_CANES_SE           BIT(20) /* stuff bit error */
 166 #define HECC_CANES_ACKE         BIT(19) /* ack error */
 167 #define HECC_CANES_BO           BIT(18) /* Bus off status */
 168 #define HECC_CANES_EP           BIT(17) /* Error passive status */
 169 #define HECC_CANES_EW           BIT(16) /* Error warning status */
 170 #define HECC_CANES_SMA          BIT(5)  /* suspend mode ack */
 171 #define HECC_CANES_CCE          BIT(4)  /* Change config enabled */
 172 #define HECC_CANES_PDA          BIT(3)  /* Power down mode ack */
 173
 174 #define HECC_CANBTC_SAM         BIT(7)  /* sample points */
 175
 176 #define HECC_BUS_ERROR          (HECC_CANES_FE | HECC_CANES_BE |\
 177                                 HECC_CANES_CRCE | HECC_CANES_SE |\
 178                                 HECC_CANES_ACKE)
 179
 180 #define HECC_CANMCF_RTR         BIT(4)  /* Remote transmit request */
 181
 182 #define HECC_CANGIF_MAIF        BIT(17) /* Message alarm interrupt */
 183 #define HECC_CANGIF_TCOIF       BIT(16) /* Timer counter overflow int */
 184 #define HECC_CANGIF_GMIF        BIT(15) /* Global mailbox interrupt */
 185 #define HECC_CANGIF_AAIF        BIT(14) /* Abort ack interrupt */
 186 #define HECC_CANGIF_WDIF        BIT(13) /* Write denied interrupt */
 187 #define HECC_CANGIF_WUIF        BIT(12) /* Wake up interrupt */
 188 #define HECC_CANGIF_RMLIF       BIT(11) /* Receive message lost interrupt */
 189 #define HECC_CANGIF_BOIF        BIT(10) /* Bus off interrupt */
 190 #define HECC_CANGIF_EPIF        BIT(9)  /* Error passive interrupt */
 191 #define HECC_CANGIF_WLIF        BIT(8)  /* Warning level interrupt */
 192 #define HECC_CANGIF_MBOX_MASK   0x1F    /* Mailbox number mask */
 193 #define HECC_CANGIM_I1EN        BIT(1)  /* Int line 1 enable */
 194 #define HECC_CANGIM_I0EN        BIT(0)  /* Int line 0 enable */
 195 #define HECC_CANGIM_DEF_MASK    0x700   /* only busoff/warning/passive */
 196 #define HECC_CANGIM_SIL         BIT(2)  /* system interrupts to int line 1 */
 197
 198 /* CAN Bittiming constants as per HECC specs */
 199 static struct can_bittiming_const ti_hecc_bittiming_const = {
 200         .name = DRV_NAME,
 201         .tseg1_min = 1,
 202         .tseg1_max = 16,
 203         .tseg2_min = 1,
 204         .tseg2_max = 8,
 205         .sjw_max = 4,
 206         .brp_min = 1,
 207         .brp_max = 256,
 208         .brp_inc = 1,
 209 };
 210
 211 struct ti_hecc_priv {
 212         struct can_priv can;    /* MUST be first member/field */
 213         struct napi_struct napi;
 214         struct net_device *ndev;
 215         struct clk *clk;
 216         void __iomem *base;
 217         u32 scc_ram_offset;
 218         u32 hecc_ram_offset;
 219         u32 mbx_offset;
 220         u32 int_line;
 221         spinlock_t mbx_lock; /* CANME register needs protection */
 222         u32 tx_head;
 223         u32 tx_tail;
 224         u32 rx_next;
 225         void (*transceiver_switch)(int);
 226 };
 227
 228 static inline int get_tx_head_mb(struct ti_hecc_priv *priv)
 229 {
 230         return priv->tx_head & HECC_TX_MB_MASK;
 231 }
 232
 233 static inline int get_tx_tail_mb(struct ti_hecc_priv *priv)
 234 {
 235         return priv->tx_tail & HECC_TX_MB_MASK;
 236 }
 237
 238 static inline int get_tx_head_prio(struct ti_hecc_priv *priv)
 239 {
 240         return (priv->tx_head >> HECC_TX_PRIO_SHIFT) & MAX_TX_PRIO;
 241 }
 242
 243 static inline void hecc_write_lam(struct ti_hecc_priv *priv, u32 mbxno, u32 val)
 244 {
 245         __raw_writel(val, priv->base + priv->hecc_ram_offset + mbxno * 4);
 246 }
 247
 248 static inline void hecc_write_mbx(struct ti_hecc_priv *priv, u32 mbxno,
 249         u32 reg, u32 val)
 250 {
 251         __raw_writel(val, priv->base + priv->mbx_offset + mbxno * 0x10 +
 252                         reg);
 253 }
 254
 255 static inline u32 hecc_read_mbx(struct ti_hecc_priv *priv, u32 mbxno, u32 reg)
 256 {
 257         return __raw_readl(priv->base + priv->mbx_offset + mbxno * 0x10 +
 258                         reg);
 259 }
 260
 261 static inline void hecc_write(struct ti_hecc_priv *priv, u32 reg, u32 val)
 262 {
 263         __raw_writel(val, priv->base + reg);
 264 }
 265
 266 static inline u32 hecc_read(struct ti_hecc_priv *priv, int reg)
 267 {
 268         return __raw_readl(priv->base + reg);
 269 }
 270
 271 static inline void hecc_set_bit(struct ti_hecc_priv *priv, int reg,
 272         u32 bit_mask)
 273 {
 274         hecc_write(priv, reg, hecc_read(priv, reg) | bit_mask);
 275 }
 276
 277 static inline void hecc_clear_bit(struct ti_hecc_priv *priv, int reg,
 278         u32 bit_mask)
 279 {
 280         hecc_write(priv, reg, hecc_read(priv, reg) & ~bit_mask);
 281 }
 282
 283 static inline u32 hecc_get_bit(struct ti_hecc_priv *priv, int reg, u32 bit_mask)
 284 {
 285         return (hecc_read(priv, reg) & bit_mask) ? 1 : 0;
 286 }
 287
 288 static int ti_hecc_get_state(const struct net_device *ndev,
 289         enum can_state *state)
 290 {
 291         struct ti_hecc_priv *priv = netdev_priv(ndev);
 292
 293         *state = priv->can.state;
 294         return 0;
 295 }
 296
 297 static int ti_hecc_set_btc(struct ti_hecc_priv *priv)
 298 {
 299         struct can_bittiming *bit_timing = &priv->can.bittiming;
 300         u32 can_btc;
 301
 302         can_btc = (bit_timing->phase_seg2 - 1) & 0x7;
 303         can_btc |= ((bit_timing->phase_seg1 + bit_timing->prop_seg - 1)
 304                         & 0xF) << 3;
 305         if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) {
 306                 if (bit_timing->brp > 4)
 307                         can_btc |= HECC_CANBTC_SAM;
 308                 else
 309                         dev_warn(priv->ndev->dev.parent, "WARN: Triple" \
 310                                 "sampling not set due to h/w limitations");
 311         }
 312         can_btc |= ((bit_timing->sjw - 1) & 0x3) << 8;
 313         can_btc |= ((bit_timing->brp - 1) & 0xFF) << 16;
 314
 315         /* ERM being set to 0 by default meaning resync at falling edge */
 316
 317         hecc_write(priv, HECC_CANBTC, can_btc);
 318         dev_info(priv->ndev->dev.parent, "setting CANBTC=%#x\n", can_btc);
 319
 320         return 0;
 321 }
 322
 323 static void ti_hecc_transceiver_switch(const struct ti_hecc_priv *priv,
 324                                         int on)
 325 {
 326         if (priv->transceiver_switch)
 327                 priv->transceiver_switch(on);
 328 }
 329
 330 static void ti_hecc_reset(struct net_device *ndev)
 331 {
 332         u32 cnt;
 333         struct ti_hecc_priv *priv = netdev_priv(ndev);
 334
 335         dev_dbg(ndev->dev.parent, "resetting hecc ...\n");
 336         hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SRES);
 337
 338         /* Set change control request and wait till enabled */
 339         hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
 340
 341         /*
 342          * INFO: It has been observed that at times CCE bit may not be
 343          * set and hw seems to be ok even if this bit is not set so
 344          * timing out with a timing of 1ms to respect the specs
 345          */
 346         cnt = HECC_CCE_WAIT_COUNT;
 347         while (!hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) {
 348                 --cnt;
 349                 udelay(10);
 350         }
 351
 352         /*
 353          * Note: On HECC, BTC can be programmed only in initialization mode, so
 354          * it is expected that the can bittiming parameters are set via ip
 355          * utility before the device is opened
 356          */
 357         ti_hecc_set_btc(priv);
 358
 359         /* Clear CCR (and CANMC register) and wait for CCE = 0 enable */
 360         hecc_write(priv, HECC_CANMC, 0);
 361
 362         /*
 363          * INFO: CAN net stack handles bus off and hence disabling auto-bus-on
 364          * hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_ABO);
 365          */
 366
 367         /*
 368          * INFO: It has been observed that at times CCE bit may not be
 369          * set and hw seems to be ok even if this bit is not set so
 370          */
 371         cnt = HECC_CCE_WAIT_COUNT;
 372         while (hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) {
 373                 --cnt;
 374                 udelay(10);
 375         }
 376
 377         /* Enable TX and RX I/O Control pins */
 378         hecc_write(priv, HECC_CANTIOC, HECC_CANTIOC_EN);
 379         hecc_write(priv, HECC_CANRIOC, HECC_CANRIOC_EN);
 380
 381         /* Clear registers for clean operation */
 382         hecc_write(priv, HECC_CANTA, HECC_SET_REG);
 383         hecc_write(priv, HECC_CANRMP, HECC_SET_REG);
 384         hecc_write(priv, HECC_CANGIF0, HECC_SET_REG);
 385         hecc_write(priv, HECC_CANGIF1, HECC_SET_REG);
 386         hecc_write(priv, HECC_CANME, 0);
 387         hecc_write(priv, HECC_CANMD, 0);
 388
 389         /* SCC compat mode NOT supported (and not needed too) */
 390         hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SCM);
 391 }
 392
 393 static void ti_hecc_start(struct net_device *ndev)
 394 {
 395         struct ti_hecc_priv *priv = netdev_priv(ndev);
 396         u32 cnt, mbxno, mbx_mask;
 397
 398         /* put HECC in initialization mode and set btc */
 399         ti_hecc_reset(ndev);
 400
 401         priv->tx_head = priv->tx_tail = HECC_TX_MASK;
 402         priv->rx_next = HECC_RX_FIRST_MBOX;
 403
 404         /* Enable local and global acceptance mask registers */
 405         hecc_write(priv, HECC_CANGAM, HECC_SET_REG);
 406
 407         /* Prepare configured mailboxes to receive messages */
 408         for (cnt = 0; cnt < HECC_MAX_RX_MBOX; cnt++) {
 409                 mbxno = HECC_MAX_MAILBOXES - 1 - cnt;
 410                 mbx_mask = BIT(mbxno);
 411                 hecc_clear_bit(priv, HECC_CANME, mbx_mask);
 412                 hecc_write_mbx(priv, mbxno, HECC_CANMID, HECC_CANMID_AME);
 413                 hecc_write_lam(priv, mbxno, HECC_SET_REG);
 414                 hecc_set_bit(priv, HECC_CANMD, mbx_mask);
 415                 hecc_set_bit(priv, HECC_CANME, mbx_mask);
 416                 hecc_set_bit(priv, HECC_CANMIM, mbx_mask);
 417         }
 418
 419         /* Prevent message over-write & Enable interrupts */
 420         hecc_write(priv, HECC_CANOPC, HECC_SET_REG);
 421         if (priv->int_line) {
 422                 hecc_write(priv, HECC_CANMIL, HECC_SET_REG);
 423                 hecc_write(priv, HECC_CANGIM, HECC_CANGIM_DEF_MASK |
 424                         HECC_CANGIM_I1EN | HECC_CANGIM_SIL);
 425         } else {
 426                 hecc_write(priv, HECC_CANMIL, 0);
 427                 hecc_write(priv, HECC_CANGIM,
 428                         HECC_CANGIM_DEF_MASK | HECC_CANGIM_I0EN);
 429         }
 430         priv->can.state = CAN_STATE_ERROR_ACTIVE;
 431 }
 432
 433 static void ti_hecc_stop(struct net_device *ndev)
 434 {
 435         struct ti_hecc_priv *priv = netdev_priv(ndev);
 436
 437         /* Disable interrupts and disable mailboxes */
 438         hecc_write(priv, HECC_CANGIM, 0);
 439         hecc_write(priv, HECC_CANMIM, 0);
 440         hecc_write(priv, HECC_CANME, 0);
 441         priv->can.state = CAN_STATE_STOPPED;
 442 }
 443
 444 static int ti_hecc_do_set_mode(struct net_device *ndev, enum can_mode mode)
 445 {
 446         int ret = 0;
 447
 448         switch (mode) {
 449         case CAN_MODE_START:
 450                 ti_hecc_start(ndev);
 451                 netif_wake_queue(ndev);
 452                 break;
 453         default:
 454                 ret = -EOPNOTSUPP;
 455                 break;
 456         }
 457
 458         return ret;
 459 }
 460
 461 /*
 462  * ti_hecc_xmit: HECC Transmit
 463  *
 464  * The transmit mailboxes start from 0 to HECC_MAX_TX_MBOX. In HECC the
 465  * priority of the mailbox for tranmission is dependent upon priority setting
 466  * field in mailbox registers. The mailbox with highest value in priority field
 467  * is transmitted first. Only when two mailboxes have the same value in
 468  * priority field the highest numbered mailbox is transmitted first.
 469  *
 470  * To utilize the HECC priority feature as described above we start with the
 471  * highest numbered mailbox with highest priority level and move on to the next
 472  * mailbox with the same priority level and so on. Once we loop through all the
 473  * transmit mailboxes we choose the next priority level (lower) and so on
 474  * until we reach the lowest priority level on the lowest numbered mailbox
 475  * when we stop transmission until all mailboxes are transmitted and then
 476  * restart at highest numbered mailbox with highest priority.
 477  *
 478  * Two counters (head and tail) are used to track the next mailbox to transmit
 479  * and to track the echo buffer for already transmitted mailbox. The queue
 480  * is stopped when all the mailboxes are busy or when there is a priority
 481  * value roll-over happens.
 482  */
 483 static netdev_tx_t ti_hecc_xmit(struct sk_buff *skb, struct net_device *ndev)
 484 {
 485         struct ti_hecc_priv *priv = netdev_priv(ndev);
 486         struct can_frame *cf = (struct can_frame *)skb->data;
 487         u32 mbxno, mbx_mask, data;
 488         unsigned long flags;
 489
 490         if (can_dropped_invalid_skb(ndev, skb))
 491                 return NETDEV_TX_OK;
 492
 493         mbxno = get_tx_head_mb(priv);
 494         mbx_mask = BIT(mbxno);
 495         spin_lock_irqsave(&priv->mbx_lock, flags);
 496         if (unlikely(hecc_read(priv, HECC_CANME) & mbx_mask)) {
 497                 spin_unlock_irqrestore(&priv->mbx_lock, flags);
 498                 netif_stop_queue(ndev);
 499                 dev_err(priv->ndev->dev.parent,
 500                         "BUG: TX mbx not ready tx_head=%08X, tx_tail=%08X\n",
 501                         priv->tx_head, priv->tx_tail);
 502                 return NETDEV_TX_BUSY;
 503         }
 504         spin_unlock_irqrestore(&priv->mbx_lock, flags);
 505
 506         /* Prepare mailbox for transmission */
 507         data = cf->can_dlc | (get_tx_head_prio(priv) << 8);
 508         if (cf->can_id & CAN_RTR_FLAG) /* Remote transmission request */
 509                 data |= HECC_CANMCF_RTR;
 510         hecc_write_mbx(priv, mbxno, HECC_CANMCF, data);
 511
 512         if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */
 513                 data = (cf->can_id & CAN_EFF_MASK) | HECC_CANMID_IDE;
 514         else /* Standard frame format */
 515                 data = (cf->can_id & CAN_SFF_MASK) << 18;
 516         hecc_write_mbx(priv, mbxno, HECC_CANMID, data);
 517         hecc_write_mbx(priv, mbxno, HECC_CANMDL,
 518                 be32_to_cpu(*(u32 *)(cf->data)));
 519         if (cf->can_dlc > 4)
 520                 hecc_write_mbx(priv, mbxno, HECC_CANMDH,
 521                         be32_to_cpu(*(u32 *)(cf->data + 4)));
 522         else
 523                 *(u32 *)(cf->data + 4) = 0;
 524         can_put_echo_skb(skb, ndev, mbxno);
 525
 526         spin_lock_irqsave(&priv->mbx_lock, flags);
 527         --priv->tx_head;
 528         if ((hecc_read(priv, HECC_CANME) & BIT(get_tx_head_mb(priv))) ||
 529                 (priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK) {
 530                 netif_stop_queue(ndev);
 531         }
 532         hecc_set_bit(priv, HECC_CANME, mbx_mask);
 533         spin_unlock_irqrestore(&priv->mbx_lock, flags);
 534
 535         hecc_clear_bit(priv, HECC_CANMD, mbx_mask);
 536         hecc_set_bit(priv, HECC_CANMIM, mbx_mask);
 537         hecc_write(priv, HECC_CANTRS, mbx_mask);
 538
 539         return NETDEV_TX_OK;
 540 }
 541
 542 static int ti_hecc_rx_pkt(struct ti_hecc_priv *priv, int mbxno)
 543 {
 544         struct net_device_stats *stats = &priv->ndev->stats;
 545         struct can_frame *cf;
 546         struct sk_buff *skb;
 547         u32 data, mbx_mask;
 548         unsigned long flags;
 549
 550         skb = alloc_can_skb(priv->ndev, &cf);
 551         if (!skb) {
 552                 if (printk_ratelimit())
 553                         dev_err(priv->ndev->dev.parent,
 554                                 "ti_hecc_rx_pkt: alloc_can_skb() failed\n");
 555                 return -ENOMEM;
 556         }
 557
 558         mbx_mask = BIT(mbxno);
 559         data = hecc_read_mbx(priv, mbxno, HECC_CANMID);
 560         if (data & HECC_CANMID_IDE)
 561                 cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG;
 562         else
 563                 cf->can_id = (data >> 18) & CAN_SFF_MASK;
 564         data = hecc_read_mbx(priv, mbxno, HECC_CANMCF);
 565         if (data & HECC_CANMCF_RTR)
 566                 cf->can_id |= CAN_RTR_FLAG;
 567         cf->can_dlc = get_can_dlc(data & 0xF);
 568         data = hecc_read_mbx(priv, mbxno, HECC_CANMDL);
 569         *(u32 *)(cf->data) = cpu_to_be32(data);
 570         if (cf->can_dlc > 4) {
 571                 data = hecc_read_mbx(priv, mbxno, HECC_CANMDH);
 572                 *(u32 *)(cf->data + 4) = cpu_to_be32(data);
 573         } else {
 574                 *(u32 *)(cf->data + 4) = 0;
 575         }
 576         spin_lock_irqsave(&priv->mbx_lock, flags);
 577         hecc_clear_bit(priv, HECC_CANME, mbx_mask);
 578         hecc_write(priv, HECC_CANRMP, mbx_mask);
 579         /* enable mailbox only if it is part of rx buffer mailboxes */
 580         if (priv->rx_next < HECC_RX_BUFFER_MBOX)
 581                 hecc_set_bit(priv, HECC_CANME, mbx_mask);
 582         spin_unlock_irqrestore(&priv->mbx_lock, flags);
 583
 584         stats->rx_bytes += cf->can_dlc;
 585         netif_receive_skb(skb);
 586         stats->rx_packets++;
 587
 588         return 0;
 589 }
 590
 591 /*
 592  * ti_hecc_rx_poll - HECC receive pkts
 593  *
 594  * The receive mailboxes start from highest numbered mailbox till last xmit
 595  * mailbox. On CAN frame reception the hardware places the data into highest
 596  * numbered mailbox that matches the CAN ID filter. Since all receive mailboxes
 597  * have same filtering (ALL CAN frames) packets will arrive in the highest
 598  * available RX mailbox and we need to ensure in-order packet reception.
 599  *
 600  * To ensure the packets are received in the right order we logically divide
 601  * the RX mailboxes into main and buffer mailboxes. Packets are received as per
 602  * mailbox priotity (higher to lower) in the main bank and once it is full we
 603  * disable further reception into main mailboxes. While the main mailboxes are
 604  * processed in NAPI, further packets are received in buffer mailboxes.
 605  *
 606  * We maintain a RX next mailbox counter to process packets and once all main
 607  * mailboxe packets are passed to the upper stack we enable all of them but
 608  * continue to process packets received in buffer mailboxes. With each packet
 609  * received from buffer mailbox we enable it immediately so as to handle the
 610  * overflow from higher mailboxes.
 611  */
 612 static int ti_hecc_rx_poll(struct napi_struct *napi, int quota)
 613 {
 614         struct net_device *ndev = napi->dev;
 615         struct ti_hecc_priv *priv = netdev_priv(ndev);
 616         u32 num_pkts = 0;
 617         u32 mbx_mask;
 618         unsigned long pending_pkts, flags;
 619
 620         if (!netif_running(ndev))
 621                 return 0;
 622
 623         while ((pending_pkts = hecc_read(priv, HECC_CANRMP)) &&
 624                 num_pkts < quota) {
 625                 mbx_mask = BIT(priv->rx_next); /* next rx mailbox to process */
 626                 if (mbx_mask & pending_pkts) {
 627                         if (ti_hecc_rx_pkt(priv, priv->rx_next) < 0)
 628                                 return num_pkts;
 629                         ++num_pkts;
 630                 } else if (priv->rx_next > HECC_RX_BUFFER_MBOX) {
 631                         break; /* pkt not received yet */
 632                 }
 633                 --priv->rx_next;
 634                 if (priv->rx_next == HECC_RX_BUFFER_MBOX) {
 635                         /* enable high bank mailboxes */
 636                         spin_lock_irqsave(&priv->mbx_lock, flags);
 637                         mbx_mask = hecc_read(priv, HECC_CANME);
 638                         mbx_mask |= HECC_RX_HIGH_MBOX_MASK;
 639                         hecc_write(priv, HECC_CANME, mbx_mask);
 640                         spin_unlock_irqrestore(&priv->mbx_lock, flags);
 641                 } else if (priv->rx_next == HECC_MAX_TX_MBOX - 1) {
 642                         priv->rx_next = HECC_RX_FIRST_MBOX;
 643                         break;
 644                 }
 645         }
 646
 647         /* Enable packet interrupt if all pkts are handled */
 648         if (hecc_read(priv, HECC_CANRMP) == 0) {
 649                 napi_complete(napi);
 650                 /* Re-enable RX mailbox interrupts */
 651                 mbx_mask = hecc_read(priv, HECC_CANMIM);
 652                 mbx_mask |= HECC_TX_MBOX_MASK;
 653                 hecc_write(priv, HECC_CANMIM, mbx_mask);
 654         }
 655
 656         return num_pkts;
 657 }
 658
 659 static int ti_hecc_error(struct net_device *ndev, int int_status,
 660         int err_status)
 661 {
 662         struct ti_hecc_priv *priv = netdev_priv(ndev);
 663         struct net_device_stats *stats = &ndev->stats;
 664         struct can_frame *cf;
 665         struct sk_buff *skb;
 666
 667         /* propagate the error condition to the can stack */
 668         skb = alloc_can_err_skb(ndev, &cf);
 669         if (!skb) {
 670                 if (printk_ratelimit())
 671                         dev_err(priv->ndev->dev.parent,
 672                                 "ti_hecc_error: alloc_can_err_skb() failed\n");
 673                 return -ENOMEM;
 674         }
 675
 676         if (int_status & HECC_CANGIF_WLIF) { /* warning level int */
 677                 if ((int_status & HECC_CANGIF_BOIF) == 0) {
 678                         priv->can.state = CAN_STATE_ERROR_WARNING;
 679                         ++priv->can.can_stats.error_warning;
 680                         cf->can_id |= CAN_ERR_CRTL;
 681                         if (hecc_read(priv, HECC_CANTEC) > 96)
 682                                 cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
 683                         if (hecc_read(priv, HECC_CANREC) > 96)
 684                                 cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
 685                 }
 686                 hecc_set_bit(priv, HECC_CANES, HECC_CANES_EW);
 687                 dev_dbg(priv->ndev->dev.parent, "Error Warning interrupt\n");
 688                 hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
 689         }
 690
 691         if (int_status & HECC_CANGIF_EPIF) { /* error passive int */
 692                 if ((int_status & HECC_CANGIF_BOIF) == 0) {
 693                         priv->can.state = CAN_STATE_ERROR_PASSIVE;
 694                         ++priv->can.can_stats.error_passive;
 695                         cf->can_id |= CAN_ERR_CRTL;
 696                         if (hecc_read(priv, HECC_CANTEC) > 127)
 697                                 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
 698                         if (hecc_read(priv, HECC_CANREC) > 127)
 699                                 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
 700                 }
 701                 hecc_set_bit(priv, HECC_CANES, HECC_CANES_EP);
 702                 dev_dbg(priv->ndev->dev.parent, "Error passive interrupt\n");
 703                 hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
 704         }
 705
 706         /*
 707          * Need to check busoff condition in error status register too to
 708          * ensure warning interrupts don't hog the system
 709          */
 710         if ((int_status & HECC_CANGIF_BOIF) || (err_status & HECC_CANES_BO)) {
 711                 priv->can.state = CAN_STATE_BUS_OFF;
 712                 cf->can_id |= CAN_ERR_BUSOFF;
 713                 hecc_set_bit(priv, HECC_CANES, HECC_CANES_BO);
 714                 hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
 715                 /* Disable all interrupts in bus-off to avoid int hog */
 716                 hecc_write(priv, HECC_CANGIM, 0);
 717                 can_bus_off(ndev);
 718         }
 719
 720         if (err_status & HECC_BUS_ERROR) {
 721                 ++priv->can.can_stats.bus_error;
 722                 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
 723                 cf->data[2] |= CAN_ERR_PROT_UNSPEC;
 724                 if (err_status & HECC_CANES_FE) {
 725                         hecc_set_bit(priv, HECC_CANES, HECC_CANES_FE);
 726                         cf->data[2] |= CAN_ERR_PROT_FORM;
 727                 }
 728                 if (err_status & HECC_CANES_BE) {
 729                         hecc_set_bit(priv, HECC_CANES, HECC_CANES_BE);
 730                         cf->data[2] |= CAN_ERR_PROT_BIT;
 731                 }
 732                 if (err_status & HECC_CANES_SE) {
 733                         hecc_set_bit(priv, HECC_CANES, HECC_CANES_SE);
 734                         cf->data[2] |= CAN_ERR_PROT_STUFF;
 735                 }
 736                 if (err_status & HECC_CANES_CRCE) {
 737                         hecc_set_bit(priv, HECC_CANES, HECC_CANES_CRCE);
 738                         cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ |
 739                                         CAN_ERR_PROT_LOC_CRC_DEL;
 740                 }
 741                 if (err_status & HECC_CANES_ACKE) {
 742                         hecc_set_bit(priv, HECC_CANES, HECC_CANES_ACKE);
 743                         cf->data[2] |= CAN_ERR_PROT_LOC_ACK |
 744                                         CAN_ERR_PROT_LOC_ACK_DEL;
 745                 }
 746         }
 747
 748         netif_rx(skb);
 749         stats->rx_packets++;
 750         stats->rx_bytes += cf->can_dlc;
 751
 752         return 0;
 753 }
 754
 755 static irqreturn_t ti_hecc_interrupt(int irq, void *dev_id)
 756 {
 757         struct net_device *ndev = (struct net_device *)dev_id;
 758         struct ti_hecc_priv *priv = netdev_priv(ndev);
 759         struct net_device_stats *stats = &ndev->stats;
 760         u32 mbxno, mbx_mask, int_status, err_status;
 761         unsigned long ack, flags;
 762
 763         int_status = hecc_read(priv,
 764                 (priv->int_line) ? HECC_CANGIF1 : HECC_CANGIF0);
 765
 766         if (!int_status)
 767                 return IRQ_NONE;
 768
 769         err_status = hecc_read(priv, HECC_CANES);
 770         if (err_status & (HECC_BUS_ERROR | HECC_CANES_BO |
 771                 HECC_CANES_EP | HECC_CANES_EW))
 772                         ti_hecc_error(ndev, int_status, err_status);
 773
 774         if (int_status & HECC_CANGIF_GMIF) {
 775                 while (priv->tx_tail - priv->tx_head > 0) {
 776                         mbxno = get_tx_tail_mb(priv);
 777                         mbx_mask = BIT(mbxno);
 778                         if (!(mbx_mask & hecc_read(priv, HECC_CANTA)))
 779                                 break;
 780                         hecc_clear_bit(priv, HECC_CANMIM, mbx_mask);
 781                         hecc_write(priv, HECC_CANTA, mbx_mask);
 782                         spin_lock_irqsave(&priv->mbx_lock, flags);
 783                         hecc_clear_bit(priv, HECC_CANME, mbx_mask);
 784                         spin_unlock_irqrestore(&priv->mbx_lock, flags);
 785                         stats->tx_bytes += hecc_read_mbx(priv, mbxno,
 786                                                 HECC_CANMCF) & 0xF;
 787                         stats->tx_packets++;
 788                         can_get_echo_skb(ndev, mbxno);
 789                         --priv->tx_tail;
 790                 }
 791
 792                 /* restart queue if wrap-up or if queue stalled on last pkt */
 793                 if (((priv->tx_head == priv->tx_tail) &&
 794                 ((priv->tx_head & HECC_TX_MASK) != HECC_TX_MASK)) ||
 795                 (((priv->tx_tail & HECC_TX_MASK) == HECC_TX_MASK) &&
 796                 ((priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK)))
 797                         netif_wake_queue(ndev);
 798
 799                 /* Disable RX mailbox interrupts and let NAPI reenable them */
 800                 if (hecc_read(priv, HECC_CANRMP)) {
 801                         ack = hecc_read(priv, HECC_CANMIM);
 802                         ack &= BIT(HECC_MAX_TX_MBOX) - 1;
 803                         hecc_write(priv, HECC_CANMIM, ack);
 804                         napi_schedule(&priv->napi);
 805                 }
 806         }
 807
 808         /* clear all interrupt conditions - read back to avoid spurious ints */
 809         if (priv->int_line) {
 810                 hecc_write(priv, HECC_CANGIF1, HECC_SET_REG);
 811                 int_status = hecc_read(priv, HECC_CANGIF1);
 812         } else {
 813                 hecc_write(priv, HECC_CANGIF0, HECC_SET_REG);
 814                 int_status = hecc_read(priv, HECC_CANGIF0);
 815         }
 816
 817         return IRQ_HANDLED;
 818 }
 819
 820 static int ti_hecc_open(struct net_device *ndev)
 821 {
 822         struct ti_hecc_priv *priv = netdev_priv(ndev);
 823         int err;
 824
 825         err = request_irq(ndev->irq, ti_hecc_interrupt, IRQF_SHARED,
 826                         ndev->name, ndev);
 827         if (err) {
 828                 dev_err(ndev->dev.parent, "error requesting interrupt\n");
 829                 return err;
 830         }
 831
 832         ti_hecc_transceiver_switch(priv, 1);
 833
 834         /* Open common can device */
 835         err = open_candev(ndev);
 836         if (err) {
 837                 dev_err(ndev->dev.parent, "open_candev() failed %d\n", err);
 838                 ti_hecc_transceiver_switch(priv, 0);
 839                 free_irq(ndev->irq, ndev);
 840                 return err;
 841         }
 842
 843         ti_hecc_start(ndev);
 844         napi_enable(&priv->napi);
 845         netif_start_queue(ndev);
 846
 847         return 0;
 848 }
 849
 850 static int ti_hecc_close(struct net_device *ndev)
 851 {
 852         struct ti_hecc_priv *priv = netdev_priv(ndev);
 853
 854         netif_stop_queue(ndev);
 855         napi_disable(&priv->napi);
 856         ti_hecc_stop(ndev);
 857         free_irq(ndev->irq, ndev);
 858         close_candev(ndev);
 859         ti_hecc_transceiver_switch(priv, 0);
 860
 861         return 0;
 862 }
 863
 864 static const struct net_device_ops ti_hecc_netdev_ops = {
 865         .ndo_open               = ti_hecc_open,
 866         .ndo_stop               = ti_hecc_close,
 867         .ndo_start_xmit         = ti_hecc_xmit,
 868 };
 869
 870 static int ti_hecc_probe(struct platform_device *pdev)
 871 {
 872         struct net_device *ndev = (struct net_device *)0;
 873         struct ti_hecc_priv *priv;
 874         struct ti_hecc_platform_data *pdata;
 875         struct resource *mem, *irq;
 876         void __iomem *addr;
 877         int err = -ENODEV;
 878
 879         pdata = pdev->dev.platform_data;
 880         if (!pdata) {
 881                 dev_err(&pdev->dev, "No platform data\n");
 882                 goto probe_exit;
 883         }
 884
 885         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 886         if (!mem) {
 887                 dev_err(&pdev->dev, "No mem resources\n");
 888                 goto probe_exit;
 889         }
 890         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 891         if (!irq) {
 892                 dev_err(&pdev->dev, "No irq resource\n");
 893                 goto probe_exit;
 894         }
 895         if (!request_mem_region(mem->start, resource_size(mem), pdev->name)) {
 896                 dev_err(&pdev->dev, "HECC region already claimed\n");
 897                 err = -EBUSY;
 898                 goto probe_exit;
 899         }
 900         addr = ioremap(mem->start, resource_size(mem));
 901         if (!addr) {
 902                 dev_err(&pdev->dev, "ioremap failed\n");
 903                 err = -ENOMEM;
 904                 goto probe_exit_free_region;
 905         }
 906
 907         ndev = alloc_candev(sizeof(struct ti_hecc_priv), HECC_MAX_TX_MBOX);
 908         if (!ndev) {
 909                 dev_err(&pdev->dev, "alloc_candev failed\n");
 910                 err = -ENOMEM;
 911                 goto probe_exit_iounmap;
 912         }
 913
 914         priv = netdev_priv(ndev);
 915         priv->ndev = ndev;
 916         priv->base = addr;
 917         priv->scc_ram_offset = pdata->scc_ram_offset;
 918         priv->hecc_ram_offset = pdata->hecc_ram_offset;
 919         priv->mbx_offset = pdata->mbx_offset;
 920         priv->int_line = pdata->int_line;
 921         priv->transceiver_switch = pdata->transceiver_switch;
 922
 923         priv->can.bittiming_const = &ti_hecc_bittiming_const;
 924         priv->can.do_set_mode = ti_hecc_do_set_mode;
 925         priv->can.do_get_state = ti_hecc_get_state;
 926         priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES;
 927
 928         spin_lock_init(&priv->mbx_lock);
 929         ndev->irq = irq->start;
 930         ndev->flags |= IFF_ECHO;
 931         platform_set_drvdata(pdev, ndev);
 932         SET_NETDEV_DEV(ndev, &pdev->dev);
 933         ndev->netdev_ops = &ti_hecc_netdev_ops;
 934
 935         priv->clk = clk_get(&pdev->dev, "hecc_ck");
 936         if (IS_ERR(priv->clk)) {
 937                 dev_err(&pdev->dev, "No clock available\n");
 938                 err = PTR_ERR(priv->clk);
 939                 priv->clk = NULL;
 940                 goto probe_exit_candev;
 941         }
 942         priv->can.clock.freq = clk_get_rate(priv->clk);
 943         netif_napi_add(ndev, &priv->napi, ti_hecc_rx_poll,
 944                 HECC_DEF_NAPI_WEIGHT);
 945
 946         clk_enable(priv->clk);
 947         err = register_candev(ndev);
 948         if (err) {
 949                 dev_err(&pdev->dev, "register_candev() failed\n");
 950                 goto probe_exit_clk;
 951         }
 952         dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%u)\n",
 953                 priv->base, (u32) ndev->irq);
 954
 955         return 0;
 956
 957 probe_exit_clk:
 958         clk_put(priv->clk);
 959 probe_exit_candev:
 960         free_candev(ndev);
 961 probe_exit_iounmap:
 962         iounmap(addr);
 963 probe_exit_free_region:
 964         release_mem_region(mem->start, resource_size(mem));
 965 probe_exit:
 966         return err;
 967 }
 968
 969 static int __devexit ti_hecc_remove(struct platform_device *pdev)
 970 {
 971         struct resource *res;
 972         struct net_device *ndev = platform_get_drvdata(pdev);
 973         struct ti_hecc_priv *priv = netdev_priv(ndev);
 974
 975         clk_disable(priv->clk);
 976         clk_put(priv->clk);
 977         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 978         iounmap(priv->base);
 979         release_mem_region(res->start, resource_size(res));
 980         unregister_candev(ndev);
 981         free_candev(ndev);
 982         platform_set_drvdata(pdev, NULL);
 983
 984         return 0;
 985 }
 986
 987
 988 #ifdef CONFIG_PM
 989 static int ti_hecc_suspend(struct platform_device *pdev, pm_message_t state)
 990 {
 991         struct net_device *dev = platform_get_drvdata(pdev);
 992         struct ti_hecc_priv *priv = netdev_priv(dev);
 993
 994         if (netif_running(dev)) {
 995                 netif_stop_queue(dev);
 996                 netif_device_detach(dev);
 997         }
 998
 999         hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_PDR);
1000         priv->can.state = CAN_STATE_SLEEPING;
1001
1002         clk_disable(priv->clk);
1003
1004         return 0;
1005 }
1006
1007 static int ti_hecc_resume(struct platform_device *pdev)
1008 {
1009         struct net_device *dev = platform_get_drvdata(pdev);
1010         struct ti_hecc_priv *priv = netdev_priv(dev);
1011
1012         clk_enable(priv->clk);
1013
1014         hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_PDR);
1015         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1016
1017         if (netif_running(dev)) {
1018                 netif_device_attach(dev);
1019                 netif_start_queue(dev);
1020         }
1021
1022         return 0;
1023 }
1024 #else
1025 #define ti_hecc_suspend NULL
1026 #define ti_hecc_resume NULL
1027 #endif
1028
1029 /* TI HECC netdevice driver: platform driver structure */
1030 static struct platform_driver ti_hecc_driver = {
1031         .driver = {
1032                 .name    = DRV_NAME,
1033                 .owner   = THIS_MODULE,
1034         },
1035         .probe = ti_hecc_probe,
1036         .remove = __devexit_p(ti_hecc_remove),
1037         .suspend = ti_hecc_suspend,
1038         .resume = ti_hecc_resume,
1039 };
1040
1041 module_platform_driver(ti_hecc_driver);
1042
1043 MODULE_AUTHOR("Anant Gole <anantgole@ti.com>");
1044 MODULE_LICENSE("GPL v2");
1045 MODULE_DESCRIPTION(DRV_DESC);