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Merge tag 'v3.3.7' into 3.3/master
[zen-stable.git] / drivers / net / ethernet / amd / pcnet32.c
blob20e6dab0186c78da49d43e14b5f66370936c7cf3
1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
2 /*
3 * Copyright 1996-1999 Thomas Bogendoerfer
4 *
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
6 *
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * This driver is for PCnet32 and PCnetPCI based ethercards
14 */
15 /**************************************************************************
16 * 23 Oct, 2000.
17 * Fixed a few bugs, related to running the controller in 32bit mode.
18 *
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
21 *
22 *************************************************************************/
23
24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
26 #define DRV_NAME "pcnet32"
27 #define DRV_VERSION "1.35"
28 #define DRV_RELDATE "21.Apr.2008"
29 #define PFX DRV_NAME ": "
30
31 static const char *const version =
32 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
33
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/sched.h>
37 #include <linux/string.h>
38 #include <linux/errno.h>
39 #include <linux/ioport.h>
40 #include <linux/slab.h>
41 #include <linux/interrupt.h>
42 #include <linux/pci.h>
43 #include <linux/delay.h>
44 #include <linux/init.h>
45 #include <linux/ethtool.h>
46 #include <linux/mii.h>
47 #include <linux/crc32.h>
48 #include <linux/netdevice.h>
49 #include <linux/etherdevice.h>
50 #include <linux/if_ether.h>
51 #include <linux/skbuff.h>
52 #include <linux/spinlock.h>
53 #include <linux/moduleparam.h>
54 #include <linux/bitops.h>
55 #include <linux/io.h>
56 #include <linux/uaccess.h>
57
58 #include <asm/dma.h>
59 #include <asm/irq.h>
60
61 /*
62 * PCI device identifiers for "new style" Linux PCI Device Drivers
63 */
64 static DEFINE_PCI_DEVICE_TABLE(pcnet32_pci_tbl) = {
65 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
66 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
67
68 /*
69 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
70 * the incorrect vendor id.
71 */
72 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
73 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
74
75 { } /* terminate list */
76 };
77
78 MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
79
80 static int cards_found;
81
82 /*
83 * VLB I/O addresses
84 */
85 static unsigned int pcnet32_portlist[] =
86 { 0x300, 0x320, 0x340, 0x360, 0 };
87
88 static int pcnet32_debug;
89 static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
90 static int pcnet32vlb; /* check for VLB cards ? */
91
92 static struct net_device *pcnet32_dev;
93
94 static int max_interrupt_work = 2;
95 static int rx_copybreak = 200;
96
97 #define PCNET32_PORT_AUI 0x00
98 #define PCNET32_PORT_10BT 0x01
99 #define PCNET32_PORT_GPSI 0x02
100 #define PCNET32_PORT_MII 0x03
101
102 #define PCNET32_PORT_PORTSEL 0x03
103 #define PCNET32_PORT_ASEL 0x04
104 #define PCNET32_PORT_100 0x40
105 #define PCNET32_PORT_FD 0x80
106
107 #define PCNET32_DMA_MASK 0xffffffff
108
109 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
110 #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
111
112 /*
113 * table to translate option values from tulip
114 * to internal options
115 */
116 static const unsigned char options_mapping[] = {
117 PCNET32_PORT_ASEL, /* 0 Auto-select */
118 PCNET32_PORT_AUI, /* 1 BNC/AUI */
119 PCNET32_PORT_AUI, /* 2 AUI/BNC */
120 PCNET32_PORT_ASEL, /* 3 not supported */
121 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
122 PCNET32_PORT_ASEL, /* 5 not supported */
123 PCNET32_PORT_ASEL, /* 6 not supported */
124 PCNET32_PORT_ASEL, /* 7 not supported */
125 PCNET32_PORT_ASEL, /* 8 not supported */
126 PCNET32_PORT_MII, /* 9 MII 10baseT */
127 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
128 PCNET32_PORT_MII, /* 11 MII (autosel) */
129 PCNET32_PORT_10BT, /* 12 10BaseT */
130 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
131 /* 14 MII 100BaseTx-FD */
132 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
133 PCNET32_PORT_ASEL /* 15 not supported */
134 };
135
136 static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
137 "Loopback test (offline)"
138 };
139
140 #define PCNET32_TEST_LEN ARRAY_SIZE(pcnet32_gstrings_test)
141
142 #define PCNET32_NUM_REGS 136
143
144 #define MAX_UNITS 8 /* More are supported, limit only on options */
145 static int options[MAX_UNITS];
146 static int full_duplex[MAX_UNITS];
147 static int homepna[MAX_UNITS];
148
149 /*
150 * Theory of Operation
151 *
152 * This driver uses the same software structure as the normal lance
153 * driver. So look for a verbose description in lance.c. The differences
154 * to the normal lance driver is the use of the 32bit mode of PCnet32
155 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
156 * 16MB limitation and we don't need bounce buffers.
157 */
158
159 /*
160 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
161 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
162 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
163 */
164 #ifndef PCNET32_LOG_TX_BUFFERS
165 #define PCNET32_LOG_TX_BUFFERS 4
166 #define PCNET32_LOG_RX_BUFFERS 5
167 #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
168 #define PCNET32_LOG_MAX_RX_BUFFERS 9
169 #endif
170
171 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
172 #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
173
174 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
175 #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
176
177 #define PKT_BUF_SKB 1544
178 /* actual buffer length after being aligned */
179 #define PKT_BUF_SIZE (PKT_BUF_SKB - NET_IP_ALIGN)
180 /* chip wants twos complement of the (aligned) buffer length */
181 #define NEG_BUF_SIZE (NET_IP_ALIGN - PKT_BUF_SKB)
182
183 /* Offsets from base I/O address. */
184 #define PCNET32_WIO_RDP 0x10
185 #define PCNET32_WIO_RAP 0x12
186 #define PCNET32_WIO_RESET 0x14
187 #define PCNET32_WIO_BDP 0x16
188
189 #define PCNET32_DWIO_RDP 0x10
190 #define PCNET32_DWIO_RAP 0x14
191 #define PCNET32_DWIO_RESET 0x18
192 #define PCNET32_DWIO_BDP 0x1C
193
194 #define PCNET32_TOTAL_SIZE 0x20
195
196 #define CSR0 0
197 #define CSR0_INIT 0x1
198 #define CSR0_START 0x2
199 #define CSR0_STOP 0x4
200 #define CSR0_TXPOLL 0x8
201 #define CSR0_INTEN 0x40
202 #define CSR0_IDON 0x0100
203 #define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
204 #define PCNET32_INIT_LOW 1
205 #define PCNET32_INIT_HIGH 2
206 #define CSR3 3
207 #define CSR4 4
208 #define CSR5 5
209 #define CSR5_SUSPEND 0x0001
210 #define CSR15 15
211 #define PCNET32_MC_FILTER 8
212
213 #define PCNET32_79C970A 0x2621
214
215 /* The PCNET32 Rx and Tx ring descriptors. */
216 struct pcnet32_rx_head {
217 __le32 base;
218 __le16 buf_length; /* two`s complement of length */
219 __le16 status;
220 __le32 msg_length;
221 __le32 reserved;
222 };
223
224 struct pcnet32_tx_head {
225 __le32 base;
226 __le16 length; /* two`s complement of length */
227 __le16 status;
228 __le32 misc;
229 __le32 reserved;
230 };
231
232 /* The PCNET32 32-Bit initialization block, described in databook. */
233 struct pcnet32_init_block {
234 __le16 mode;
235 __le16 tlen_rlen;
236 u8 phys_addr[6];
237 __le16 reserved;
238 __le32 filter[2];
239 /* Receive and transmit ring base, along with extra bits. */
240 __le32 rx_ring;
241 __le32 tx_ring;
242 };
243
244 /* PCnet32 access functions */
245 struct pcnet32_access {
246 u16 (*read_csr) (unsigned long, int);
247 void (*write_csr) (unsigned long, int, u16);
248 u16 (*read_bcr) (unsigned long, int);
249 void (*write_bcr) (unsigned long, int, u16);
250 u16 (*read_rap) (unsigned long);
251 void (*write_rap) (unsigned long, u16);
252 void (*reset) (unsigned long);
253 };
254
255 /*
256 * The first field of pcnet32_private is read by the ethernet device
257 * so the structure should be allocated using pci_alloc_consistent().
258 */
259 struct pcnet32_private {
260 struct pcnet32_init_block *init_block;
261 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
262 struct pcnet32_rx_head *rx_ring;
263 struct pcnet32_tx_head *tx_ring;
264 dma_addr_t init_dma_addr;/* DMA address of beginning of the init block,
265 returned by pci_alloc_consistent */
266 struct pci_dev *pci_dev;
267 const char *name;
268 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
269 struct sk_buff **tx_skbuff;
270 struct sk_buff **rx_skbuff;
271 dma_addr_t *tx_dma_addr;
272 dma_addr_t *rx_dma_addr;
273 const struct pcnet32_access *a;
274 spinlock_t lock; /* Guard lock */
275 unsigned int cur_rx, cur_tx; /* The next free ring entry */
276 unsigned int rx_ring_size; /* current rx ring size */
277 unsigned int tx_ring_size; /* current tx ring size */
278 unsigned int rx_mod_mask; /* rx ring modular mask */
279 unsigned int tx_mod_mask; /* tx ring modular mask */
280 unsigned short rx_len_bits;
281 unsigned short tx_len_bits;
282 dma_addr_t rx_ring_dma_addr;
283 dma_addr_t tx_ring_dma_addr;
284 unsigned int dirty_rx, /* ring entries to be freed. */
285 dirty_tx;
286
287 struct net_device *dev;
288 struct napi_struct napi;
289 char tx_full;
290 char phycount; /* number of phys found */
291 int options;
292 unsigned int shared_irq:1, /* shared irq possible */
293 dxsuflo:1, /* disable transmit stop on uflo */
294 mii:1; /* mii port available */
295 struct net_device *next;
296 struct mii_if_info mii_if;
297 struct timer_list watchdog_timer;
298 u32 msg_enable; /* debug message level */
299
300 /* each bit indicates an available PHY */
301 u32 phymask;
302 unsigned short chip_version; /* which variant this is */
303
304 /* saved registers during ethtool blink */
305 u16 save_regs[4];
306 };
307
308 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
309 static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
310 static int pcnet32_open(struct net_device *);
311 static int pcnet32_init_ring(struct net_device *);
312 static netdev_tx_t pcnet32_start_xmit(struct sk_buff *,
313 struct net_device *);
314 static void pcnet32_tx_timeout(struct net_device *dev);
315 static irqreturn_t pcnet32_interrupt(int, void *);
316 static int pcnet32_close(struct net_device *);
317 static struct net_device_stats *pcnet32_get_stats(struct net_device *);
318 static void pcnet32_load_multicast(struct net_device *dev);
319 static void pcnet32_set_multicast_list(struct net_device *);
320 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
321 static void pcnet32_watchdog(struct net_device *);
322 static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
323 static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
324 int val);
325 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
326 static void pcnet32_ethtool_test(struct net_device *dev,
327 struct ethtool_test *eth_test, u64 * data);
328 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
329 static int pcnet32_get_regs_len(struct net_device *dev);
330 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
331 void *ptr);
332 static void pcnet32_purge_tx_ring(struct net_device *dev);
333 static int pcnet32_alloc_ring(struct net_device *dev, const char *name);
334 static void pcnet32_free_ring(struct net_device *dev);
335 static void pcnet32_check_media(struct net_device *dev, int verbose);
336
337 static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
338 {
339 outw(index, addr + PCNET32_WIO_RAP);
340 return inw(addr + PCNET32_WIO_RDP);
341 }
342
343 static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
344 {
345 outw(index, addr + PCNET32_WIO_RAP);
346 outw(val, addr + PCNET32_WIO_RDP);
347 }
348
349 static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
350 {
351 outw(index, addr + PCNET32_WIO_RAP);
352 return inw(addr + PCNET32_WIO_BDP);
353 }
354
355 static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
356 {
357 outw(index, addr + PCNET32_WIO_RAP);
358 outw(val, addr + PCNET32_WIO_BDP);
359 }
360
361 static u16 pcnet32_wio_read_rap(unsigned long addr)
362 {
363 return inw(addr + PCNET32_WIO_RAP);
364 }
365
366 static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
367 {
368 outw(val, addr + PCNET32_WIO_RAP);
369 }
370
371 static void pcnet32_wio_reset(unsigned long addr)
372 {
373 inw(addr + PCNET32_WIO_RESET);
374 }
375
376 static int pcnet32_wio_check(unsigned long addr)
377 {
378 outw(88, addr + PCNET32_WIO_RAP);
379 return inw(addr + PCNET32_WIO_RAP) == 88;
380 }
381
382 static const struct pcnet32_access pcnet32_wio = {
383 .read_csr = pcnet32_wio_read_csr,
384 .write_csr = pcnet32_wio_write_csr,
385 .read_bcr = pcnet32_wio_read_bcr,
386 .write_bcr = pcnet32_wio_write_bcr,
387 .read_rap = pcnet32_wio_read_rap,
388 .write_rap = pcnet32_wio_write_rap,
389 .reset = pcnet32_wio_reset
390 };
391
392 static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
393 {
394 outl(index, addr + PCNET32_DWIO_RAP);
395 return inl(addr + PCNET32_DWIO_RDP) & 0xffff;
396 }
397
398 static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
399 {
400 outl(index, addr + PCNET32_DWIO_RAP);
401 outl(val, addr + PCNET32_DWIO_RDP);
402 }
403
404 static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
405 {
406 outl(index, addr + PCNET32_DWIO_RAP);
407 return inl(addr + PCNET32_DWIO_BDP) & 0xffff;
408 }
409
410 static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
411 {
412 outl(index, addr + PCNET32_DWIO_RAP);
413 outl(val, addr + PCNET32_DWIO_BDP);
414 }
415
416 static u16 pcnet32_dwio_read_rap(unsigned long addr)
417 {
418 return inl(addr + PCNET32_DWIO_RAP) & 0xffff;
419 }
420
421 static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
422 {
423 outl(val, addr + PCNET32_DWIO_RAP);
424 }
425
426 static void pcnet32_dwio_reset(unsigned long addr)
427 {
428 inl(addr + PCNET32_DWIO_RESET);
429 }
430
431 static int pcnet32_dwio_check(unsigned long addr)
432 {
433 outl(88, addr + PCNET32_DWIO_RAP);
434 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88;
435 }
436
437 static const struct pcnet32_access pcnet32_dwio = {
438 .read_csr = pcnet32_dwio_read_csr,
439 .write_csr = pcnet32_dwio_write_csr,
440 .read_bcr = pcnet32_dwio_read_bcr,
441 .write_bcr = pcnet32_dwio_write_bcr,
442 .read_rap = pcnet32_dwio_read_rap,
443 .write_rap = pcnet32_dwio_write_rap,
444 .reset = pcnet32_dwio_reset
445 };
446
447 static void pcnet32_netif_stop(struct net_device *dev)
448 {
449 struct pcnet32_private *lp = netdev_priv(dev);
450
451 dev->trans_start = jiffies; /* prevent tx timeout */
452 napi_disable(&lp->napi);
453 netif_tx_disable(dev);
454 }
455
456 static void pcnet32_netif_start(struct net_device *dev)
457 {
458 struct pcnet32_private *lp = netdev_priv(dev);
459 ulong ioaddr = dev->base_addr;
460 u16 val;
461
462 netif_wake_queue(dev);
463 val = lp->a->read_csr(ioaddr, CSR3);
464 val &= 0x00ff;
465 lp->a->write_csr(ioaddr, CSR3, val);
466 napi_enable(&lp->napi);
467 }
468
469 /*
470 * Allocate space for the new sized tx ring.
471 * Free old resources
472 * Save new resources.
473 * Any failure keeps old resources.
474 * Must be called with lp->lock held.
475 */
476 static void pcnet32_realloc_tx_ring(struct net_device *dev,
477 struct pcnet32_private *lp,
478 unsigned int size)
479 {
480 dma_addr_t new_ring_dma_addr;
481 dma_addr_t *new_dma_addr_list;
482 struct pcnet32_tx_head *new_tx_ring;
483 struct sk_buff **new_skb_list;
484
485 pcnet32_purge_tx_ring(dev);
486
487 new_tx_ring = pci_alloc_consistent(lp->pci_dev,
488 sizeof(struct pcnet32_tx_head) *
489 (1 << size),
490 &new_ring_dma_addr);
491 if (new_tx_ring == NULL) {
492 netif_err(lp, drv, dev, "Consistent memory allocation failed\n");
493 return;
494 }
495 memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size));
496
497 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
498 GFP_ATOMIC);
499 if (!new_dma_addr_list) {
500 netif_err(lp, drv, dev, "Memory allocation failed\n");
501 goto free_new_tx_ring;
502 }
503
504 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
505 GFP_ATOMIC);
506 if (!new_skb_list) {
507 netif_err(lp, drv, dev, "Memory allocation failed\n");
508 goto free_new_lists;
509 }
510
511 kfree(lp->tx_skbuff);
512 kfree(lp->tx_dma_addr);
513 pci_free_consistent(lp->pci_dev,
514 sizeof(struct pcnet32_tx_head) *
515 lp->tx_ring_size, lp->tx_ring,
516 lp->tx_ring_dma_addr);
517
518 lp->tx_ring_size = (1 << size);
519 lp->tx_mod_mask = lp->tx_ring_size - 1;
520 lp->tx_len_bits = (size << 12);
521 lp->tx_ring = new_tx_ring;
522 lp->tx_ring_dma_addr = new_ring_dma_addr;
523 lp->tx_dma_addr = new_dma_addr_list;
524 lp->tx_skbuff = new_skb_list;
525 return;
526
527 free_new_lists:
528 kfree(new_dma_addr_list);
529 free_new_tx_ring:
530 pci_free_consistent(lp->pci_dev,
531 sizeof(struct pcnet32_tx_head) *
532 (1 << size),
533 new_tx_ring,
534 new_ring_dma_addr);
535 }
536
537 /*
538 * Allocate space for the new sized rx ring.
539 * Re-use old receive buffers.
540 * alloc extra buffers
541 * free unneeded buffers
542 * free unneeded buffers
543 * Save new resources.
544 * Any failure keeps old resources.
545 * Must be called with lp->lock held.
546 */
547 static void pcnet32_realloc_rx_ring(struct net_device *dev,
548 struct pcnet32_private *lp,
549 unsigned int size)
550 {
551 dma_addr_t new_ring_dma_addr;
552 dma_addr_t *new_dma_addr_list;
553 struct pcnet32_rx_head *new_rx_ring;
554 struct sk_buff **new_skb_list;
555 int new, overlap;
556
557 new_rx_ring = pci_alloc_consistent(lp->pci_dev,
558 sizeof(struct pcnet32_rx_head) *
559 (1 << size),
560 &new_ring_dma_addr);
561 if (new_rx_ring == NULL) {
562 netif_err(lp, drv, dev, "Consistent memory allocation failed\n");
563 return;
564 }
565 memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size));
566
567 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
568 GFP_ATOMIC);
569 if (!new_dma_addr_list) {
570 netif_err(lp, drv, dev, "Memory allocation failed\n");
571 goto free_new_rx_ring;
572 }
573
574 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
575 GFP_ATOMIC);
576 if (!new_skb_list) {
577 netif_err(lp, drv, dev, "Memory allocation failed\n");
578 goto free_new_lists;
579 }
580
581 /* first copy the current receive buffers */
582 overlap = min(size, lp->rx_ring_size);
583 for (new = 0; new < overlap; new++) {
584 new_rx_ring[new] = lp->rx_ring[new];
585 new_dma_addr_list[new] = lp->rx_dma_addr[new];
586 new_skb_list[new] = lp->rx_skbuff[new];
587 }
588 /* now allocate any new buffers needed */
589 for (; new < size; new++) {
590 struct sk_buff *rx_skbuff;
591 new_skb_list[new] = dev_alloc_skb(PKT_BUF_SKB);
592 rx_skbuff = new_skb_list[new];
593 if (!rx_skbuff) {
594 /* keep the original lists and buffers */
595 netif_err(lp, drv, dev, "%s dev_alloc_skb failed\n",
596 __func__);
597 goto free_all_new;
598 }
599 skb_reserve(rx_skbuff, NET_IP_ALIGN);
600
601 new_dma_addr_list[new] =
602 pci_map_single(lp->pci_dev, rx_skbuff->data,
603 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
604 new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]);
605 new_rx_ring[new].buf_length = cpu_to_le16(NEG_BUF_SIZE);
606 new_rx_ring[new].status = cpu_to_le16(0x8000);
607 }
608 /* and free any unneeded buffers */
609 for (; new < lp->rx_ring_size; new++) {
610 if (lp->rx_skbuff[new]) {
611 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new],
612 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
613 dev_kfree_skb(lp->rx_skbuff[new]);
614 }
615 }
616
617 kfree(lp->rx_skbuff);
618 kfree(lp->rx_dma_addr);
619 pci_free_consistent(lp->pci_dev,
620 sizeof(struct pcnet32_rx_head) *
621 lp->rx_ring_size, lp->rx_ring,
622 lp->rx_ring_dma_addr);
623
624 lp->rx_ring_size = (1 << size);
625 lp->rx_mod_mask = lp->rx_ring_size - 1;
626 lp->rx_len_bits = (size << 4);
627 lp->rx_ring = new_rx_ring;
628 lp->rx_ring_dma_addr = new_ring_dma_addr;
629 lp->rx_dma_addr = new_dma_addr_list;
630 lp->rx_skbuff = new_skb_list;
631 return;
632
633 free_all_new:
634 while (--new >= lp->rx_ring_size) {
635 if (new_skb_list[new]) {
636 pci_unmap_single(lp->pci_dev, new_dma_addr_list[new],
637 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
638 dev_kfree_skb(new_skb_list[new]);
639 }
640 }
641 kfree(new_skb_list);
642 free_new_lists:
643 kfree(new_dma_addr_list);
644 free_new_rx_ring:
645 pci_free_consistent(lp->pci_dev,
646 sizeof(struct pcnet32_rx_head) *
647 (1 << size),
648 new_rx_ring,
649 new_ring_dma_addr);
650 }
651
652 static void pcnet32_purge_rx_ring(struct net_device *dev)
653 {
654 struct pcnet32_private *lp = netdev_priv(dev);
655 int i;
656
657 /* free all allocated skbuffs */
658 for (i = 0; i < lp->rx_ring_size; i++) {
659 lp->rx_ring[i].status = 0; /* CPU owns buffer */
660 wmb(); /* Make sure adapter sees owner change */
661 if (lp->rx_skbuff[i]) {
662 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
663 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
664 dev_kfree_skb_any(lp->rx_skbuff[i]);
665 }
666 lp->rx_skbuff[i] = NULL;
667 lp->rx_dma_addr[i] = 0;
668 }
669 }
670
671 #ifdef CONFIG_NET_POLL_CONTROLLER
672 static void pcnet32_poll_controller(struct net_device *dev)
673 {
674 disable_irq(dev->irq);
675 pcnet32_interrupt(0, dev);
676 enable_irq(dev->irq);
677 }
678 #endif
679
680 static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
681 {
682 struct pcnet32_private *lp = netdev_priv(dev);
683 unsigned long flags;
684 int r = -EOPNOTSUPP;
685
686 if (lp->mii) {
687 spin_lock_irqsave(&lp->lock, flags);
688 mii_ethtool_gset(&lp->mii_if, cmd);
689 spin_unlock_irqrestore(&lp->lock, flags);
690 r = 0;
691 }
692 return r;
693 }
694
695 static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
696 {
697 struct pcnet32_private *lp = netdev_priv(dev);
698 unsigned long flags;
699 int r = -EOPNOTSUPP;
700
701 if (lp->mii) {
702 spin_lock_irqsave(&lp->lock, flags);
703 r = mii_ethtool_sset(&lp->mii_if, cmd);
704 spin_unlock_irqrestore(&lp->lock, flags);
705 }
706 return r;
707 }
708
709 static void pcnet32_get_drvinfo(struct net_device *dev,
710 struct ethtool_drvinfo *info)
711 {
712 struct pcnet32_private *lp = netdev_priv(dev);
713
714 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
715 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
716 if (lp->pci_dev)
717 strlcpy(info->bus_info, pci_name(lp->pci_dev),
718 sizeof(info->bus_info));
719 else
720 snprintf(info->bus_info, sizeof(info->bus_info),
721 "VLB 0x%lx", dev->base_addr);
722 }
723
724 static u32 pcnet32_get_link(struct net_device *dev)
725 {
726 struct pcnet32_private *lp = netdev_priv(dev);
727 unsigned long flags;
728 int r;
729
730 spin_lock_irqsave(&lp->lock, flags);
731 if (lp->mii) {
732 r = mii_link_ok(&lp->mii_if);
733 } else if (lp->chip_version >= PCNET32_79C970A) {
734 ulong ioaddr = dev->base_addr; /* card base I/O address */
735 r = (lp->a->read_bcr(ioaddr, 4) != 0xc0);
736 } else { /* can not detect link on really old chips */
737 r = 1;
738 }
739 spin_unlock_irqrestore(&lp->lock, flags);
740
741 return r;
742 }
743
744 static u32 pcnet32_get_msglevel(struct net_device *dev)
745 {
746 struct pcnet32_private *lp = netdev_priv(dev);
747 return lp->msg_enable;
748 }
749
750 static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
751 {
752 struct pcnet32_private *lp = netdev_priv(dev);
753 lp->msg_enable = value;
754 }
755
756 static int pcnet32_nway_reset(struct net_device *dev)
757 {
758 struct pcnet32_private *lp = netdev_priv(dev);
759 unsigned long flags;
760 int r = -EOPNOTSUPP;
761
762 if (lp->mii) {
763 spin_lock_irqsave(&lp->lock, flags);
764 r = mii_nway_restart(&lp->mii_if);
765 spin_unlock_irqrestore(&lp->lock, flags);
766 }
767 return r;
768 }
769
770 static void pcnet32_get_ringparam(struct net_device *dev,
771 struct ethtool_ringparam *ering)
772 {
773 struct pcnet32_private *lp = netdev_priv(dev);
774
775 ering->tx_max_pending = TX_MAX_RING_SIZE;
776 ering->tx_pending = lp->tx_ring_size;
777 ering->rx_max_pending = RX_MAX_RING_SIZE;
778 ering->rx_pending = lp->rx_ring_size;
779 }
780
781 static int pcnet32_set_ringparam(struct net_device *dev,
782 struct ethtool_ringparam *ering)
783 {
784 struct pcnet32_private *lp = netdev_priv(dev);
785 unsigned long flags;
786 unsigned int size;
787 ulong ioaddr = dev->base_addr;
788 int i;
789
790 if (ering->rx_mini_pending || ering->rx_jumbo_pending)
791 return -EINVAL;
792
793 if (netif_running(dev))
794 pcnet32_netif_stop(dev);
795
796 spin_lock_irqsave(&lp->lock, flags);
797 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
798
799 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
800
801 /* set the minimum ring size to 4, to allow the loopback test to work
802 * unchanged.
803 */
804 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
805 if (size <= (1 << i))
806 break;
807 }
808 if ((1 << i) != lp->tx_ring_size)
809 pcnet32_realloc_tx_ring(dev, lp, i);
810
811 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
812 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
813 if (size <= (1 << i))
814 break;
815 }
816 if ((1 << i) != lp->rx_ring_size)
817 pcnet32_realloc_rx_ring(dev, lp, i);
818
819 lp->napi.weight = lp->rx_ring_size / 2;
820
821 if (netif_running(dev)) {
822 pcnet32_netif_start(dev);
823 pcnet32_restart(dev, CSR0_NORMAL);
824 }
825
826 spin_unlock_irqrestore(&lp->lock, flags);
827
828 netif_info(lp, drv, dev, "Ring Param Settings: RX: %d, TX: %d\n",
829 lp->rx_ring_size, lp->tx_ring_size);
830
831 return 0;
832 }
833
834 static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
835 u8 *data)
836 {
837 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
838 }
839
840 static int pcnet32_get_sset_count(struct net_device *dev, int sset)
841 {
842 switch (sset) {
843 case ETH_SS_TEST:
844 return PCNET32_TEST_LEN;
845 default:
846 return -EOPNOTSUPP;
847 }
848 }
849
850 static void pcnet32_ethtool_test(struct net_device *dev,
851 struct ethtool_test *test, u64 * data)
852 {
853 struct pcnet32_private *lp = netdev_priv(dev);
854 int rc;
855
856 if (test->flags == ETH_TEST_FL_OFFLINE) {
857 rc = pcnet32_loopback_test(dev, data);
858 if (rc) {
859 netif_printk(lp, hw, KERN_DEBUG, dev,
860 "Loopback test failed\n");
861 test->flags |= ETH_TEST_FL_FAILED;
862 } else
863 netif_printk(lp, hw, KERN_DEBUG, dev,
864 "Loopback test passed\n");
865 } else
866 netif_printk(lp, hw, KERN_DEBUG, dev,
867 "No tests to run (specify 'Offline' on ethtool)\n");
868 } /* end pcnet32_ethtool_test */
869
870 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
871 {
872 struct pcnet32_private *lp = netdev_priv(dev);
873 const struct pcnet32_access *a = lp->a; /* access to registers */
874 ulong ioaddr = dev->base_addr; /* card base I/O address */
875 struct sk_buff *skb; /* sk buff */
876 int x, i; /* counters */
877 int numbuffs = 4; /* number of TX/RX buffers and descs */
878 u16 status = 0x8300; /* TX ring status */
879 __le16 teststatus; /* test of ring status */
880 int rc; /* return code */
881 int size; /* size of packets */
882 unsigned char *packet; /* source packet data */
883 static const int data_len = 60; /* length of source packets */
884 unsigned long flags;
885 unsigned long ticks;
886
887 rc = 1; /* default to fail */
888
889 if (netif_running(dev))
890 pcnet32_netif_stop(dev);
891
892 spin_lock_irqsave(&lp->lock, flags);
893 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
894
895 numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
896
897 /* Reset the PCNET32 */
898 lp->a->reset(ioaddr);
899 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
900
901 /* switch pcnet32 to 32bit mode */
902 lp->a->write_bcr(ioaddr, 20, 2);
903
904 /* purge & init rings but don't actually restart */
905 pcnet32_restart(dev, 0x0000);
906
907 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
908
909 /* Initialize Transmit buffers. */
910 size = data_len + 15;
911 for (x = 0; x < numbuffs; x++) {
912 skb = dev_alloc_skb(size);
913 if (!skb) {
914 netif_printk(lp, hw, KERN_DEBUG, dev,
915 "Cannot allocate skb at line: %d!\n",
916 __LINE__);
917 goto clean_up;
918 }
919 packet = skb->data;
920 skb_put(skb, size); /* create space for data */
921 lp->tx_skbuff[x] = skb;
922 lp->tx_ring[x].length = cpu_to_le16(-skb->len);
923 lp->tx_ring[x].misc = 0;
924
925 /* put DA and SA into the skb */
926 for (i = 0; i < 6; i++)
927 *packet++ = dev->dev_addr[i];
928 for (i = 0; i < 6; i++)
929 *packet++ = dev->dev_addr[i];
930 /* type */
931 *packet++ = 0x08;
932 *packet++ = 0x06;
933 /* packet number */
934 *packet++ = x;
935 /* fill packet with data */
936 for (i = 0; i < data_len; i++)
937 *packet++ = i;
938
939 lp->tx_dma_addr[x] =
940 pci_map_single(lp->pci_dev, skb->data, skb->len,
941 PCI_DMA_TODEVICE);
942 lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]);
943 wmb(); /* Make sure owner changes after all others are visible */
944 lp->tx_ring[x].status = cpu_to_le16(status);
945 }
946
947 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */
948 a->write_bcr(ioaddr, 32, x | 0x0002);
949
950 /* set int loopback in CSR15 */
951 x = a->read_csr(ioaddr, CSR15) & 0xfffc;
952 lp->a->write_csr(ioaddr, CSR15, x | 0x0044);
953
954 teststatus = cpu_to_le16(0x8000);
955 lp->a->write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */
956
957 /* Check status of descriptors */
958 for (x = 0; x < numbuffs; x++) {
959 ticks = 0;
960 rmb();
961 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
962 spin_unlock_irqrestore(&lp->lock, flags);
963 msleep(1);
964 spin_lock_irqsave(&lp->lock, flags);
965 rmb();
966 ticks++;
967 }
968 if (ticks == 200) {
969 netif_err(lp, hw, dev, "Desc %d failed to reset!\n", x);
970 break;
971 }
972 }
973
974 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
975 wmb();
976 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
977 netdev_printk(KERN_DEBUG, dev, "RX loopback packets:\n");
978
979 for (x = 0; x < numbuffs; x++) {
980 netdev_printk(KERN_DEBUG, dev, "Packet %d: ", x);
981 skb = lp->rx_skbuff[x];
982 for (i = 0; i < size; i++)
983 pr_cont(" %02x", *(skb->data + i));
984 pr_cont("\n");
985 }
986 }
987
988 x = 0;
989 rc = 0;
990 while (x < numbuffs && !rc) {
991 skb = lp->rx_skbuff[x];
992 packet = lp->tx_skbuff[x]->data;
993 for (i = 0; i < size; i++) {
994 if (*(skb->data + i) != packet[i]) {
995 netif_printk(lp, hw, KERN_DEBUG, dev,
996 "Error in compare! %2x - %02x %02x\n",
997 i, *(skb->data + i), packet[i]);
998 rc = 1;
999 break;
1000 }
1001 }
1002 x++;
1003 }
1004
1005 clean_up:
1006 *data1 = rc;
1007 pcnet32_purge_tx_ring(dev);
1008
1009 x = a->read_csr(ioaddr, CSR15);
1010 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */
1011
1012 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
1013 a->write_bcr(ioaddr, 32, (x & ~0x0002));
1014
1015 if (netif_running(dev)) {
1016 pcnet32_netif_start(dev);
1017 pcnet32_restart(dev, CSR0_NORMAL);
1018 } else {
1019 pcnet32_purge_rx_ring(dev);
1020 lp->a->write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1021 }
1022 spin_unlock_irqrestore(&lp->lock, flags);
1023
1024 return rc;
1025 } /* end pcnet32_loopback_test */
1026
1027 static int pcnet32_set_phys_id(struct net_device *dev,
1028 enum ethtool_phys_id_state state)
1029 {
1030 struct pcnet32_private *lp = netdev_priv(dev);
1031 const struct pcnet32_access *a = lp->a;
1032 ulong ioaddr = dev->base_addr;
1033 unsigned long flags;
1034 int i;
1035
1036 switch (state) {
1037 case ETHTOOL_ID_ACTIVE:
1038 /* Save the current value of the bcrs */
1039 spin_lock_irqsave(&lp->lock, flags);
1040 for (i = 4; i < 8; i++)
1041 lp->save_regs[i - 4] = a->read_bcr(ioaddr, i);
1042 spin_unlock_irqrestore(&lp->lock, flags);
1043 return 2; /* cycle on/off twice per second */
1044
1045 case ETHTOOL_ID_ON:
1046 case ETHTOOL_ID_OFF:
1047 /* Blink the led */
1048 spin_lock_irqsave(&lp->lock, flags);
1049 for (i = 4; i < 8; i++)
1050 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1051 spin_unlock_irqrestore(&lp->lock, flags);
1052 break;
1053
1054 case ETHTOOL_ID_INACTIVE:
1055 /* Restore the original value of the bcrs */
1056 spin_lock_irqsave(&lp->lock, flags);
1057 for (i = 4; i < 8; i++)
1058 a->write_bcr(ioaddr, i, lp->save_regs[i - 4]);
1059 spin_unlock_irqrestore(&lp->lock, flags);
1060 }
1061 return 0;
1062 }
1063
1064 /*
1065 * lp->lock must be held.
1066 */
1067 static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
1068 int can_sleep)
1069 {
1070 int csr5;
1071 struct pcnet32_private *lp = netdev_priv(dev);
1072 const struct pcnet32_access *a = lp->a;
1073 ulong ioaddr = dev->base_addr;
1074 int ticks;
1075
1076 /* really old chips have to be stopped. */
1077 if (lp->chip_version < PCNET32_79C970A)
1078 return 0;
1079
1080 /* set SUSPEND (SPND) - CSR5 bit 0 */
1081 csr5 = a->read_csr(ioaddr, CSR5);
1082 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
1083
1084 /* poll waiting for bit to be set */
1085 ticks = 0;
1086 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
1087 spin_unlock_irqrestore(&lp->lock, *flags);
1088 if (can_sleep)
1089 msleep(1);
1090 else
1091 mdelay(1);
1092 spin_lock_irqsave(&lp->lock, *flags);
1093 ticks++;
1094 if (ticks > 200) {
1095 netif_printk(lp, hw, KERN_DEBUG, dev,
1096 "Error getting into suspend!\n");
1097 return 0;
1098 }
1099 }
1100 return 1;
1101 }
1102
1103 /*
1104 * process one receive descriptor entry
1105 */
1106
1107 static void pcnet32_rx_entry(struct net_device *dev,
1108 struct pcnet32_private *lp,
1109 struct pcnet32_rx_head *rxp,
1110 int entry)
1111 {
1112 int status = (short)le16_to_cpu(rxp->status) >> 8;
1113 int rx_in_place = 0;
1114 struct sk_buff *skb;
1115 short pkt_len;
1116
1117 if (status != 0x03) { /* There was an error. */
1118 /*
1119 * There is a tricky error noted by John Murphy,
1120 * <murf@perftech.com> to Russ Nelson: Even with full-sized
1121 * buffers it's possible for a jabber packet to use two
1122 * buffers, with only the last correctly noting the error.
1123 */
1124 if (status & 0x01) /* Only count a general error at the */
1125 dev->stats.rx_errors++; /* end of a packet. */
1126 if (status & 0x20)
1127 dev->stats.rx_frame_errors++;
1128 if (status & 0x10)
1129 dev->stats.rx_over_errors++;
1130 if (status & 0x08)
1131 dev->stats.rx_crc_errors++;
1132 if (status & 0x04)
1133 dev->stats.rx_fifo_errors++;
1134 return;
1135 }
1136
1137 pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
1138
1139 /* Discard oversize frames. */
1140 if (unlikely(pkt_len > PKT_BUF_SIZE)) {
1141 netif_err(lp, drv, dev, "Impossible packet size %d!\n",
1142 pkt_len);
1143 dev->stats.rx_errors++;
1144 return;
1145 }
1146 if (pkt_len < 60) {
1147 netif_err(lp, rx_err, dev, "Runt packet!\n");
1148 dev->stats.rx_errors++;
1149 return;
1150 }
1151
1152 if (pkt_len > rx_copybreak) {
1153 struct sk_buff *newskb;
1154
1155 newskb = dev_alloc_skb(PKT_BUF_SKB);
1156 if (newskb) {
1157 skb_reserve(newskb, NET_IP_ALIGN);
1158 skb = lp->rx_skbuff[entry];
1159 pci_unmap_single(lp->pci_dev,
1160 lp->rx_dma_addr[entry],
1161 PKT_BUF_SIZE,
1162 PCI_DMA_FROMDEVICE);
1163 skb_put(skb, pkt_len);
1164 lp->rx_skbuff[entry] = newskb;
1165 lp->rx_dma_addr[entry] =
1166 pci_map_single(lp->pci_dev,
1167 newskb->data,
1168 PKT_BUF_SIZE,
1169 PCI_DMA_FROMDEVICE);
1170 rxp->base = cpu_to_le32(lp->rx_dma_addr[entry]);
1171 rx_in_place = 1;
1172 } else
1173 skb = NULL;
1174 } else
1175 skb = dev_alloc_skb(pkt_len + NET_IP_ALIGN);
1176
1177 if (skb == NULL) {
1178 netif_err(lp, drv, dev, "Memory squeeze, dropping packet\n");
1179 dev->stats.rx_dropped++;
1180 return;
1181 }
1182 if (!rx_in_place) {
1183 skb_reserve(skb, NET_IP_ALIGN);
1184 skb_put(skb, pkt_len); /* Make room */
1185 pci_dma_sync_single_for_cpu(lp->pci_dev,
1186 lp->rx_dma_addr[entry],
1187 pkt_len,
1188 PCI_DMA_FROMDEVICE);
1189 skb_copy_to_linear_data(skb,
1190 (unsigned char *)(lp->rx_skbuff[entry]->data),
1191 pkt_len);
1192 pci_dma_sync_single_for_device(lp->pci_dev,
1193 lp->rx_dma_addr[entry],
1194 pkt_len,
1195 PCI_DMA_FROMDEVICE);
1196 }
1197 dev->stats.rx_bytes += skb->len;
1198 skb->protocol = eth_type_trans(skb, dev);
1199 netif_receive_skb(skb);
1200 dev->stats.rx_packets++;
1201 }
1202
1203 static int pcnet32_rx(struct net_device *dev, int budget)
1204 {
1205 struct pcnet32_private *lp = netdev_priv(dev);
1206 int entry = lp->cur_rx & lp->rx_mod_mask;
1207 struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
1208 int npackets = 0;
1209
1210 /* If we own the next entry, it's a new packet. Send it up. */
1211 while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) {
1212 pcnet32_rx_entry(dev, lp, rxp, entry);
1213 npackets += 1;
1214 /*
1215 * The docs say that the buffer length isn't touched, but Andrew
1216 * Boyd of QNX reports that some revs of the 79C965 clear it.
1217 */
1218 rxp->buf_length = cpu_to_le16(NEG_BUF_SIZE);
1219 wmb(); /* Make sure owner changes after others are visible */
1220 rxp->status = cpu_to_le16(0x8000);
1221 entry = (++lp->cur_rx) & lp->rx_mod_mask;
1222 rxp = &lp->rx_ring[entry];
1223 }
1224
1225 return npackets;
1226 }
1227
1228 static int pcnet32_tx(struct net_device *dev)
1229 {
1230 struct pcnet32_private *lp = netdev_priv(dev);
1231 unsigned int dirty_tx = lp->dirty_tx;
1232 int delta;
1233 int must_restart = 0;
1234
1235 while (dirty_tx != lp->cur_tx) {
1236 int entry = dirty_tx & lp->tx_mod_mask;
1237 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1238
1239 if (status < 0)
1240 break; /* It still hasn't been Txed */
1241
1242 lp->tx_ring[entry].base = 0;
1243
1244 if (status & 0x4000) {
1245 /* There was a major error, log it. */
1246 int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1247 dev->stats.tx_errors++;
1248 netif_err(lp, tx_err, dev,
1249 "Tx error status=%04x err_status=%08x\n",
1250 status, err_status);
1251 if (err_status & 0x04000000)
1252 dev->stats.tx_aborted_errors++;
1253 if (err_status & 0x08000000)
1254 dev->stats.tx_carrier_errors++;
1255 if (err_status & 0x10000000)
1256 dev->stats.tx_window_errors++;
1257 #ifndef DO_DXSUFLO
1258 if (err_status & 0x40000000) {
1259 dev->stats.tx_fifo_errors++;
1260 /* Ackk! On FIFO errors the Tx unit is turned off! */
1261 /* Remove this verbosity later! */
1262 netif_err(lp, tx_err, dev, "Tx FIFO error!\n");
1263 must_restart = 1;
1264 }
1265 #else
1266 if (err_status & 0x40000000) {
1267 dev->stats.tx_fifo_errors++;
1268 if (!lp->dxsuflo) { /* If controller doesn't recover ... */
1269 /* Ackk! On FIFO errors the Tx unit is turned off! */
1270 /* Remove this verbosity later! */
1271 netif_err(lp, tx_err, dev, "Tx FIFO error!\n");
1272 must_restart = 1;
1273 }
1274 }
1275 #endif
1276 } else {
1277 if (status & 0x1800)
1278 dev->stats.collisions++;
1279 dev->stats.tx_packets++;
1280 }
1281
1282 /* We must free the original skb */
1283 if (lp->tx_skbuff[entry]) {
1284 pci_unmap_single(lp->pci_dev,
1285 lp->tx_dma_addr[entry],
1286 lp->tx_skbuff[entry]->
1287 len, PCI_DMA_TODEVICE);
1288 dev_kfree_skb_any(lp->tx_skbuff[entry]);
1289 lp->tx_skbuff[entry] = NULL;
1290 lp->tx_dma_addr[entry] = 0;
1291 }
1292 dirty_tx++;
1293 }
1294
1295 delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
1296 if (delta > lp->tx_ring_size) {
1297 netif_err(lp, drv, dev, "out-of-sync dirty pointer, %d vs. %d, full=%d\n",
1298 dirty_tx, lp->cur_tx, lp->tx_full);
1299 dirty_tx += lp->tx_ring_size;
1300 delta -= lp->tx_ring_size;
1301 }
1302
1303 if (lp->tx_full &&
1304 netif_queue_stopped(dev) &&
1305 delta < lp->tx_ring_size - 2) {
1306 /* The ring is no longer full, clear tbusy. */
1307 lp->tx_full = 0;
1308 netif_wake_queue(dev);
1309 }
1310 lp->dirty_tx = dirty_tx;
1311
1312 return must_restart;
1313 }
1314
1315 static int pcnet32_poll(struct napi_struct *napi, int budget)
1316 {
1317 struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi);
1318 struct net_device *dev = lp->dev;
1319 unsigned long ioaddr = dev->base_addr;
1320 unsigned long flags;
1321 int work_done;
1322 u16 val;
1323
1324 work_done = pcnet32_rx(dev, budget);
1325
1326 spin_lock_irqsave(&lp->lock, flags);
1327 if (pcnet32_tx(dev)) {
1328 /* reset the chip to clear the error condition, then restart */
1329 lp->a->reset(ioaddr);
1330 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
1331 pcnet32_restart(dev, CSR0_START);
1332 netif_wake_queue(dev);
1333 }
1334 spin_unlock_irqrestore(&lp->lock, flags);
1335
1336 if (work_done < budget) {
1337 spin_lock_irqsave(&lp->lock, flags);
1338
1339 __napi_complete(napi);
1340
1341 /* clear interrupt masks */
1342 val = lp->a->read_csr(ioaddr, CSR3);
1343 val &= 0x00ff;
1344 lp->a->write_csr(ioaddr, CSR3, val);
1345
1346 /* Set interrupt enable. */
1347 lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN);
1348
1349 spin_unlock_irqrestore(&lp->lock, flags);
1350 }
1351 return work_done;
1352 }
1353
1354 #define PCNET32_REGS_PER_PHY 32
1355 #define PCNET32_MAX_PHYS 32
1356 static int pcnet32_get_regs_len(struct net_device *dev)
1357 {
1358 struct pcnet32_private *lp = netdev_priv(dev);
1359 int j = lp->phycount * PCNET32_REGS_PER_PHY;
1360
1361 return (PCNET32_NUM_REGS + j) * sizeof(u16);
1362 }
1363
1364 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1365 void *ptr)
1366 {
1367 int i, csr0;
1368 u16 *buff = ptr;
1369 struct pcnet32_private *lp = netdev_priv(dev);
1370 const struct pcnet32_access *a = lp->a;
1371 ulong ioaddr = dev->base_addr;
1372 unsigned long flags;
1373
1374 spin_lock_irqsave(&lp->lock, flags);
1375
1376 csr0 = a->read_csr(ioaddr, CSR0);
1377 if (!(csr0 & CSR0_STOP)) /* If not stopped */
1378 pcnet32_suspend(dev, &flags, 1);
1379
1380 /* read address PROM */
1381 for (i = 0; i < 16; i += 2)
1382 *buff++ = inw(ioaddr + i);
1383
1384 /* read control and status registers */
1385 for (i = 0; i < 90; i++)
1386 *buff++ = a->read_csr(ioaddr, i);
1387
1388 *buff++ = a->read_csr(ioaddr, 112);
1389 *buff++ = a->read_csr(ioaddr, 114);
1390
1391 /* read bus configuration registers */
1392 for (i = 0; i < 30; i++)
1393 *buff++ = a->read_bcr(ioaddr, i);
1394
1395 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */
1396
1397 for (i = 31; i < 36; i++)
1398 *buff++ = a->read_bcr(ioaddr, i);
1399
1400 /* read mii phy registers */
1401 if (lp->mii) {
1402 int j;
1403 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1404 if (lp->phymask & (1 << j)) {
1405 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1406 lp->a->write_bcr(ioaddr, 33,
1407 (j << 5) | i);
1408 *buff++ = lp->a->read_bcr(ioaddr, 34);
1409 }
1410 }
1411 }
1412 }
1413
1414 if (!(csr0 & CSR0_STOP)) { /* If not stopped */
1415 int csr5;
1416
1417 /* clear SUSPEND (SPND) - CSR5 bit 0 */
1418 csr5 = a->read_csr(ioaddr, CSR5);
1419 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
1420 }
1421
1422 spin_unlock_irqrestore(&lp->lock, flags);
1423 }
1424
1425 static const struct ethtool_ops pcnet32_ethtool_ops = {
1426 .get_settings = pcnet32_get_settings,
1427 .set_settings = pcnet32_set_settings,
1428 .get_drvinfo = pcnet32_get_drvinfo,
1429 .get_msglevel = pcnet32_get_msglevel,
1430 .set_msglevel = pcnet32_set_msglevel,
1431 .nway_reset = pcnet32_nway_reset,
1432 .get_link = pcnet32_get_link,
1433 .get_ringparam = pcnet32_get_ringparam,
1434 .set_ringparam = pcnet32_set_ringparam,
1435 .get_strings = pcnet32_get_strings,
1436 .self_test = pcnet32_ethtool_test,
1437 .set_phys_id = pcnet32_set_phys_id,
1438 .get_regs_len = pcnet32_get_regs_len,
1439 .get_regs = pcnet32_get_regs,
1440 .get_sset_count = pcnet32_get_sset_count,
1441 };
1442
1443 /* only probes for non-PCI devices, the rest are handled by
1444 * pci_register_driver via pcnet32_probe_pci */
1445
1446 static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1447 {
1448 unsigned int *port, ioaddr;
1449
1450 /* search for PCnet32 VLB cards at known addresses */
1451 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1452 if (request_region
1453 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1454 /* check if there is really a pcnet chip on that ioaddr */
1455 if ((inb(ioaddr + 14) == 0x57) &&
1456 (inb(ioaddr + 15) == 0x57)) {
1457 pcnet32_probe1(ioaddr, 0, NULL);
1458 } else {
1459 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1460 }
1461 }
1462 }
1463 }
1464
1465 static int __devinit
1466 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1467 {
1468 unsigned long ioaddr;
1469 int err;
1470
1471 err = pci_enable_device(pdev);
1472 if (err < 0) {
1473 if (pcnet32_debug & NETIF_MSG_PROBE)
1474 pr_err("failed to enable device -- err=%d\n", err);
1475 return err;
1476 }
1477 pci_set_master(pdev);
1478
1479 ioaddr = pci_resource_start(pdev, 0);
1480 if (!ioaddr) {
1481 if (pcnet32_debug & NETIF_MSG_PROBE)
1482 pr_err("card has no PCI IO resources, aborting\n");
1483 return -ENODEV;
1484 }
1485
1486 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
1487 if (pcnet32_debug & NETIF_MSG_PROBE)
1488 pr_err("architecture does not support 32bit PCI busmaster DMA\n");
1489 return -ENODEV;
1490 }
1491 if (!request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci")) {
1492 if (pcnet32_debug & NETIF_MSG_PROBE)
1493 pr_err("io address range already allocated\n");
1494 return -EBUSY;
1495 }
1496
1497 err = pcnet32_probe1(ioaddr, 1, pdev);
1498 if (err < 0)
1499 pci_disable_device(pdev);
1500
1501 return err;
1502 }
1503
1504 static const struct net_device_ops pcnet32_netdev_ops = {
1505 .ndo_open = pcnet32_open,
1506 .ndo_stop = pcnet32_close,
1507 .ndo_start_xmit = pcnet32_start_xmit,
1508 .ndo_tx_timeout = pcnet32_tx_timeout,
1509 .ndo_get_stats = pcnet32_get_stats,
1510 .ndo_set_rx_mode = pcnet32_set_multicast_list,
1511 .ndo_do_ioctl = pcnet32_ioctl,
1512 .ndo_change_mtu = eth_change_mtu,
1513 .ndo_set_mac_address = eth_mac_addr,
1514 .ndo_validate_addr = eth_validate_addr,
1515 #ifdef CONFIG_NET_POLL_CONTROLLER
1516 .ndo_poll_controller = pcnet32_poll_controller,
1517 #endif
1518 };
1519
1520 /* pcnet32_probe1
1521 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1522 * pdev will be NULL when called from pcnet32_probe_vlbus.
1523 */
1524 static int __devinit
1525 pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1526 {
1527 struct pcnet32_private *lp;
1528 int i, media;
1529 int fdx, mii, fset, dxsuflo;
1530 int chip_version;
1531 char *chipname;
1532 struct net_device *dev;
1533 const struct pcnet32_access *a = NULL;
1534 u8 promaddr[6];
1535 int ret = -ENODEV;
1536
1537 /* reset the chip */
1538 pcnet32_wio_reset(ioaddr);
1539
1540 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1541 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1542 a = &pcnet32_wio;
1543 } else {
1544 pcnet32_dwio_reset(ioaddr);
1545 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 &&
1546 pcnet32_dwio_check(ioaddr)) {
1547 a = &pcnet32_dwio;
1548 } else {
1549 if (pcnet32_debug & NETIF_MSG_PROBE)
1550 pr_err("No access methods\n");
1551 goto err_release_region;
1552 }
1553 }
1554
1555 chip_version =
1556 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1557 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1558 pr_info(" PCnet chip version is %#x\n", chip_version);
1559 if ((chip_version & 0xfff) != 0x003) {
1560 if (pcnet32_debug & NETIF_MSG_PROBE)
1561 pr_info("Unsupported chip version\n");
1562 goto err_release_region;
1563 }
1564
1565 /* initialize variables */
1566 fdx = mii = fset = dxsuflo = 0;
1567 chip_version = (chip_version >> 12) & 0xffff;
1568
1569 switch (chip_version) {
1570 case 0x2420:
1571 chipname = "PCnet/PCI 79C970"; /* PCI */
1572 break;
1573 case 0x2430:
1574 if (shared)
1575 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1576 else
1577 chipname = "PCnet/32 79C965"; /* 486/VL bus */
1578 break;
1579 case 0x2621:
1580 chipname = "PCnet/PCI II 79C970A"; /* PCI */
1581 fdx = 1;
1582 break;
1583 case 0x2623:
1584 chipname = "PCnet/FAST 79C971"; /* PCI */
1585 fdx = 1;
1586 mii = 1;
1587 fset = 1;
1588 break;
1589 case 0x2624:
1590 chipname = "PCnet/FAST+ 79C972"; /* PCI */
1591 fdx = 1;
1592 mii = 1;
1593 fset = 1;
1594 break;
1595 case 0x2625:
1596 chipname = "PCnet/FAST III 79C973"; /* PCI */
1597 fdx = 1;
1598 mii = 1;
1599 break;
1600 case 0x2626:
1601 chipname = "PCnet/Home 79C978"; /* PCI */
1602 fdx = 1;
1603 /*
1604 * This is based on specs published at www.amd.com. This section
1605 * assumes that a card with a 79C978 wants to go into standard
1606 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1607 * and the module option homepna=1 can select this instead.
1608 */
1609 media = a->read_bcr(ioaddr, 49);
1610 media &= ~3; /* default to 10Mb ethernet */
1611 if (cards_found < MAX_UNITS && homepna[cards_found])
1612 media |= 1; /* switch to home wiring mode */
1613 if (pcnet32_debug & NETIF_MSG_PROBE)
1614 printk(KERN_DEBUG PFX "media set to %sMbit mode\n",
1615 (media & 1) ? "1" : "10");
1616 a->write_bcr(ioaddr, 49, media);
1617 break;
1618 case 0x2627:
1619 chipname = "PCnet/FAST III 79C975"; /* PCI */
1620 fdx = 1;
1621 mii = 1;
1622 break;
1623 case 0x2628:
1624 chipname = "PCnet/PRO 79C976";
1625 fdx = 1;
1626 mii = 1;
1627 break;
1628 default:
1629 if (pcnet32_debug & NETIF_MSG_PROBE)
1630 pr_info("PCnet version %#x, no PCnet32 chip\n",
1631 chip_version);
1632 goto err_release_region;
1633 }
1634
1635 /*
1636 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1637 * starting until the packet is loaded. Strike one for reliability, lose
1638 * one for latency - although on PCI this isn't a big loss. Older chips
1639 * have FIFO's smaller than a packet, so you can't do this.
1640 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1641 */
1642
1643 if (fset) {
1644 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1645 a->write_csr(ioaddr, 80,
1646 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1647 dxsuflo = 1;
1648 }
1649
1650 dev = alloc_etherdev(sizeof(*lp));
1651 if (!dev) {
1652 if (pcnet32_debug & NETIF_MSG_PROBE)
1653 pr_err("Memory allocation failed\n");
1654 ret = -ENOMEM;
1655 goto err_release_region;
1656 }
1657
1658 if (pdev)
1659 SET_NETDEV_DEV(dev, &pdev->dev);
1660
1661 if (pcnet32_debug & NETIF_MSG_PROBE)
1662 pr_info("%s at %#3lx,", chipname, ioaddr);
1663
1664 /* In most chips, after a chip reset, the ethernet address is read from the
1665 * station address PROM at the base address and programmed into the
1666 * "Physical Address Registers" CSR12-14.
1667 * As a precautionary measure, we read the PROM values and complain if
1668 * they disagree with the CSRs. If they miscompare, and the PROM addr
1669 * is valid, then the PROM addr is used.
1670 */
1671 for (i = 0; i < 3; i++) {
1672 unsigned int val;
1673 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1674 /* There may be endianness issues here. */
1675 dev->dev_addr[2 * i] = val & 0x0ff;
1676 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1677 }
1678
1679 /* read PROM address and compare with CSR address */
1680 for (i = 0; i < 6; i++)
1681 promaddr[i] = inb(ioaddr + i);
1682
1683 if (memcmp(promaddr, dev->dev_addr, 6) ||
1684 !is_valid_ether_addr(dev->dev_addr)) {
1685 if (is_valid_ether_addr(promaddr)) {
1686 if (pcnet32_debug & NETIF_MSG_PROBE) {
1687 pr_cont(" warning: CSR address invalid,\n");
1688 pr_info(" using instead PROM address of");
1689 }
1690 memcpy(dev->dev_addr, promaddr, 6);
1691 }
1692 }
1693 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1694
1695 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1696 if (!is_valid_ether_addr(dev->perm_addr))
1697 memset(dev->dev_addr, 0, ETH_ALEN);
1698
1699 if (pcnet32_debug & NETIF_MSG_PROBE) {
1700 pr_cont(" %pM", dev->dev_addr);
1701
1702 /* Version 0x2623 and 0x2624 */
1703 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1704 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
1705 pr_info(" tx_start_pt(0x%04x):", i);
1706 switch (i >> 10) {
1707 case 0:
1708 pr_cont(" 20 bytes,");
1709 break;
1710 case 1:
1711 pr_cont(" 64 bytes,");
1712 break;
1713 case 2:
1714 pr_cont(" 128 bytes,");
1715 break;
1716 case 3:
1717 pr_cont("~220 bytes,");
1718 break;
1719 }
1720 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
1721 pr_cont(" BCR18(%x):", i & 0xffff);
1722 if (i & (1 << 5))
1723 pr_cont("BurstWrEn ");
1724 if (i & (1 << 6))
1725 pr_cont("BurstRdEn ");
1726 if (i & (1 << 7))
1727 pr_cont("DWordIO ");
1728 if (i & (1 << 11))
1729 pr_cont("NoUFlow ");
1730 i = a->read_bcr(ioaddr, 25);
1731 pr_info(" SRAMSIZE=0x%04x,", i << 8);
1732 i = a->read_bcr(ioaddr, 26);
1733 pr_cont(" SRAM_BND=0x%04x,", i << 8);
1734 i = a->read_bcr(ioaddr, 27);
1735 if (i & (1 << 14))
1736 pr_cont("LowLatRx");
1737 }
1738 }
1739
1740 dev->base_addr = ioaddr;
1741 lp = netdev_priv(dev);
1742 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1743 lp->init_block = pci_alloc_consistent(pdev, sizeof(*lp->init_block),
1744 &lp->init_dma_addr);
1745 if (!lp->init_block) {
1746 if (pcnet32_debug & NETIF_MSG_PROBE)
1747 pr_err("Consistent memory allocation failed\n");
1748 ret = -ENOMEM;
1749 goto err_free_netdev;
1750 }
1751 lp->pci_dev = pdev;
1752
1753 lp->dev = dev;
1754
1755 spin_lock_init(&lp->lock);
1756
1757 lp->name = chipname;
1758 lp->shared_irq = shared;
1759 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */
1760 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */
1761 lp->tx_mod_mask = lp->tx_ring_size - 1;
1762 lp->rx_mod_mask = lp->rx_ring_size - 1;
1763 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1764 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1765 lp->mii_if.full_duplex = fdx;
1766 lp->mii_if.phy_id_mask = 0x1f;
1767 lp->mii_if.reg_num_mask = 0x1f;
1768 lp->dxsuflo = dxsuflo;
1769 lp->mii = mii;
1770 lp->chip_version = chip_version;
1771 lp->msg_enable = pcnet32_debug;
1772 if ((cards_found >= MAX_UNITS) ||
1773 (options[cards_found] >= sizeof(options_mapping)))
1774 lp->options = PCNET32_PORT_ASEL;
1775 else
1776 lp->options = options_mapping[options[cards_found]];
1777 lp->mii_if.dev = dev;
1778 lp->mii_if.mdio_read = mdio_read;
1779 lp->mii_if.mdio_write = mdio_write;
1780
1781 /* napi.weight is used in both the napi and non-napi cases */
1782 lp->napi.weight = lp->rx_ring_size / 2;
1783
1784 netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2);
1785
1786 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1787 ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1788 lp->options |= PCNET32_PORT_FD;
1789
1790 lp->a = a;
1791
1792 /* prior to register_netdev, dev->name is not yet correct */
1793 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1794 ret = -ENOMEM;
1795 goto err_free_ring;
1796 }
1797 /* detect special T1/E1 WAN card by checking for MAC address */
1798 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0 &&
1799 dev->dev_addr[2] == 0x75)
1800 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1801
1802 lp->init_block->mode = cpu_to_le16(0x0003); /* Disable Rx and Tx. */
1803 lp->init_block->tlen_rlen =
1804 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
1805 for (i = 0; i < 6; i++)
1806 lp->init_block->phys_addr[i] = dev->dev_addr[i];
1807 lp->init_block->filter[0] = 0x00000000;
1808 lp->init_block->filter[1] = 0x00000000;
1809 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
1810 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
1811
1812 /* switch pcnet32 to 32bit mode */
1813 a->write_bcr(ioaddr, 20, 2);
1814
1815 a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
1816 a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
1817
1818 if (pdev) { /* use the IRQ provided by PCI */
1819 dev->irq = pdev->irq;
1820 if (pcnet32_debug & NETIF_MSG_PROBE)
1821 pr_cont(" assigned IRQ %d\n", dev->irq);
1822 } else {
1823 unsigned long irq_mask = probe_irq_on();
1824
1825 /*
1826 * To auto-IRQ we enable the initialization-done and DMA error
1827 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1828 * boards will work.
1829 */
1830 /* Trigger an initialization just for the interrupt. */
1831 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
1832 mdelay(1);
1833
1834 dev->irq = probe_irq_off(irq_mask);
1835 if (!dev->irq) {
1836 if (pcnet32_debug & NETIF_MSG_PROBE)
1837 pr_cont(", failed to detect IRQ line\n");
1838 ret = -ENODEV;
1839 goto err_free_ring;
1840 }
1841 if (pcnet32_debug & NETIF_MSG_PROBE)
1842 pr_cont(", probed IRQ %d\n", dev->irq);
1843 }
1844
1845 /* Set the mii phy_id so that we can query the link state */
1846 if (lp->mii) {
1847 /* lp->phycount and lp->phymask are set to 0 by memset above */
1848
1849 lp->mii_if.phy_id = ((lp->a->read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1850 /* scan for PHYs */
1851 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1852 unsigned short id1, id2;
1853
1854 id1 = mdio_read(dev, i, MII_PHYSID1);
1855 if (id1 == 0xffff)
1856 continue;
1857 id2 = mdio_read(dev, i, MII_PHYSID2);
1858 if (id2 == 0xffff)
1859 continue;
1860 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1861 continue; /* 79C971 & 79C972 have phantom phy at id 31 */
1862 lp->phycount++;
1863 lp->phymask |= (1 << i);
1864 lp->mii_if.phy_id = i;
1865 if (pcnet32_debug & NETIF_MSG_PROBE)
1866 pr_info("Found PHY %04x:%04x at address %d\n",
1867 id1, id2, i);
1868 }
1869 lp->a->write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1870 if (lp->phycount > 1)
1871 lp->options |= PCNET32_PORT_MII;
1872 }
1873
1874 init_timer(&lp->watchdog_timer);
1875 lp->watchdog_timer.data = (unsigned long)dev;
1876 lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1877
1878 /* The PCNET32-specific entries in the device structure. */
1879 dev->netdev_ops = &pcnet32_netdev_ops;
1880 dev->ethtool_ops = &pcnet32_ethtool_ops;
1881 dev->watchdog_timeo = (5 * HZ);
1882
1883 /* Fill in the generic fields of the device structure. */
1884 if (register_netdev(dev))
1885 goto err_free_ring;
1886
1887 if (pdev) {
1888 pci_set_drvdata(pdev, dev);
1889 } else {
1890 lp->next = pcnet32_dev;
1891 pcnet32_dev = dev;
1892 }
1893
1894 if (pcnet32_debug & NETIF_MSG_PROBE)
1895 pr_info("%s: registered as %s\n", dev->name, lp->name);
1896 cards_found++;
1897
1898 /* enable LED writes */
1899 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1900
1901 return 0;
1902
1903 err_free_ring:
1904 pcnet32_free_ring(dev);
1905 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
1906 lp->init_block, lp->init_dma_addr);
1907 err_free_netdev:
1908 free_netdev(dev);
1909 err_release_region:
1910 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1911 return ret;
1912 }
1913
1914 /* if any allocation fails, caller must also call pcnet32_free_ring */
1915 static int pcnet32_alloc_ring(struct net_device *dev, const char *name)
1916 {
1917 struct pcnet32_private *lp = netdev_priv(dev);
1918
1919 lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
1920 sizeof(struct pcnet32_tx_head) *
1921 lp->tx_ring_size,
1922 &lp->tx_ring_dma_addr);
1923 if (lp->tx_ring == NULL) {
1924 netif_err(lp, drv, dev, "Consistent memory allocation failed\n");
1925 return -ENOMEM;
1926 }
1927
1928 lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
1929 sizeof(struct pcnet32_rx_head) *
1930 lp->rx_ring_size,
1931 &lp->rx_ring_dma_addr);
1932 if (lp->rx_ring == NULL) {
1933 netif_err(lp, drv, dev, "Consistent memory allocation failed\n");
1934 return -ENOMEM;
1935 }
1936
1937 lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
1938 GFP_ATOMIC);
1939 if (!lp->tx_dma_addr) {
1940 netif_err(lp, drv, dev, "Memory allocation failed\n");
1941 return -ENOMEM;
1942 }
1943
1944 lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
1945 GFP_ATOMIC);
1946 if (!lp->rx_dma_addr) {
1947 netif_err(lp, drv, dev, "Memory allocation failed\n");
1948 return -ENOMEM;
1949 }
1950
1951 lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
1952 GFP_ATOMIC);
1953 if (!lp->tx_skbuff) {
1954 netif_err(lp, drv, dev, "Memory allocation failed\n");
1955 return -ENOMEM;
1956 }
1957
1958 lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
1959 GFP_ATOMIC);
1960 if (!lp->rx_skbuff) {
1961 netif_err(lp, drv, dev, "Memory allocation failed\n");
1962 return -ENOMEM;
1963 }
1964
1965 return 0;
1966 }
1967
1968 static void pcnet32_free_ring(struct net_device *dev)
1969 {
1970 struct pcnet32_private *lp = netdev_priv(dev);
1971
1972 kfree(lp->tx_skbuff);
1973 lp->tx_skbuff = NULL;
1974
1975 kfree(lp->rx_skbuff);
1976 lp->rx_skbuff = NULL;
1977
1978 kfree(lp->tx_dma_addr);
1979 lp->tx_dma_addr = NULL;
1980
1981 kfree(lp->rx_dma_addr);
1982 lp->rx_dma_addr = NULL;
1983
1984 if (lp->tx_ring) {
1985 pci_free_consistent(lp->pci_dev,
1986 sizeof(struct pcnet32_tx_head) *
1987 lp->tx_ring_size, lp->tx_ring,
1988 lp->tx_ring_dma_addr);
1989 lp->tx_ring = NULL;
1990 }
1991
1992 if (lp->rx_ring) {
1993 pci_free_consistent(lp->pci_dev,
1994 sizeof(struct pcnet32_rx_head) *
1995 lp->rx_ring_size, lp->rx_ring,
1996 lp->rx_ring_dma_addr);
1997 lp->rx_ring = NULL;
1998 }
1999 }
2000
2001 static int pcnet32_open(struct net_device *dev)
2002 {
2003 struct pcnet32_private *lp = netdev_priv(dev);
2004 struct pci_dev *pdev = lp->pci_dev;
2005 unsigned long ioaddr = dev->base_addr;
2006 u16 val;
2007 int i;
2008 int rc;
2009 unsigned long flags;
2010
2011 if (request_irq(dev->irq, pcnet32_interrupt,
2012 lp->shared_irq ? IRQF_SHARED : 0, dev->name,
2013 (void *)dev)) {
2014 return -EAGAIN;
2015 }
2016
2017 spin_lock_irqsave(&lp->lock, flags);
2018 /* Check for a valid station address */
2019 if (!is_valid_ether_addr(dev->dev_addr)) {
2020 rc = -EINVAL;
2021 goto err_free_irq;
2022 }
2023
2024 /* Reset the PCNET32 */
2025 lp->a->reset(ioaddr);
2026
2027 /* switch pcnet32 to 32bit mode */
2028 lp->a->write_bcr(ioaddr, 20, 2);
2029
2030 netif_printk(lp, ifup, KERN_DEBUG, dev,
2031 "%s() irq %d tx/rx rings %#x/%#x init %#x\n",
2032 __func__, dev->irq, (u32) (lp->tx_ring_dma_addr),
2033 (u32) (lp->rx_ring_dma_addr),
2034 (u32) (lp->init_dma_addr));
2035
2036 /* set/reset autoselect bit */
2037 val = lp->a->read_bcr(ioaddr, 2) & ~2;
2038 if (lp->options & PCNET32_PORT_ASEL)
2039 val |= 2;
2040 lp->a->write_bcr(ioaddr, 2, val);
2041
2042 /* handle full duplex setting */
2043 if (lp->mii_if.full_duplex) {
2044 val = lp->a->read_bcr(ioaddr, 9) & ~3;
2045 if (lp->options & PCNET32_PORT_FD) {
2046 val |= 1;
2047 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
2048 val |= 2;
2049 } else if (lp->options & PCNET32_PORT_ASEL) {
2050 /* workaround of xSeries250, turn on for 79C975 only */
2051 if (lp->chip_version == 0x2627)
2052 val |= 3;
2053 }
2054 lp->a->write_bcr(ioaddr, 9, val);
2055 }
2056
2057 /* set/reset GPSI bit in test register */
2058 val = lp->a->read_csr(ioaddr, 124) & ~0x10;
2059 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
2060 val |= 0x10;
2061 lp->a->write_csr(ioaddr, 124, val);
2062
2063 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
2064 if (pdev && pdev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2065 (pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
2066 pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
2067 if (lp->options & PCNET32_PORT_ASEL) {
2068 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
2069 netif_printk(lp, link, KERN_DEBUG, dev,
2070 "Setting 100Mb-Full Duplex\n");
2071 }
2072 }
2073 if (lp->phycount < 2) {
2074 /*
2075 * 24 Jun 2004 according AMD, in order to change the PHY,
2076 * DANAS (or DISPM for 79C976) must be set; then select the speed,
2077 * duplex, and/or enable auto negotiation, and clear DANAS
2078 */
2079 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
2080 lp->a->write_bcr(ioaddr, 32,
2081 lp->a->read_bcr(ioaddr, 32) | 0x0080);
2082 /* disable Auto Negotiation, set 10Mpbs, HD */
2083 val = lp->a->read_bcr(ioaddr, 32) & ~0xb8;
2084 if (lp->options & PCNET32_PORT_FD)
2085 val |= 0x10;
2086 if (lp->options & PCNET32_PORT_100)
2087 val |= 0x08;
2088 lp->a->write_bcr(ioaddr, 32, val);
2089 } else {
2090 if (lp->options & PCNET32_PORT_ASEL) {
2091 lp->a->write_bcr(ioaddr, 32,
2092 lp->a->read_bcr(ioaddr,
2093 32) | 0x0080);
2094 /* enable auto negotiate, setup, disable fd */
2095 val = lp->a->read_bcr(ioaddr, 32) & ~0x98;
2096 val |= 0x20;
2097 lp->a->write_bcr(ioaddr, 32, val);
2098 }
2099 }
2100 } else {
2101 int first_phy = -1;
2102 u16 bmcr;
2103 u32 bcr9;
2104 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
2105
2106 /*
2107 * There is really no good other way to handle multiple PHYs
2108 * other than turning off all automatics
2109 */
2110 val = lp->a->read_bcr(ioaddr, 2);
2111 lp->a->write_bcr(ioaddr, 2, val & ~2);
2112 val = lp->a->read_bcr(ioaddr, 32);
2113 lp->a->write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */
2114
2115 if (!(lp->options & PCNET32_PORT_ASEL)) {
2116 /* setup ecmd */
2117 ecmd.port = PORT_MII;
2118 ecmd.transceiver = XCVR_INTERNAL;
2119 ecmd.autoneg = AUTONEG_DISABLE;
2120 ethtool_cmd_speed_set(&ecmd,
2121 (lp->options & PCNET32_PORT_100) ?
2122 SPEED_100 : SPEED_10);
2123 bcr9 = lp->a->read_bcr(ioaddr, 9);
2124
2125 if (lp->options & PCNET32_PORT_FD) {
2126 ecmd.duplex = DUPLEX_FULL;
2127 bcr9 |= (1 << 0);
2128 } else {
2129 ecmd.duplex = DUPLEX_HALF;
2130 bcr9 |= ~(1 << 0);
2131 }
2132 lp->a->write_bcr(ioaddr, 9, bcr9);
2133 }
2134
2135 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2136 if (lp->phymask & (1 << i)) {
2137 /* isolate all but the first PHY */
2138 bmcr = mdio_read(dev, i, MII_BMCR);
2139 if (first_phy == -1) {
2140 first_phy = i;
2141 mdio_write(dev, i, MII_BMCR,
2142 bmcr & ~BMCR_ISOLATE);
2143 } else {
2144 mdio_write(dev, i, MII_BMCR,
2145 bmcr | BMCR_ISOLATE);
2146 }
2147 /* use mii_ethtool_sset to setup PHY */
2148 lp->mii_if.phy_id = i;
2149 ecmd.phy_address = i;
2150 if (lp->options & PCNET32_PORT_ASEL) {
2151 mii_ethtool_gset(&lp->mii_if, &ecmd);
2152 ecmd.autoneg = AUTONEG_ENABLE;
2153 }
2154 mii_ethtool_sset(&lp->mii_if, &ecmd);
2155 }
2156 }
2157 lp->mii_if.phy_id = first_phy;
2158 netif_info(lp, link, dev, "Using PHY number %d\n", first_phy);
2159 }
2160
2161 #ifdef DO_DXSUFLO
2162 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
2163 val = lp->a->read_csr(ioaddr, CSR3);
2164 val |= 0x40;
2165 lp->a->write_csr(ioaddr, CSR3, val);
2166 }
2167 #endif
2168
2169 lp->init_block->mode =
2170 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2171 pcnet32_load_multicast(dev);
2172
2173 if (pcnet32_init_ring(dev)) {
2174 rc = -ENOMEM;
2175 goto err_free_ring;
2176 }
2177
2178 napi_enable(&lp->napi);
2179
2180 /* Re-initialize the PCNET32, and start it when done. */
2181 lp->a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
2182 lp->a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
2183
2184 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2185 lp->a->write_csr(ioaddr, CSR0, CSR0_INIT);
2186
2187 netif_start_queue(dev);
2188
2189 if (lp->chip_version >= PCNET32_79C970A) {
2190 /* Print the link status and start the watchdog */
2191 pcnet32_check_media(dev, 1);
2192 mod_timer(&lp->watchdog_timer, PCNET32_WATCHDOG_TIMEOUT);
2193 }
2194
2195 i = 0;
2196 while (i++ < 100)
2197 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON)
2198 break;
2199 /*
2200 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2201 * reports that doing so triggers a bug in the '974.
2202 */
2203 lp->a->write_csr(ioaddr, CSR0, CSR0_NORMAL);
2204
2205 netif_printk(lp, ifup, KERN_DEBUG, dev,
2206 "pcnet32 open after %d ticks, init block %#x csr0 %4.4x\n",
2207 i,
2208 (u32) (lp->init_dma_addr),
2209 lp->a->read_csr(ioaddr, CSR0));
2210
2211 spin_unlock_irqrestore(&lp->lock, flags);
2212
2213 return 0; /* Always succeed */
2214
2215 err_free_ring:
2216 /* free any allocated skbuffs */
2217 pcnet32_purge_rx_ring(dev);
2218
2219 /*
2220 * Switch back to 16bit mode to avoid problems with dumb
2221 * DOS packet driver after a warm reboot
2222 */
2223 lp->a->write_bcr(ioaddr, 20, 4);
2224
2225 err_free_irq:
2226 spin_unlock_irqrestore(&lp->lock, flags);
2227 free_irq(dev->irq, dev);
2228 return rc;
2229 }
2230
2231 /*
2232 * The LANCE has been halted for one reason or another (busmaster memory
2233 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2234 * etc.). Modern LANCE variants always reload their ring-buffer
2235 * configuration when restarted, so we must reinitialize our ring
2236 * context before restarting. As part of this reinitialization,
2237 * find all packets still on the Tx ring and pretend that they had been
2238 * sent (in effect, drop the packets on the floor) - the higher-level
2239 * protocols will time out and retransmit. It'd be better to shuffle
2240 * these skbs to a temp list and then actually re-Tx them after
2241 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
2242 */
2243
2244 static void pcnet32_purge_tx_ring(struct net_device *dev)
2245 {
2246 struct pcnet32_private *lp = netdev_priv(dev);
2247 int i;
2248
2249 for (i = 0; i < lp->tx_ring_size; i++) {
2250 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2251 wmb(); /* Make sure adapter sees owner change */
2252 if (lp->tx_skbuff[i]) {
2253 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2254 lp->tx_skbuff[i]->len,
2255 PCI_DMA_TODEVICE);
2256 dev_kfree_skb_any(lp->tx_skbuff[i]);
2257 }
2258 lp->tx_skbuff[i] = NULL;
2259 lp->tx_dma_addr[i] = 0;
2260 }
2261 }
2262
2263 /* Initialize the PCNET32 Rx and Tx rings. */
2264 static int pcnet32_init_ring(struct net_device *dev)
2265 {
2266 struct pcnet32_private *lp = netdev_priv(dev);
2267 int i;
2268
2269 lp->tx_full = 0;
2270 lp->cur_rx = lp->cur_tx = 0;
2271 lp->dirty_rx = lp->dirty_tx = 0;
2272
2273 for (i = 0; i < lp->rx_ring_size; i++) {
2274 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2275 if (rx_skbuff == NULL) {
2276 lp->rx_skbuff[i] = dev_alloc_skb(PKT_BUF_SKB);
2277 rx_skbuff = lp->rx_skbuff[i];
2278 if (!rx_skbuff) {
2279 /* there is not much we can do at this point */
2280 netif_err(lp, drv, dev, "%s dev_alloc_skb failed\n",
2281 __func__);
2282 return -1;
2283 }
2284 skb_reserve(rx_skbuff, NET_IP_ALIGN);
2285 }
2286
2287 rmb();
2288 if (lp->rx_dma_addr[i] == 0)
2289 lp->rx_dma_addr[i] =
2290 pci_map_single(lp->pci_dev, rx_skbuff->data,
2291 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
2292 lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]);
2293 lp->rx_ring[i].buf_length = cpu_to_le16(NEG_BUF_SIZE);
2294 wmb(); /* Make sure owner changes after all others are visible */
2295 lp->rx_ring[i].status = cpu_to_le16(0x8000);
2296 }
2297 /* The Tx buffer address is filled in as needed, but we do need to clear
2298 * the upper ownership bit. */
2299 for (i = 0; i < lp->tx_ring_size; i++) {
2300 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2301 wmb(); /* Make sure adapter sees owner change */
2302 lp->tx_ring[i].base = 0;
2303 lp->tx_dma_addr[i] = 0;
2304 }
2305
2306 lp->init_block->tlen_rlen =
2307 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
2308 for (i = 0; i < 6; i++)
2309 lp->init_block->phys_addr[i] = dev->dev_addr[i];
2310 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
2311 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
2312 wmb(); /* Make sure all changes are visible */
2313 return 0;
2314 }
2315
2316 /* the pcnet32 has been issued a stop or reset. Wait for the stop bit
2317 * then flush the pending transmit operations, re-initialize the ring,
2318 * and tell the chip to initialize.
2319 */
2320 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
2321 {
2322 struct pcnet32_private *lp = netdev_priv(dev);
2323 unsigned long ioaddr = dev->base_addr;
2324 int i;
2325
2326 /* wait for stop */
2327 for (i = 0; i < 100; i++)
2328 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_STOP)
2329 break;
2330
2331 if (i >= 100)
2332 netif_err(lp, drv, dev, "%s timed out waiting for stop\n",
2333 __func__);
2334
2335 pcnet32_purge_tx_ring(dev);
2336 if (pcnet32_init_ring(dev))
2337 return;
2338
2339 /* ReInit Ring */
2340 lp->a->write_csr(ioaddr, CSR0, CSR0_INIT);
2341 i = 0;
2342 while (i++ < 1000)
2343 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON)
2344 break;
2345
2346 lp->a->write_csr(ioaddr, CSR0, csr0_bits);
2347 }
2348
2349 static void pcnet32_tx_timeout(struct net_device *dev)
2350 {
2351 struct pcnet32_private *lp = netdev_priv(dev);
2352 unsigned long ioaddr = dev->base_addr, flags;
2353
2354 spin_lock_irqsave(&lp->lock, flags);
2355 /* Transmitter timeout, serious problems. */
2356 if (pcnet32_debug & NETIF_MSG_DRV)
2357 pr_err("%s: transmit timed out, status %4.4x, resetting\n",
2358 dev->name, lp->a->read_csr(ioaddr, CSR0));
2359 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
2360 dev->stats.tx_errors++;
2361 if (netif_msg_tx_err(lp)) {
2362 int i;
2363 printk(KERN_DEBUG
2364 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2365 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2366 lp->cur_rx);
2367 for (i = 0; i < lp->rx_ring_size; i++)
2368 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2369 le32_to_cpu(lp->rx_ring[i].base),
2370 (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2371 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2372 le16_to_cpu(lp->rx_ring[i].status));
2373 for (i = 0; i < lp->tx_ring_size; i++)
2374 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2375 le32_to_cpu(lp->tx_ring[i].base),
2376 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2377 le32_to_cpu(lp->tx_ring[i].misc),
2378 le16_to_cpu(lp->tx_ring[i].status));
2379 printk("\n");
2380 }
2381 pcnet32_restart(dev, CSR0_NORMAL);
2382
2383 dev->trans_start = jiffies; /* prevent tx timeout */
2384 netif_wake_queue(dev);
2385
2386 spin_unlock_irqrestore(&lp->lock, flags);
2387 }
2388
2389 static netdev_tx_t pcnet32_start_xmit(struct sk_buff *skb,
2390 struct net_device *dev)
2391 {
2392 struct pcnet32_private *lp = netdev_priv(dev);
2393 unsigned long ioaddr = dev->base_addr;
2394 u16 status;
2395 int entry;
2396 unsigned long flags;
2397
2398 spin_lock_irqsave(&lp->lock, flags);
2399
2400 netif_printk(lp, tx_queued, KERN_DEBUG, dev,
2401 "%s() called, csr0 %4.4x\n",
2402 __func__, lp->a->read_csr(ioaddr, CSR0));
2403
2404 /* Default status -- will not enable Successful-TxDone
2405 * interrupt when that option is available to us.
2406 */
2407 status = 0x8300;
2408
2409 /* Fill in a Tx ring entry */
2410
2411 /* Mask to ring buffer boundary. */
2412 entry = lp->cur_tx & lp->tx_mod_mask;
2413
2414 /* Caution: the write order is important here, set the status
2415 * with the "ownership" bits last. */
2416
2417 lp->tx_ring[entry].length = cpu_to_le16(-skb->len);
2418
2419 lp->tx_ring[entry].misc = 0x00000000;
2420
2421 lp->tx_skbuff[entry] = skb;
2422 lp->tx_dma_addr[entry] =
2423 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
2424 lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]);
2425 wmb(); /* Make sure owner changes after all others are visible */
2426 lp->tx_ring[entry].status = cpu_to_le16(status);
2427
2428 lp->cur_tx++;
2429 dev->stats.tx_bytes += skb->len;
2430
2431 /* Trigger an immediate send poll. */
2432 lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
2433
2434 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2435 lp->tx_full = 1;
2436 netif_stop_queue(dev);
2437 }
2438 spin_unlock_irqrestore(&lp->lock, flags);
2439 return NETDEV_TX_OK;
2440 }
2441
2442 /* The PCNET32 interrupt handler. */
2443 static irqreturn_t
2444 pcnet32_interrupt(int irq, void *dev_id)
2445 {
2446 struct net_device *dev = dev_id;
2447 struct pcnet32_private *lp;
2448 unsigned long ioaddr;
2449 u16 csr0;
2450 int boguscnt = max_interrupt_work;
2451
2452 ioaddr = dev->base_addr;
2453 lp = netdev_priv(dev);
2454
2455 spin_lock(&lp->lock);
2456
2457 csr0 = lp->a->read_csr(ioaddr, CSR0);
2458 while ((csr0 & 0x8f00) && --boguscnt >= 0) {
2459 if (csr0 == 0xffff)
2460 break; /* PCMCIA remove happened */
2461 /* Acknowledge all of the current interrupt sources ASAP. */
2462 lp->a->write_csr(ioaddr, CSR0, csr0 & ~0x004f);
2463
2464 netif_printk(lp, intr, KERN_DEBUG, dev,
2465 "interrupt csr0=%#2.2x new csr=%#2.2x\n",
2466 csr0, lp->a->read_csr(ioaddr, CSR0));
2467
2468 /* Log misc errors. */
2469 if (csr0 & 0x4000)
2470 dev->stats.tx_errors++; /* Tx babble. */
2471 if (csr0 & 0x1000) {
2472 /*
2473 * This happens when our receive ring is full. This
2474 * shouldn't be a problem as we will see normal rx
2475 * interrupts for the frames in the receive ring. But
2476 * there are some PCI chipsets (I can reproduce this
2477 * on SP3G with Intel saturn chipset) which have
2478 * sometimes problems and will fill up the receive
2479 * ring with error descriptors. In this situation we
2480 * don't get a rx interrupt, but a missed frame
2481 * interrupt sooner or later.
2482 */
2483 dev->stats.rx_errors++; /* Missed a Rx frame. */
2484 }
2485 if (csr0 & 0x0800) {
2486 netif_err(lp, drv, dev, "Bus master arbitration failure, status %4.4x\n",
2487 csr0);
2488 /* unlike for the lance, there is no restart needed */
2489 }
2490 if (napi_schedule_prep(&lp->napi)) {
2491 u16 val;
2492 /* set interrupt masks */
2493 val = lp->a->read_csr(ioaddr, CSR3);
2494 val |= 0x5f00;
2495 lp->a->write_csr(ioaddr, CSR3, val);
2496
2497 __napi_schedule(&lp->napi);
2498 break;
2499 }
2500 csr0 = lp->a->read_csr(ioaddr, CSR0);
2501 }
2502
2503 netif_printk(lp, intr, KERN_DEBUG, dev,
2504 "exiting interrupt, csr0=%#4.4x\n",
2505 lp->a->read_csr(ioaddr, CSR0));
2506
2507 spin_unlock(&lp->lock);
2508
2509 return IRQ_HANDLED;
2510 }
2511
2512 static int pcnet32_close(struct net_device *dev)
2513 {
2514 unsigned long ioaddr = dev->base_addr;
2515 struct pcnet32_private *lp = netdev_priv(dev);
2516 unsigned long flags;
2517
2518 del_timer_sync(&lp->watchdog_timer);
2519
2520 netif_stop_queue(dev);
2521 napi_disable(&lp->napi);
2522
2523 spin_lock_irqsave(&lp->lock, flags);
2524
2525 dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112);
2526
2527 netif_printk(lp, ifdown, KERN_DEBUG, dev,
2528 "Shutting down ethercard, status was %2.2x\n",
2529 lp->a->read_csr(ioaddr, CSR0));
2530
2531 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2532 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
2533
2534 /*
2535 * Switch back to 16bit mode to avoid problems with dumb
2536 * DOS packet driver after a warm reboot
2537 */
2538 lp->a->write_bcr(ioaddr, 20, 4);
2539
2540 spin_unlock_irqrestore(&lp->lock, flags);
2541
2542 free_irq(dev->irq, dev);
2543
2544 spin_lock_irqsave(&lp->lock, flags);
2545
2546 pcnet32_purge_rx_ring(dev);
2547 pcnet32_purge_tx_ring(dev);
2548
2549 spin_unlock_irqrestore(&lp->lock, flags);
2550
2551 return 0;
2552 }
2553
2554 static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
2555 {
2556 struct pcnet32_private *lp = netdev_priv(dev);
2557 unsigned long ioaddr = dev->base_addr;
2558 unsigned long flags;
2559
2560 spin_lock_irqsave(&lp->lock, flags);
2561 dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112);
2562 spin_unlock_irqrestore(&lp->lock, flags);
2563
2564 return &dev->stats;
2565 }
2566
2567 /* taken from the sunlance driver, which it took from the depca driver */
2568 static void pcnet32_load_multicast(struct net_device *dev)
2569 {
2570 struct pcnet32_private *lp = netdev_priv(dev);
2571 volatile struct pcnet32_init_block *ib = lp->init_block;
2572 volatile __le16 *mcast_table = (__le16 *)ib->filter;
2573 struct netdev_hw_addr *ha;
2574 unsigned long ioaddr = dev->base_addr;
2575 int i;
2576 u32 crc;
2577
2578 /* set all multicast bits */
2579 if (dev->flags & IFF_ALLMULTI) {
2580 ib->filter[0] = cpu_to_le32(~0U);
2581 ib->filter[1] = cpu_to_le32(~0U);
2582 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2583 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2584 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2585 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
2586 return;
2587 }
2588 /* clear the multicast filter */
2589 ib->filter[0] = 0;
2590 ib->filter[1] = 0;
2591
2592 /* Add addresses */
2593 netdev_for_each_mc_addr(ha, dev) {
2594 crc = ether_crc_le(6, ha->addr);
2595 crc = crc >> 26;
2596 mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf));
2597 }
2598 for (i = 0; i < 4; i++)
2599 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER + i,
2600 le16_to_cpu(mcast_table[i]));
2601 }
2602
2603 /*
2604 * Set or clear the multicast filter for this adaptor.
2605 */
2606 static void pcnet32_set_multicast_list(struct net_device *dev)
2607 {
2608 unsigned long ioaddr = dev->base_addr, flags;
2609 struct pcnet32_private *lp = netdev_priv(dev);
2610 int csr15, suspended;
2611
2612 spin_lock_irqsave(&lp->lock, flags);
2613 suspended = pcnet32_suspend(dev, &flags, 0);
2614 csr15 = lp->a->read_csr(ioaddr, CSR15);
2615 if (dev->flags & IFF_PROMISC) {
2616 /* Log any net taps. */
2617 netif_info(lp, hw, dev, "Promiscuous mode enabled\n");
2618 lp->init_block->mode =
2619 cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
2620 7);
2621 lp->a->write_csr(ioaddr, CSR15, csr15 | 0x8000);
2622 } else {
2623 lp->init_block->mode =
2624 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2625 lp->a->write_csr(ioaddr, CSR15, csr15 & 0x7fff);
2626 pcnet32_load_multicast(dev);
2627 }
2628
2629 if (suspended) {
2630 int csr5;
2631 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2632 csr5 = lp->a->read_csr(ioaddr, CSR5);
2633 lp->a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
2634 } else {
2635 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
2636 pcnet32_restart(dev, CSR0_NORMAL);
2637 netif_wake_queue(dev);
2638 }
2639
2640 spin_unlock_irqrestore(&lp->lock, flags);
2641 }
2642
2643 /* This routine assumes that the lp->lock is held */
2644 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2645 {
2646 struct pcnet32_private *lp = netdev_priv(dev);
2647 unsigned long ioaddr = dev->base_addr;
2648 u16 val_out;
2649
2650 if (!lp->mii)
2651 return 0;
2652
2653 lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2654 val_out = lp->a->read_bcr(ioaddr, 34);
2655
2656 return val_out;
2657 }
2658
2659 /* This routine assumes that the lp->lock is held */
2660 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2661 {
2662 struct pcnet32_private *lp = netdev_priv(dev);
2663 unsigned long ioaddr = dev->base_addr;
2664
2665 if (!lp->mii)
2666 return;
2667
2668 lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2669 lp->a->write_bcr(ioaddr, 34, val);
2670 }
2671
2672 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2673 {
2674 struct pcnet32_private *lp = netdev_priv(dev);
2675 int rc;
2676 unsigned long flags;
2677
2678 /* SIOC[GS]MIIxxx ioctls */
2679 if (lp->mii) {
2680 spin_lock_irqsave(&lp->lock, flags);
2681 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2682 spin_unlock_irqrestore(&lp->lock, flags);
2683 } else {
2684 rc = -EOPNOTSUPP;
2685 }
2686
2687 return rc;
2688 }
2689
2690 static int pcnet32_check_otherphy(struct net_device *dev)
2691 {
2692 struct pcnet32_private *lp = netdev_priv(dev);
2693 struct mii_if_info mii = lp->mii_if;
2694 u16 bmcr;
2695 int i;
2696
2697 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2698 if (i == lp->mii_if.phy_id)
2699 continue; /* skip active phy */
2700 if (lp->phymask & (1 << i)) {
2701 mii.phy_id = i;
2702 if (mii_link_ok(&mii)) {
2703 /* found PHY with active link */
2704 netif_info(lp, link, dev, "Using PHY number %d\n",
2705 i);
2706
2707 /* isolate inactive phy */
2708 bmcr =
2709 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2710 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2711 bmcr | BMCR_ISOLATE);
2712
2713 /* de-isolate new phy */
2714 bmcr = mdio_read(dev, i, MII_BMCR);
2715 mdio_write(dev, i, MII_BMCR,
2716 bmcr & ~BMCR_ISOLATE);
2717
2718 /* set new phy address */
2719 lp->mii_if.phy_id = i;
2720 return 1;
2721 }
2722 }
2723 }
2724 return 0;
2725 }
2726
2727 /*
2728 * Show the status of the media. Similar to mii_check_media however it
2729 * correctly shows the link speed for all (tested) pcnet32 variants.
2730 * Devices with no mii just report link state without speed.
2731 *
2732 * Caller is assumed to hold and release the lp->lock.
2733 */
2734
2735 static void pcnet32_check_media(struct net_device *dev, int verbose)
2736 {
2737 struct pcnet32_private *lp = netdev_priv(dev);
2738 int curr_link;
2739 int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2740 u32 bcr9;
2741
2742 if (lp->mii) {
2743 curr_link = mii_link_ok(&lp->mii_if);
2744 } else {
2745 ulong ioaddr = dev->base_addr; /* card base I/O address */
2746 curr_link = (lp->a->read_bcr(ioaddr, 4) != 0xc0);
2747 }
2748 if (!curr_link) {
2749 if (prev_link || verbose) {
2750 netif_carrier_off(dev);
2751 netif_info(lp, link, dev, "link down\n");
2752 }
2753 if (lp->phycount > 1) {
2754 curr_link = pcnet32_check_otherphy(dev);
2755 prev_link = 0;
2756 }
2757 } else if (verbose || !prev_link) {
2758 netif_carrier_on(dev);
2759 if (lp->mii) {
2760 if (netif_msg_link(lp)) {
2761 struct ethtool_cmd ecmd = {
2762 .cmd = ETHTOOL_GSET };
2763 mii_ethtool_gset(&lp->mii_if, &ecmd);
2764 netdev_info(dev, "link up, %uMbps, %s-duplex\n",
2765 ethtool_cmd_speed(&ecmd),
2766 (ecmd.duplex == DUPLEX_FULL)
2767 ? "full" : "half");
2768 }
2769 bcr9 = lp->a->read_bcr(dev->base_addr, 9);
2770 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2771 if (lp->mii_if.full_duplex)
2772 bcr9 |= (1 << 0);
2773 else
2774 bcr9 &= ~(1 << 0);
2775 lp->a->write_bcr(dev->base_addr, 9, bcr9);
2776 }
2777 } else {
2778 netif_info(lp, link, dev, "link up\n");
2779 }
2780 }
2781 }
2782
2783 /*
2784 * Check for loss of link and link establishment.
2785 * Can not use mii_check_media because it does nothing if mode is forced.
2786 */
2787
2788 static void pcnet32_watchdog(struct net_device *dev)
2789 {
2790 struct pcnet32_private *lp = netdev_priv(dev);
2791 unsigned long flags;
2792
2793 /* Print the link status if it has changed */
2794 spin_lock_irqsave(&lp->lock, flags);
2795 pcnet32_check_media(dev, 0);
2796 spin_unlock_irqrestore(&lp->lock, flags);
2797
2798 mod_timer(&lp->watchdog_timer, round_jiffies(PCNET32_WATCHDOG_TIMEOUT));
2799 }
2800
2801 static int pcnet32_pm_suspend(struct pci_dev *pdev, pm_message_t state)
2802 {
2803 struct net_device *dev = pci_get_drvdata(pdev);
2804
2805 if (netif_running(dev)) {
2806 netif_device_detach(dev);
2807 pcnet32_close(dev);
2808 }
2809 pci_save_state(pdev);
2810 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2811 return 0;
2812 }
2813
2814 static int pcnet32_pm_resume(struct pci_dev *pdev)
2815 {
2816 struct net_device *dev = pci_get_drvdata(pdev);
2817
2818 pci_set_power_state(pdev, PCI_D0);
2819 pci_restore_state(pdev);
2820
2821 if (netif_running(dev)) {
2822 pcnet32_open(dev);
2823 netif_device_attach(dev);
2824 }
2825 return 0;
2826 }
2827
2828 static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
2829 {
2830 struct net_device *dev = pci_get_drvdata(pdev);
2831
2832 if (dev) {
2833 struct pcnet32_private *lp = netdev_priv(dev);
2834
2835 unregister_netdev(dev);
2836 pcnet32_free_ring(dev);
2837 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
2838 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
2839 lp->init_block, lp->init_dma_addr);
2840 free_netdev(dev);
2841 pci_disable_device(pdev);
2842 pci_set_drvdata(pdev, NULL);
2843 }
2844 }
2845
2846 static struct pci_driver pcnet32_driver = {
2847 .name = DRV_NAME,
2848 .probe = pcnet32_probe_pci,
2849 .remove = __devexit_p(pcnet32_remove_one),
2850 .id_table = pcnet32_pci_tbl,
2851 .suspend = pcnet32_pm_suspend,
2852 .resume = pcnet32_pm_resume,
2853 };
2854
2855 /* An additional parameter that may be passed in... */
2856 static int debug = -1;
2857 static int tx_start_pt = -1;
2858 static int pcnet32_have_pci;
2859
2860 module_param(debug, int, 0);
2861 MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2862 module_param(max_interrupt_work, int, 0);
2863 MODULE_PARM_DESC(max_interrupt_work,
2864 DRV_NAME " maximum events handled per interrupt");
2865 module_param(rx_copybreak, int, 0);
2866 MODULE_PARM_DESC(rx_copybreak,
2867 DRV_NAME " copy breakpoint for copy-only-tiny-frames");
2868 module_param(tx_start_pt, int, 0);
2869 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2870 module_param(pcnet32vlb, int, 0);
2871 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2872 module_param_array(options, int, NULL, 0);
2873 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2874 module_param_array(full_duplex, int, NULL, 0);
2875 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2876 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2877 module_param_array(homepna, int, NULL, 0);
2878 MODULE_PARM_DESC(homepna,
2879 DRV_NAME
2880 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
2881
2882 MODULE_AUTHOR("Thomas Bogendoerfer");
2883 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
2884 MODULE_LICENSE("GPL");
2885
2886 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
2887
2888 static int __init pcnet32_init_module(void)
2889 {
2890 pr_info("%s", version);
2891
2892 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
2893
2894 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
2895 tx_start = tx_start_pt;
2896
2897 /* find the PCI devices */
2898 if (!pci_register_driver(&pcnet32_driver))
2899 pcnet32_have_pci = 1;
2900
2901 /* should we find any remaining VLbus devices ? */
2902 if (pcnet32vlb)
2903 pcnet32_probe_vlbus(pcnet32_portlist);
2904
2905 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
2906 pr_info("%d cards_found\n", cards_found);
2907
2908 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
2909 }
2910
2911 static void __exit pcnet32_cleanup_module(void)
2912 {
2913 struct net_device *next_dev;
2914
2915 while (pcnet32_dev) {
2916 struct pcnet32_private *lp = netdev_priv(pcnet32_dev);
2917 next_dev = lp->next;
2918 unregister_netdev(pcnet32_dev);
2919 pcnet32_free_ring(pcnet32_dev);
2920 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
2921 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
2922 lp->init_block, lp->init_dma_addr);
2923 free_netdev(pcnet32_dev);
2924 pcnet32_dev = next_dev;
2925 }
2926
2927 if (pcnet32_have_pci)
2928 pci_unregister_driver(&pcnet32_driver);
2929 }
2930
2931 module_init(pcnet32_init_module);
2932 module_exit(pcnet32_cleanup_module);
2933
2934 /*
2935 * Local variables:
2936 * c-indent-level: 4
2937 * tab-width: 8
2938 * End:
2939 */